Init Commit

Monorepo for Rust support of VA416XX family of radiation hardened MCUs

va416xx/src/spw/clkdiv.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CLKDIV` reader"]
+pub type R = crate::R<ClkdivSpec>;
+#[doc = "Register `CLKDIV` writer"]
+pub type W = crate::W<ClkdivSpec>;
+#[doc = "Field `CLKDIVRUN` reader - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"]
+pub type ClkdivrunR = crate::FieldReader;
+#[doc = "Field `CLKDIVRUN` writer - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"]
+pub type ClkdivrunW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CLKDIVSTART` reader - 8-bit Clock divisor value used for the clock-divider during startup"]
+pub type ClkdivstartR = crate::FieldReader;
+#[doc = "Field `CLKDIVSTART` writer - 8-bit Clock divisor value used for the clock-divider during startup"]
+pub type ClkdivstartW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"]
+    #[inline(always)]
+    pub fn clkdivrun(&self) -> ClkdivrunR {
+        ClkdivrunR::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"]
+    #[inline(always)]
+    pub fn clkdivstart(&self) -> ClkdivstartR {
+        ClkdivstartR::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"]
+    #[inline(always)]
+    #[must_use]
+    pub fn clkdivrun(&mut self) -> ClkdivrunW<ClkdivSpec> {
+        ClkdivrunW::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"]
+    #[inline(always)]
+    #[must_use]
+    pub fn clkdivstart(&mut self) -> ClkdivstartW<ClkdivSpec> {
+        ClkdivstartW::new(self, 8)
+    }
+}
+#[doc = "Clock Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ClkdivSpec;
+impl crate::RegisterSpec for ClkdivSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
+impl crate::Readable for ClkdivSpec {}
+#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
+impl crate::Writable for ClkdivSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKDIV to value 0x0909"]
+impl crate::Resettable for ClkdivSpec {
+    const RESET_VALUE: u32 = 0x0909;
+}

va416xx/src/spw/ctrl.rs

@@ -0,0 +1,366 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CtrlSpec>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CtrlSpec>;
+#[doc = "Field `LD` reader - Disable the SpaceWire CODEC"]
+pub type LdR = crate::BitReader;
+#[doc = "Field `LD` writer - Disable the SpaceWire CODEC"]
+pub type LdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LS` reader - Start the link"]
+pub type LsR = crate::BitReader;
+#[doc = "Field `LS` writer - Start the link"]
+pub type LsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AS` reader - Automatically start the link when a NULL has been received"]
+pub type AsR = crate::BitReader;
+#[doc = "Field `AS` writer - Automatically start the link when a NULL has been received"]
+pub type AsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IE` reader - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"]
+pub type IeR = crate::BitReader;
+#[doc = "Field `IE` writer - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"]
+pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TI` reader - The host can generate a tick by writing a one to this field"]
+pub type TiR = crate::BitReader;
+#[doc = "Field `TI` writer - The host can generate a tick by writing a one to this field"]
+pub type TiW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PM` reader - Enable Promiscuous mode"]
+pub type PmR = crate::BitReader;
+#[doc = "Field `PM` writer - Enable Promiscuous mode"]
+pub type PmW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RS` reader - Make complete reset of the SpaceWire node. Self-clearing"]
+pub type RsR = crate::BitReader;
+#[doc = "Field `RS` writer - Make complete reset of the SpaceWire node. Self-clearing"]
+pub type RsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TQ` reader - Generate interrupt when a valid time-code is received"]
+pub type TqR = crate::BitReader;
+#[doc = "Field `TQ` writer - Generate interrupt when a valid time-code is received"]
+pub type TqW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LI` reader - Generate interrupt when link error occurs"]
+pub type LiR = crate::BitReader;
+#[doc = "Field `LI` writer - Generate interrupt when link error occurs"]
+pub type LiW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TT` reader - Enable time-code transmissions"]
+pub type TtR = crate::BitReader;
+#[doc = "Field `TT` writer - Enable time-code transmissions"]
+pub type TtW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TR` reader - Enable time-code receptions"]
+pub type TrR = crate::BitReader;
+#[doc = "Field `TR` writer - Enable time-code receptions"]
+pub type TrW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TF` reader - Time-code Flag Filter"]
+pub type TfR = crate::BitReader;
+#[doc = "Field `TF` writer - Time-code Flag Filter"]
+pub type TfW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TL` reader - Transmitter Enable Lock Control"]
+pub type TlR = crate::BitReader;
+#[doc = "Field `TL` writer - Transmitter Enable Lock Control"]
+pub type TlW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PE` reader - SpW Plug-and-Play Enable"]
+pub type PeR = crate::BitReader;
+#[doc = "Field `PE` writer - SpW Plug-and-Play Enable"]
+pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RE` reader - Enable RMAP command handler"]
+pub type ReR = crate::BitReader;
+#[doc = "Field `RE` writer - Enable RMAP command handler"]
+pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RD` reader - If set only one RMAP buffer is used"]
+pub type RdR = crate::BitReader;
+#[doc = "Field `RD` writer - If set only one RMAP buffer is used"]
+pub type RdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PNPA` reader - SpW Plug-and-Play Available"]
+pub type PnpaR = crate::FieldReader;
+#[doc = "Field `NP` reader - Disable port force"]
+pub type NpR = crate::BitReader;
+#[doc = "Field `NP` writer - Disable port force"]
+pub type NpW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PS` reader - Selects the active port when the no port force bit is zero"]
+pub type PsR = crate::BitReader;
+#[doc = "Field `PS` writer - Selects the active port when the no port force bit is zero"]
+pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LE` reader - Loop-back Enable"]
+pub type LeR = crate::BitReader;
+#[doc = "Field `LE` writer - Loop-back Enable"]
+pub type LeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ID` reader - Interrupt distribution available"]
+pub type IdR = crate::BitReader;
+#[doc = "Field `CC` reader - CCSDS/CCITT CRC-16"]
+pub type CcR = crate::BitReader;
+#[doc = "Field `PO` reader - The number of available SpaceWire ports minus one"]
+pub type PoR = crate::BitReader;
+#[doc = "Field `NCH` reader - Number of DMA Channels minus one"]
+pub type NchR = crate::FieldReader;
+#[doc = "Field `RC` reader - Reads as 1 if RMAP CRC is enabled in the core"]
+pub type RcR = crate::BitReader;
+#[doc = "Field `RX` reader - Reads as 1 if unaligned writes are available for the receiver"]
+pub type RxR = crate::BitReader;
+#[doc = "Field `RA` reader - Reads as 1 if the RMAP command handler is available"]
+pub type RaR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Disable the SpaceWire CODEC"]
+    #[inline(always)]
+    pub fn ld(&self) -> LdR {
+        LdR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Start the link"]
+    #[inline(always)]
+    pub fn ls(&self) -> LsR {
+        LsR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Automatically start the link when a NULL has been received"]
+    #[inline(always)]
+    pub fn as_(&self) -> AsR {
+        AsR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"]
+    #[inline(always)]
+    pub fn ie(&self) -> IeR {
+        IeR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"]
+    #[inline(always)]
+    pub fn ti(&self) -> TiR {
+        TiR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Enable Promiscuous mode"]
+    #[inline(always)]
+    pub fn pm(&self) -> PmR {
+        PmR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"]
+    #[inline(always)]
+    pub fn rs(&self) -> RsR {
+        RsR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"]
+    #[inline(always)]
+    pub fn tq(&self) -> TqR {
+        TqR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Generate interrupt when link error occurs"]
+    #[inline(always)]
+    pub fn li(&self) -> LiR {
+        LiR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Enable time-code transmissions"]
+    #[inline(always)]
+    pub fn tt(&self) -> TtR {
+        TtR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Enable time-code receptions"]
+    #[inline(always)]
+    pub fn tr(&self) -> TrR {
+        TrR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Time-code Flag Filter"]
+    #[inline(always)]
+    pub fn tf(&self) -> TfR {
+        TfR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Transmitter Enable Lock Control"]
+    #[inline(always)]
+    pub fn tl(&self) -> TlR {
+        TlR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 15 - SpW Plug-and-Play Enable"]
+    #[inline(always)]
+    pub fn pe(&self) -> PeR {
+        PeR::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Enable RMAP command handler"]
+    #[inline(always)]
+    pub fn re(&self) -> ReR {
+        ReR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - If set only one RMAP buffer is used"]
+    #[inline(always)]
+    pub fn rd(&self) -> RdR {
+        RdR::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bits 18:19 - SpW Plug-and-Play Available"]
+    #[inline(always)]
+    pub fn pnpa(&self) -> PnpaR {
+        PnpaR::new(((self.bits >> 18) & 3) as u8)
+    }
+    #[doc = "Bit 20 - Disable port force"]
+    #[inline(always)]
+    pub fn np(&self) -> NpR {
+        NpR::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"]
+    #[inline(always)]
+    pub fn ps(&self) -> PsR {
+        PsR::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Loop-back Enable"]
+    #[inline(always)]
+    pub fn le(&self) -> LeR {
+        LeR::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Interrupt distribution available"]
+    #[inline(always)]
+    pub fn id(&self) -> IdR {
+        IdR::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - CCSDS/CCITT CRC-16"]
+    #[inline(always)]
+    pub fn cc(&self) -> CcR {
+        CcR::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The number of available SpaceWire ports minus one"]
+    #[inline(always)]
+    pub fn po(&self) -> PoR {
+        PoR::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bits 27:28 - Number of DMA Channels minus one"]
+    #[inline(always)]
+    pub fn nch(&self) -> NchR {
+        NchR::new(((self.bits >> 27) & 3) as u8)
+    }
+    #[doc = "Bit 29 - Reads as 1 if RMAP CRC is enabled in the core"]
+    #[inline(always)]
+    pub fn rc(&self) -> RcR {
+        RcR::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - Reads as 1 if unaligned writes are available for the receiver"]
+    #[inline(always)]
+    pub fn rx(&self) -> RxR {
+        RxR::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Reads as 1 if the RMAP command handler is available"]
+    #[inline(always)]
+    pub fn ra(&self) -> RaR {
+        RaR::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable the SpaceWire CODEC"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ld(&mut self) -> LdW<CtrlSpec> {
+        LdW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Start the link"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ls(&mut self) -> LsW<CtrlSpec> {
+        LsW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Automatically start the link when a NULL has been received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn as_(&mut self) -> AsW<CtrlSpec> {
+        AsW::new(self, 2)
+    }
+    #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ie(&mut self) -> IeW<CtrlSpec> {
+        IeW::new(self, 3)
+    }
+    #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ti(&mut self) -> TiW<CtrlSpec> {
+        TiW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Enable Promiscuous mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pm(&mut self) -> PmW<CtrlSpec> {
+        PmW::new(self, 5)
+    }
+    #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rs(&mut self) -> RsW<CtrlSpec> {
+        RsW::new(self, 6)
+    }
+    #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tq(&mut self) -> TqW<CtrlSpec> {
+        TqW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Generate interrupt when link error occurs"]
+    #[inline(always)]
+    #[must_use]
+    pub fn li(&mut self) -> LiW<CtrlSpec> {
+        LiW::new(self, 9)
+    }
+    #[doc = "Bit 10 - Enable time-code transmissions"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tt(&mut self) -> TtW<CtrlSpec> {
+        TtW::new(self, 10)
+    }
+    #[doc = "Bit 11 - Enable time-code receptions"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tr(&mut self) -> TrW<CtrlSpec> {
+        TrW::new(self, 11)
+    }
+    #[doc = "Bit 12 - Time-code Flag Filter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tf(&mut self) -> TfW<CtrlSpec> {
+        TfW::new(self, 12)
+    }
+    #[doc = "Bit 13 - Transmitter Enable Lock Control"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tl(&mut self) -> TlW<CtrlSpec> {
+        TlW::new(self, 13)
+    }
+    #[doc = "Bit 15 - SpW Plug-and-Play Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pe(&mut self) -> PeW<CtrlSpec> {
+        PeW::new(self, 15)
+    }
+    #[doc = "Bit 16 - Enable RMAP command handler"]
+    #[inline(always)]
+    #[must_use]
+    pub fn re(&mut self) -> ReW<CtrlSpec> {
+        ReW::new(self, 16)
+    }
+    #[doc = "Bit 17 - If set only one RMAP buffer is used"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rd(&mut self) -> RdW<CtrlSpec> {
+        RdW::new(self, 17)
+    }
+    #[doc = "Bit 20 - Disable port force"]
+    #[inline(always)]
+    #[must_use]
+    pub fn np(&mut self) -> NpW<CtrlSpec> {
+        NpW::new(self, 20)
+    }
+    #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ps(&mut self) -> PsW<CtrlSpec> {
+        PsW::new(self, 21)
+    }
+    #[doc = "Bit 22 - Loop-back Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn le(&mut self) -> LeW<CtrlSpec> {
+        LeW::new(self, 22)
+    }
+}
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlSpec;
+impl crate::RegisterSpec for CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0xa201_0004"]
+impl crate::Resettable for CtrlSpec {
+    const RESET_VALUE: u32 = 0xa201_0004;
+}

va416xx/src/spw/defaddr.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DEFADDR` reader"]
+pub type R = crate::R<DefaddrSpec>;
+#[doc = "Register `DEFADDR` writer"]
+pub type W = crate::W<DefaddrSpec>;
+#[doc = "Field `DEFADDR` reader - 8-bit node address used for node identification on the SpaceWire network"]
+pub type DefaddrR = crate::FieldReader;
+#[doc = "Field `DEFADDR` writer - 8-bit node address used for node identification on the SpaceWire network"]
+pub type DefaddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `DEFMASK` reader - 8-bit default mask used for node identification on the SpaceWire network"]
+pub type DefmaskR = crate::FieldReader;
+#[doc = "Field `DEFMASK` writer - 8-bit default mask used for node identification on the SpaceWire network"]
+pub type DefmaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"]
+    #[inline(always)]
+    pub fn defaddr(&self) -> DefaddrR {
+        DefaddrR::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"]
+    #[inline(always)]
+    pub fn defmask(&self) -> DefmaskR {
+        DefmaskR::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"]
+    #[inline(always)]
+    #[must_use]
+    pub fn defaddr(&mut self) -> DefaddrW<DefaddrSpec> {
+        DefaddrW::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"]
+    #[inline(always)]
+    #[must_use]
+    pub fn defmask(&mut self) -> DefmaskW<DefaddrSpec> {
+        DefmaskW::new(self, 8)
+    }
+}
+#[doc = "Node Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`defaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`defaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DefaddrSpec;
+impl crate::RegisterSpec for DefaddrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`defaddr::R`](R) reader structure"]
+impl crate::Readable for DefaddrSpec {}
+#[doc = "`write(|w| ..)` method takes [`defaddr::W`](W) writer structure"]
+impl crate::Writable for DefaddrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DEFADDR to value 0xfe"]
+impl crate::Resettable for DefaddrSpec {
+    const RESET_VALUE: u32 = 0xfe;
+}

va416xx/src/spw/dkey.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `DKEY` reader"]
+pub type R = crate::R<DkeySpec>;
+#[doc = "Register `DKEY` writer"]
+pub type W = crate::W<DkeySpec>;
+#[doc = "Field `DESTKEY` reader - RMAP destination key"]
+pub type DestkeyR = crate::FieldReader;
+#[doc = "Field `DESTKEY` writer - RMAP destination key"]
+pub type DestkeyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - RMAP destination key"]
+    #[inline(always)]
+    pub fn destkey(&self) -> DestkeyR {
+        DestkeyR::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - RMAP destination key"]
+    #[inline(always)]
+    #[must_use]
+    pub fn destkey(&mut self) -> DestkeyW<DkeySpec> {
+        DestkeyW::new(self, 0)
+    }
+}
+#[doc = "Destination Key\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dkey::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dkey::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DkeySpec;
+impl crate::RegisterSpec for DkeySpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dkey::R`](R) reader structure"]
+impl crate::Readable for DkeySpec {}
+#[doc = "`write(|w| ..)` method takes [`dkey::W`](W) writer structure"]
+impl crate::Writable for DkeySpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DKEY to value 0"]
+impl crate::Resettable for DkeySpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/dmaaddr0.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DMAADDR0` reader"]
+pub type R = crate::R<Dmaaddr0Spec>;
+#[doc = "Register `DMAADDR0` writer"]
+pub type W = crate::W<Dmaaddr0Spec>;
+#[doc = "Field `ADDR` reader - Address"]
+pub type AddrR = crate::FieldReader;
+#[doc = "Field `ADDR` writer - Address"]
+pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `MASK` reader - Mask"]
+pub type MaskR = crate::FieldReader;
+#[doc = "Field `MASK` writer - Mask"]
+pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Address"]
+    #[inline(always)]
+    pub fn addr(&self) -> AddrR {
+        AddrR::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Mask"]
+    #[inline(always)]
+    pub fn mask(&self) -> MaskR {
+        MaskR::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Address"]
+    #[inline(always)]
+    #[must_use]
+    pub fn addr(&mut self) -> AddrW<Dmaaddr0Spec> {
+        AddrW::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Mask"]
+    #[inline(always)]
+    #[must_use]
+    pub fn mask(&mut self) -> MaskW<Dmaaddr0Spec> {
+        MaskW::new(self, 8)
+    }
+}
+#[doc = "DMA Receiver Table Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaaddr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaaddr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dmaaddr0Spec;
+impl crate::RegisterSpec for Dmaaddr0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dmaaddr0::R`](R) reader structure"]
+impl crate::Readable for Dmaaddr0Spec {}
+#[doc = "`write(|w| ..)` method takes [`dmaaddr0::W`](W) writer structure"]
+impl crate::Writable for Dmaaddr0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMAADDR0 to value 0"]
+impl crate::Resettable for Dmaaddr0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/dmactrl0.rs

@@ -0,0 +1,384 @@
+#[doc = "Register `DMACTRL0` reader"]
+pub type R = crate::R<Dmactrl0Spec>;
+#[doc = "Register `DMACTRL0` writer"]
+pub type W = crate::W<Dmactrl0Spec>;
+#[doc = "Field `TE` reader - Write a one to this bit each time new descriptors are activated in the table"]
+pub type TeR = crate::BitReader;
+#[doc = "Field `TE` writer - Write a one to this bit each time new descriptors are activated in the table"]
+pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RE` reader - Packets are allowed to be received to this channel"]
+pub type ReR = crate::BitReader;
+#[doc = "Field `RE` writer - Packets are allowed to be received to this channel"]
+pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TI` reader - An interrupt will be generated each time a packet is transmitted"]
+pub type TiR = crate::BitReader;
+#[doc = "Field `TI` writer - An interrupt will be generated each time a packet is transmitted"]
+pub type TiW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RI` reader - An interrupt will be generated each time a packet has been received"]
+pub type RiR = crate::BitReader;
+#[doc = "Field `RI` writer - An interrupt will be generated each time a packet has been received"]
+pub type RiW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AI` reader - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"]
+pub type AiR = crate::BitReader;
+#[doc = "Field `AI` writer - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"]
+pub type AiW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PS` reader - Set each time a packet has been sent"]
+pub type PsR = crate::BitReader;
+#[doc = "Field `PS` writer - Set each time a packet has been sent"]
+pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PR` reader - Set each time a packet has been received"]
+pub type PrR = crate::BitReader;
+#[doc = "Field `PR` writer - Set each time a packet has been received"]
+pub type PrW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TA` reader - An error response was detected on the AHB bus - DMA transmit"]
+pub type TaR = crate::BitReader;
+#[doc = "Field `TA` writer - An error response was detected on the AHB bus - DMA transmit"]
+pub type TaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RA` reader - An error response was detected on the AHB bus - DMA receive"]
+pub type RaR = crate::BitReader;
+#[doc = "Field `RA` writer - An error response was detected on the AHB bus - DMA receive"]
+pub type RaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AT` reader - Abort the currently transmitting packet and disable transmissions"]
+pub type AtR = crate::BitReader;
+#[doc = "Field `RX` reader - Reception to the DMA channel is currently active"]
+pub type RxR = crate::BitReader;
+#[doc = "Field `RD` reader - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"]
+pub type RdR = crate::BitReader;
+#[doc = "Field `RD` writer - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"]
+pub type RdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NS` reader - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"]
+pub type NsR = crate::BitReader;
+#[doc = "Field `NS` writer - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"]
+pub type NsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EN` reader - Enable Address"]
+pub type EnR = crate::BitReader;
+#[doc = "Field `EN` writer - Enable Address"]
+pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SA` reader - Strip Address"]
+pub type SaR = crate::BitReader;
+#[doc = "Field `SA` writer - Strip Address"]
+pub type SaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SP` reader - Strip PID"]
+pub type SpR = crate::BitReader;
+#[doc = "Field `SP` writer - Strip PID"]
+pub type SpW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LE` reader - Disable transmitter when a link error occurs"]
+pub type LeR = crate::BitReader;
+#[doc = "Field `LE` writer - Disable transmitter when a link error occurs"]
+pub type LeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TL` reader - Transmit Enable Lock"]
+pub type TlR = crate::BitReader;
+#[doc = "Field `TL` writer - Transmit Enable Lock"]
+pub type TlW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TP` reader - Transmit Packet IRQ"]
+pub type TpR = crate::BitReader;
+#[doc = "Field `TP` writer - Transmit Packet IRQ"]
+pub type TpW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RP` reader - Receive Packet IRQ"]
+pub type RpR = crate::BitReader;
+#[doc = "Field `RP` writer - Receive Packet IRQ"]
+pub type RpW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IT` reader - Interrupt code transmit enable on truncation"]
+pub type ItR = crate::BitReader;
+#[doc = "Field `IT` writer - Interrupt code transmit enable on truncation"]
+pub type ItW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IE` reader - Interrupt code transmit enable on EEP"]
+pub type IeR = crate::BitReader;
+#[doc = "Field `IE` writer - Interrupt code transmit enable on EEP"]
+pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TR` reader - Truncated"]
+pub type TrR = crate::BitReader;
+#[doc = "Field `TR` writer - Truncated"]
+pub type TrW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EP` reader - EEP Termination"]
+pub type EpR = crate::BitReader;
+#[doc = "Field `EP` writer - EEP Termination"]
+pub type EpW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INTNUM` reader - Interrupt number used for this channel"]
+pub type IntnumR = crate::FieldReader;
+#[doc = "Field `INTNUM` writer - Interrupt number used for this channel"]
+pub type IntnumW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+impl R {
+    #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"]
+    #[inline(always)]
+    pub fn te(&self) -> TeR {
+        TeR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Packets are allowed to be received to this channel"]
+    #[inline(always)]
+    pub fn re(&self) -> ReR {
+        ReR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"]
+    #[inline(always)]
+    pub fn ti(&self) -> TiR {
+        TiR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"]
+    #[inline(always)]
+    pub fn ri(&self) -> RiR {
+        RiR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"]
+    #[inline(always)]
+    pub fn ai(&self) -> AiR {
+        AiR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set each time a packet has been sent"]
+    #[inline(always)]
+    pub fn ps(&self) -> PsR {
+        PsR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set each time a packet has been received"]
+    #[inline(always)]
+    pub fn pr(&self) -> PrR {
+        PrR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"]
+    #[inline(always)]
+    pub fn ta(&self) -> TaR {
+        TaR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"]
+    #[inline(always)]
+    pub fn ra(&self) -> RaR {
+        RaR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Abort the currently transmitting packet and disable transmissions"]
+    #[inline(always)]
+    pub fn at(&self) -> AtR {
+        AtR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Reception to the DMA channel is currently active"]
+    #[inline(always)]
+    pub fn rx(&self) -> RxR {
+        RxR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"]
+    #[inline(always)]
+    pub fn rd(&self) -> RdR {
+        RdR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"]
+    #[inline(always)]
+    pub fn ns(&self) -> NsR {
+        NsR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Enable Address"]
+    #[inline(always)]
+    pub fn en(&self) -> EnR {
+        EnR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - Strip Address"]
+    #[inline(always)]
+    pub fn sa(&self) -> SaR {
+        SaR::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Strip PID"]
+    #[inline(always)]
+    pub fn sp(&self) -> SpR {
+        SpR::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Disable transmitter when a link error occurs"]
+    #[inline(always)]
+    pub fn le(&self) -> LeR {
+        LeR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Transmit Enable Lock"]
+    #[inline(always)]
+    pub fn tl(&self) -> TlR {
+        TlR::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Transmit Packet IRQ"]
+    #[inline(always)]
+    pub fn tp(&self) -> TpR {
+        TpR::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Receive Packet IRQ"]
+    #[inline(always)]
+    pub fn rp(&self) -> RpR {
+        RpR::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - Interrupt code transmit enable on truncation"]
+    #[inline(always)]
+    pub fn it(&self) -> ItR {
+        ItR::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Interrupt code transmit enable on EEP"]
+    #[inline(always)]
+    pub fn ie(&self) -> IeR {
+        IeR::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Truncated"]
+    #[inline(always)]
+    pub fn tr(&self) -> TrR {
+        TrR::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - EEP Termination"]
+    #[inline(always)]
+    pub fn ep(&self) -> EpR {
+        EpR::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bits 26:31 - Interrupt number used for this channel"]
+    #[inline(always)]
+    pub fn intnum(&self) -> IntnumR {
+        IntnumR::new(((self.bits >> 26) & 0x3f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"]
+    #[inline(always)]
+    #[must_use]
+    pub fn te(&mut self) -> TeW<Dmactrl0Spec> {
+        TeW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Packets are allowed to be received to this channel"]
+    #[inline(always)]
+    #[must_use]
+    pub fn re(&mut self) -> ReW<Dmactrl0Spec> {
+        ReW::new(self, 1)
+    }
+    #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ti(&mut self) -> TiW<Dmactrl0Spec> {
+        TiW::new(self, 2)
+    }
+    #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ri(&mut self) -> RiW<Dmactrl0Spec> {
+        RiW::new(self, 3)
+    }
+    #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ai(&mut self) -> AiW<Dmactrl0Spec> {
+        AiW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set each time a packet has been sent"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ps(&mut self) -> PsW<Dmactrl0Spec> {
+        PsW::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set each time a packet has been received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pr(&mut self) -> PrW<Dmactrl0Spec> {
+        PrW::new(self, 6)
+    }
+    #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ta(&mut self) -> TaW<Dmactrl0Spec> {
+        TaW::new(self, 7)
+    }
+    #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ra(&mut self) -> RaW<Dmactrl0Spec> {
+        RaW::new(self, 8)
+    }
+    #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rd(&mut self) -> RdW<Dmactrl0Spec> {
+        RdW::new(self, 11)
+    }
+    #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ns(&mut self) -> NsW<Dmactrl0Spec> {
+        NsW::new(self, 12)
+    }
+    #[doc = "Bit 13 - Enable Address"]
+    #[inline(always)]
+    #[must_use]
+    pub fn en(&mut self) -> EnW<Dmactrl0Spec> {
+        EnW::new(self, 13)
+    }
+    #[doc = "Bit 14 - Strip Address"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sa(&mut self) -> SaW<Dmactrl0Spec> {
+        SaW::new(self, 14)
+    }
+    #[doc = "Bit 15 - Strip PID"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sp(&mut self) -> SpW<Dmactrl0Spec> {
+        SpW::new(self, 15)
+    }
+    #[doc = "Bit 16 - Disable transmitter when a link error occurs"]
+    #[inline(always)]
+    #[must_use]
+    pub fn le(&mut self) -> LeW<Dmactrl0Spec> {
+        LeW::new(self, 16)
+    }
+    #[doc = "Bit 17 - Transmit Enable Lock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tl(&mut self) -> TlW<Dmactrl0Spec> {
+        TlW::new(self, 17)
+    }
+    #[doc = "Bit 18 - Transmit Packet IRQ"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tp(&mut self) -> TpW<Dmactrl0Spec> {
+        TpW::new(self, 18)
+    }
+    #[doc = "Bit 19 - Receive Packet IRQ"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rp(&mut self) -> RpW<Dmactrl0Spec> {
+        RpW::new(self, 19)
+    }
+    #[doc = "Bit 20 - Interrupt code transmit enable on truncation"]
+    #[inline(always)]
+    #[must_use]
+    pub fn it(&mut self) -> ItW<Dmactrl0Spec> {
+        ItW::new(self, 20)
+    }
+    #[doc = "Bit 21 - Interrupt code transmit enable on EEP"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ie(&mut self) -> IeW<Dmactrl0Spec> {
+        IeW::new(self, 21)
+    }
+    #[doc = "Bit 22 - Truncated"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tr(&mut self) -> TrW<Dmactrl0Spec> {
+        TrW::new(self, 22)
+    }
+    #[doc = "Bit 23 - EEP Termination"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ep(&mut self) -> EpW<Dmactrl0Spec> {
+        EpW::new(self, 23)
+    }
+    #[doc = "Bits 26:31 - Interrupt number used for this channel"]
+    #[inline(always)]
+    #[must_use]
+    pub fn intnum(&mut self) -> IntnumW<Dmactrl0Spec> {
+        IntnumW::new(self, 26)
+    }
+}
+#[doc = "DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dmactrl0Spec;
+impl crate::RegisterSpec for Dmactrl0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dmactrl0::R`](R) reader structure"]
+impl crate::Readable for Dmactrl0Spec {}
+#[doc = "`write(|w| ..)` method takes [`dmactrl0::W`](W) writer structure"]
+impl crate::Writable for Dmactrl0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMACTRL0 to value 0"]
+impl crate::Resettable for Dmactrl0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/dmamaxlen0.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `DMAMAXLEN0` reader"]
+pub type R = crate::R<Dmamaxlen0Spec>;
+#[doc = "Register `DMAMAXLEN0` writer"]
+pub type W = crate::W<Dmamaxlen0Spec>;
+#[doc = "Field `RXMAXLEN` reader - Receiver packet maximum length in bytes"]
+pub type RxmaxlenR = crate::FieldReader<u32>;
+#[doc = "Field `RXMAXLEN` writer - Receiver packet maximum length in bytes"]
+pub type RxmaxlenW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
+impl R {
+    #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"]
+    #[inline(always)]
+    pub fn rxmaxlen(&self) -> RxmaxlenR {
+        RxmaxlenR::new((self.bits >> 2) & 0x007f_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxmaxlen(&mut self) -> RxmaxlenW<Dmamaxlen0Spec> {
+        RxmaxlenW::new(self, 2)
+    }
+}
+#[doc = "DMA RX Maximum Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmamaxlen0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmamaxlen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dmamaxlen0Spec;
+impl crate::RegisterSpec for Dmamaxlen0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dmamaxlen0::R`](R) reader structure"]
+impl crate::Readable for Dmamaxlen0Spec {}
+#[doc = "`write(|w| ..)` method takes [`dmamaxlen0::W`](W) writer structure"]
+impl crate::Writable for Dmamaxlen0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMAMAXLEN0 to value 0"]
+impl crate::Resettable for Dmamaxlen0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/dmarxdesc0.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DMARXDESC0` reader"]
+pub type R = crate::R<Dmarxdesc0Spec>;
+#[doc = "Register `DMARXDESC0` writer"]
+pub type W = crate::W<Dmarxdesc0Spec>;
+#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"]
+pub type DescselR = crate::FieldReader;
+#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"]
+pub type DescselW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"]
+pub type DescbaseaddrR = crate::FieldReader<u32>;
+#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"]
+pub type DescbaseaddrW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 3:9 - Offset into the descriptor table"]
+    #[inline(always)]
+    pub fn descsel(&self) -> DescselR {
+        DescselR::new(((self.bits >> 3) & 0x7f) as u8)
+    }
+    #[doc = "Bits 10:31 - Sets the base address of the descriptor table"]
+    #[inline(always)]
+    pub fn descbaseaddr(&self) -> DescbaseaddrR {
+        DescbaseaddrR::new((self.bits >> 10) & 0x003f_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 3:9 - Offset into the descriptor table"]
+    #[inline(always)]
+    #[must_use]
+    pub fn descsel(&mut self) -> DescselW<Dmarxdesc0Spec> {
+        DescselW::new(self, 3)
+    }
+    #[doc = "Bits 10:31 - Sets the base address of the descriptor table"]
+    #[inline(always)]
+    #[must_use]
+    pub fn descbaseaddr(&mut self) -> DescbaseaddrW<Dmarxdesc0Spec> {
+        DescbaseaddrW::new(self, 10)
+    }
+}
+#[doc = "DMA Receiver Table Destination Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxdesc0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmarxdesc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dmarxdesc0Spec;
+impl crate::RegisterSpec for Dmarxdesc0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dmarxdesc0::R`](R) reader structure"]
+impl crate::Readable for Dmarxdesc0Spec {}
+#[doc = "`write(|w| ..)` method takes [`dmarxdesc0::W`](W) writer structure"]
+impl crate::Writable for Dmarxdesc0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMARXDESC0 to value 0"]
+impl crate::Resettable for Dmarxdesc0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/dmatxdesc0.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DMATXDESC0` reader"]
+pub type R = crate::R<Dmatxdesc0Spec>;
+#[doc = "Register `DMATXDESC0` writer"]
+pub type W = crate::W<Dmatxdesc0Spec>;
+#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"]
+pub type DescselR = crate::FieldReader;
+#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"]
+pub type DescselW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"]
+pub type DescbaseaddrR = crate::FieldReader<u32>;
+#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"]
+pub type DescbaseaddrW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 4:9 - Offset into the descriptor table"]
+    #[inline(always)]
+    pub fn descsel(&self) -> DescselR {
+        DescselR::new(((self.bits >> 4) & 0x3f) as u8)
+    }
+    #[doc = "Bits 10:31 - Sets the base address of the descriptor table"]
+    #[inline(always)]
+    pub fn descbaseaddr(&self) -> DescbaseaddrR {
+        DescbaseaddrR::new((self.bits >> 10) & 0x003f_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 4:9 - Offset into the descriptor table"]
+    #[inline(always)]
+    #[must_use]
+    pub fn descsel(&mut self) -> DescselW<Dmatxdesc0Spec> {
+        DescselW::new(self, 4)
+    }
+    #[doc = "Bits 10:31 - Sets the base address of the descriptor table"]
+    #[inline(always)]
+    #[must_use]
+    pub fn descbaseaddr(&mut self) -> DescbaseaddrW<Dmatxdesc0Spec> {
+        DescbaseaddrW::new(self, 10)
+    }
+}
+#[doc = "DMA Transmitter Descriptor Table Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxdesc0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatxdesc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dmatxdesc0Spec;
+impl crate::RegisterSpec for Dmatxdesc0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dmatxdesc0::R`](R) reader structure"]
+impl crate::Readable for Dmatxdesc0Spec {}
+#[doc = "`write(|w| ..)` method takes [`dmatxdesc0::W`](W) writer structure"]
+impl crate::Writable for Dmatxdesc0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMATXDESC0 to value 0"]
+impl crate::Resettable for Dmatxdesc0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/sts.rs

@@ -0,0 +1,205 @@
+#[doc = "Register `STS` reader"]
+pub type R = crate::R<StsSpec>;
+#[doc = "Register `STS` writer"]
+pub type W = crate::W<StsSpec>;
+#[doc = "Field `TO` reader - A new time count value was received"]
+pub type ToR = crate::BitReader;
+#[doc = "Field `TO` writer - A new time count value was received"]
+pub type ToW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CE` reader - Credit has occurred"]
+pub type CeR = crate::BitReader;
+#[doc = "Field `CE` writer - Credit has occurred"]
+pub type CeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ER` reader - Escape error has occurred"]
+pub type ErR = crate::BitReader;
+#[doc = "Field `ER` writer - Escape error has occurred"]
+pub type ErW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DE` reader - Disconnection error has occurred"]
+pub type DeR = crate::BitReader;
+#[doc = "Field `DE` writer - Disconnection error has occurred"]
+pub type DeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PE` reader - Parity error has occurred"]
+pub type PeR = crate::BitReader;
+#[doc = "Field `PE` writer - Parity error has occurred"]
+pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WE` reader - A synchronization problem has occurred when receiving NChars"]
+pub type WeR = crate::BitReader;
+#[doc = "Field `WE` writer - A synchronization problem has occurred when receiving NChars"]
+pub type WeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IA` reader - Packet is received with an invalid destination address field"]
+pub type IaR = crate::BitReader;
+#[doc = "Field `IA` writer - Packet is received with an invalid destination address field"]
+pub type IaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EE` reader - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"]
+pub type EeR = crate::BitReader;
+#[doc = "Field `EE` writer - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"]
+pub type EeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AP` reader - Active port"]
+pub type ApR = crate::BitReader;
+#[doc = "Field `AP` writer - Active port"]
+pub type ApW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LS` reader - Link State"]
+pub type LsR = crate::FieldReader;
+#[doc = "Field `LS` writer - Link State"]
+pub type LsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `NTXD` reader - Number of Transmit Descriptors"]
+pub type NtxdR = crate::FieldReader;
+#[doc = "Field `NTXD` writer - Number of Transmit Descriptors"]
+pub type NtxdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `NRXD` reader - Number of Receive Descriptors"]
+pub type NrxdR = crate::FieldReader;
+#[doc = "Field `NRXD` writer - Number of Receive Descriptors"]
+pub type NrxdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 0 - A new time count value was received"]
+    #[inline(always)]
+    pub fn to(&self) -> ToR {
+        ToR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Credit has occurred"]
+    #[inline(always)]
+    pub fn ce(&self) -> CeR {
+        CeR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Escape error has occurred"]
+    #[inline(always)]
+    pub fn er(&self) -> ErR {
+        ErR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Disconnection error has occurred"]
+    #[inline(always)]
+    pub fn de(&self) -> DeR {
+        DeR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Parity error has occurred"]
+    #[inline(always)]
+    pub fn pe(&self) -> PeR {
+        PeR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"]
+    #[inline(always)]
+    pub fn we(&self) -> WeR {
+        WeR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Packet is received with an invalid destination address field"]
+    #[inline(always)]
+    pub fn ia(&self) -> IaR {
+        IaR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"]
+    #[inline(always)]
+    pub fn ee(&self) -> EeR {
+        EeR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Active port"]
+    #[inline(always)]
+    pub fn ap(&self) -> ApR {
+        ApR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bits 21:23 - Link State"]
+    #[inline(always)]
+    pub fn ls(&self) -> LsR {
+        LsR::new(((self.bits >> 21) & 7) as u8)
+    }
+    #[doc = "Bits 24:25 - Number of Transmit Descriptors"]
+    #[inline(always)]
+    pub fn ntxd(&self) -> NtxdR {
+        NtxdR::new(((self.bits >> 24) & 3) as u8)
+    }
+    #[doc = "Bits 26:27 - Number of Receive Descriptors"]
+    #[inline(always)]
+    pub fn nrxd(&self) -> NrxdR {
+        NrxdR::new(((self.bits >> 26) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - A new time count value was received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn to(&mut self) -> ToW<StsSpec> {
+        ToW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Credit has occurred"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ce(&mut self) -> CeW<StsSpec> {
+        CeW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Escape error has occurred"]
+    #[inline(always)]
+    #[must_use]
+    pub fn er(&mut self) -> ErW<StsSpec> {
+        ErW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Disconnection error has occurred"]
+    #[inline(always)]
+    #[must_use]
+    pub fn de(&mut self) -> DeW<StsSpec> {
+        DeW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Parity error has occurred"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pe(&mut self) -> PeW<StsSpec> {
+        PeW::new(self, 4)
+    }
+    #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"]
+    #[inline(always)]
+    #[must_use]
+    pub fn we(&mut self) -> WeW<StsSpec> {
+        WeW::new(self, 6)
+    }
+    #[doc = "Bit 7 - Packet is received with an invalid destination address field"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ia(&mut self) -> IaW<StsSpec> {
+        IaW::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ee(&mut self) -> EeW<StsSpec> {
+        EeW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Active port"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ap(&mut self) -> ApW<StsSpec> {
+        ApW::new(self, 9)
+    }
+    #[doc = "Bits 21:23 - Link State"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ls(&mut self) -> LsW<StsSpec> {
+        LsW::new(self, 21)
+    }
+    #[doc = "Bits 24:25 - Number of Transmit Descriptors"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ntxd(&mut self) -> NtxdW<StsSpec> {
+        NtxdW::new(self, 24)
+    }
+    #[doc = "Bits 26:27 - Number of Receive Descriptors"]
+    #[inline(always)]
+    #[must_use]
+    pub fn nrxd(&mut self) -> NrxdW<StsSpec> {
+        NrxdW::new(self, 26)
+    }
+}
+#[doc = "Status/Interrupt Source Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StsSpec;
+impl crate::RegisterSpec for StsSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sts::R`](R) reader structure"]
+impl crate::Readable for StsSpec {}
+#[doc = "`write(|w| ..)` method takes [`sts::W`](W) writer structure"]
+impl crate::Writable for StsSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STS to value 0x0640_0000"]
+impl crate::Resettable for StsSpec {
+    const RESET_VALUE: u32 = 0x0640_0000;
+}

va416xx/src/spw/tc.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `TC` reader"]
+pub type R = crate::R<TcSpec>;
+#[doc = "Register `TC` writer"]
+pub type W = crate::W<TcSpec>;
+#[doc = "Field `TIMECNT` reader - The current value of the system time counter"]
+pub type TimecntR = crate::FieldReader;
+#[doc = "Field `TIMECNT` writer - The current value of the system time counter"]
+pub type TimecntW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `TIRQ_END` reader - The current value of the time control flags"]
+pub type TirqEndR = crate::FieldReader;
+#[doc = "Field `TIRQ_END` writer - The current value of the time control flags"]
+pub type TirqEndW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:5 - The current value of the system time counter"]
+    #[inline(always)]
+    pub fn timecnt(&self) -> TimecntR {
+        TimecntR::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 6:7 - The current value of the time control flags"]
+    #[inline(always)]
+    pub fn tirq_end(&self) -> TirqEndR {
+        TirqEndR::new(((self.bits >> 6) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - The current value of the system time counter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn timecnt(&mut self) -> TimecntW<TcSpec> {
+        TimecntW::new(self, 0)
+    }
+    #[doc = "Bits 6:7 - The current value of the time control flags"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tirq_end(&mut self) -> TirqEndW<TcSpec> {
+        TirqEndW::new(self, 6)
+    }
+}
+#[doc = "Time Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TcSpec;
+impl crate::RegisterSpec for TcSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tc::R`](R) reader structure"]
+impl crate::Readable for TcSpec {}
+#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"]
+impl crate::Writable for TcSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TC to value 0"]
+impl crate::Resettable for TcSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/spw/tdr.rs

@@ -0,0 +1,29 @@
+#[doc = "Register `TDR` reader"]
+pub type R = crate::R<TdrSpec>;
+#[doc = "Field `TIMER64` reader - Used to generate the 6.4 and 12.8 us time periods"]
+pub type Timer64R = crate::FieldReader<u16>;
+#[doc = "Field `DISCONNECT` reader - Used to generate the 850 ns disconnect time period"]
+pub type DisconnectR = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:11 - Used to generate the 6.4 and 12.8 us time periods"]
+    #[inline(always)]
+    pub fn timer64(&self) -> Timer64R {
+        Timer64R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 12:21 - Used to generate the 850 ns disconnect time period"]
+    #[inline(always)]
+    pub fn disconnect(&self) -> DisconnectR {
+        DisconnectR::new(((self.bits >> 12) & 0x03ff) as u16)
+    }
+}
+#[doc = "Timer and Disconnect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TdrSpec;
+impl crate::RegisterSpec for TdrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tdr::R`](R) reader structure"]
+impl crate::Readable for TdrSpec {}
+#[doc = "`reset()` method sets TDR to value 0"]
+impl crate::Resettable for TdrSpec {
+    const RESET_VALUE: u32 = 0;
+}