Init Commit

Monorepo for Rust support of VA416XX family of radiation hardened MCUs
2021-12-07 00:31:51 +01:00
commit 5d1740efea
606 changed files with 74678 additions and 0 deletions
--- a/va416xx/src/sysconfig/adc_cal.rs
+++ b/va416xx/src/sysconfig/adc_cal.rs
@ -0,0 +1,22 @@
+#[doc = "Register `ADC_CAL` reader"]
+pub type R = crate::R<AdcCalSpec>;
+#[doc = "Field `ADC_CAL` reader - ADC Calibration bits"]
+pub type AdcCalR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:4 - ADC Calibration bits"]
+    #[inline(always)]
+    pub fn adc_cal(&self) -> AdcCalR {
+        AdcCalR::new((self.bits & 0x1f) as u8)
+    }
+}
+#[doc = "ADC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AdcCalSpec;
+impl crate::RegisterSpec for AdcCalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`adc_cal::R`](R) reader structure"]
+impl crate::Readable for AdcCalSpec {}
+#[doc = "`reset()` method sets ADC_CAL to value 0"]
+impl crate::Resettable for AdcCalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/analog_cntl.rs
+++ b/va416xx/src/sysconfig/analog_cntl.rs
@ -0,0 +1,235 @@
+#[doc = "Register `ANALOG_CNTL` reader"]
+pub type R = crate::R<AnalogCntlSpec>;
+#[doc = "Register `ANALOG_CNTL` writer"]
+pub type W = crate::W<AnalogCntlSpec>;
+#[doc = "Field `TMOSC` reader - Test Mode"]
+pub type TmoscR = crate::BitReader;
+#[doc = "Field `TMOSC` writer - Test Mode"]
+pub type TmoscW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TMPOKDIS` reader - Test Mode"]
+pub type TmpokdisR = crate::BitReader;
+#[doc = "Field `TMPOKDIS` writer - Test Mode"]
+pub type TmpokdisW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TM_ADCMUX_N` reader - Test Mode"]
+pub type TmAdcmuxNR = crate::BitReader;
+#[doc = "Field `TM_ADCMUX_N` writer - Test Mode"]
+pub type TmAdcmuxNW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TM_ADCMUX_P` reader - Test Mode"]
+pub type TmAdcmuxPR = crate::BitReader;
+#[doc = "Field `TM_ADCMUX_P` writer - Test Mode"]
+pub type TmAdcmuxPW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TMRATIO` reader - Test Mode"]
+pub type TmratioR = crate::BitReader;
+#[doc = "Field `TMRATIO` writer - Test Mode"]
+pub type TmratioW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TMATOMUX` reader - Test Mode"]
+pub type TmatomuxR = crate::FieldReader;
+#[doc = "Field `TMATOMUX` writer - Test Mode"]
+pub type TmatomuxW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `ADC_STEST` reader - Number of clocks for sample time"]
+pub type AdcStestR = crate::FieldReader;
+#[doc = "Field `ADC_STEST` writer - Number of clocks for sample time"]
+pub type AdcStestW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `RCLK_POS_EN` reader - Enable normal test clock"]
+pub type RclkPosEnR = crate::BitReader;
+#[doc = "Field `RCLK_POS_EN` writer - Enable normal test clock"]
+pub type RclkPosEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RCLK_NEG_EN` reader - Enable inverted test clock"]
+pub type RclkNegEnR = crate::BitReader;
+#[doc = "Field `RCLK_NEG_EN` writer - Enable inverted test clock"]
+pub type RclkNegEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APB2CLK_POS_EN` reader - Enable normal APB2CLK for test output"]
+pub type Apb2clkPosEnR = crate::BitReader;
+#[doc = "Field `APB2CLK_POS_EN` writer - Enable normal APB2CLK for test output"]
+pub type Apb2clkPosEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APB2CLK_NEG_EN` reader - Enable inverted APB2CLK for test output"]
+pub type Apb2clkNegEnR = crate::BitReader;
+#[doc = "Field `APB2CLK_NEG_EN` writer - Enable inverted APB2CLK for test output"]
+pub type Apb2clkNegEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TM_ANALOG_PD_EN` reader - Enables pull down on analog pads"]
+pub type TmAnalogPdEnR = crate::BitReader;
+#[doc = "Field `TM_ANALOG_PD_EN` writer - Enables pull down on analog pads"]
+pub type TmAnalogPdEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `JMP2BOOT` reader - Enables a skip of all delay counters and eFuse read"]
+pub type Jmp2bootR = crate::BitReader;
+#[doc = "Field `JMP2BOOT` writer - Enables a skip of all delay counters and eFuse read"]
+pub type Jmp2bootW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SKIPBOOT` reader - Enables a skip of all delay counters, eFuse read, and boot"]
+pub type SkipbootR = crate::BitReader;
+#[doc = "Field `SKIPBOOT` writer - Enables a skip of all delay counters, eFuse read, and boot"]
+pub type SkipbootW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Test Mode"]
+    #[inline(always)]
+    pub fn tmosc(&self) -> TmoscR {
+        TmoscR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Test Mode"]
+    #[inline(always)]
+    pub fn tmpokdis(&self) -> TmpokdisR {
+        TmpokdisR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Test Mode"]
+    #[inline(always)]
+    pub fn tm_adcmux_n(&self) -> TmAdcmuxNR {
+        TmAdcmuxNR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Test Mode"]
+    #[inline(always)]
+    pub fn tm_adcmux_p(&self) -> TmAdcmuxPR {
+        TmAdcmuxPR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Test Mode"]
+    #[inline(always)]
+    pub fn tmratio(&self) -> TmratioR {
+        TmratioR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:6 - Test Mode"]
+    #[inline(always)]
+    pub fn tmatomux(&self) -> TmatomuxR {
+        TmatomuxR::new(((self.bits >> 5) & 3) as u8)
+    }
+    #[doc = "Bits 9:12 - Number of clocks for sample time"]
+    #[inline(always)]
+    pub fn adc_stest(&self) -> AdcStestR {
+        AdcStestR::new(((self.bits >> 9) & 0x0f) as u8)
+    }
+    #[doc = "Bit 14 - Enable normal test clock"]
+    #[inline(always)]
+    pub fn rclk_pos_en(&self) -> RclkPosEnR {
+        RclkPosEnR::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Enable inverted test clock"]
+    #[inline(always)]
+    pub fn rclk_neg_en(&self) -> RclkNegEnR {
+        RclkNegEnR::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Enable normal APB2CLK for test output"]
+    #[inline(always)]
+    pub fn apb2clk_pos_en(&self) -> Apb2clkPosEnR {
+        Apb2clkPosEnR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Enable inverted APB2CLK for test output"]
+    #[inline(always)]
+    pub fn apb2clk_neg_en(&self) -> Apb2clkNegEnR {
+        Apb2clkNegEnR::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Enables pull down on analog pads"]
+    #[inline(always)]
+    pub fn tm_analog_pd_en(&self) -> TmAnalogPdEnR {
+        TmAnalogPdEnR::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"]
+    #[inline(always)]
+    pub fn jmp2boot(&self) -> Jmp2bootR {
+        Jmp2bootR::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"]
+    #[inline(always)]
+    pub fn skipboot(&self) -> SkipbootR {
+        SkipbootR::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Test Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tmosc(&mut self) -> TmoscW<AnalogCntlSpec> {
+        TmoscW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Test Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tmpokdis(&mut self) -> TmpokdisW<AnalogCntlSpec> {
+        TmpokdisW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Test Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tm_adcmux_n(&mut self) -> TmAdcmuxNW<AnalogCntlSpec> {
+        TmAdcmuxNW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Test Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tm_adcmux_p(&mut self) -> TmAdcmuxPW<AnalogCntlSpec> {
+        TmAdcmuxPW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Test Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tmratio(&mut self) -> TmratioW<AnalogCntlSpec> {
+        TmratioW::new(self, 4)
+    }
+    #[doc = "Bits 5:6 - Test Mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tmatomux(&mut self) -> TmatomuxW<AnalogCntlSpec> {
+        TmatomuxW::new(self, 5)
+    }
+    #[doc = "Bits 9:12 - Number of clocks for sample time"]
+    #[inline(always)]
+    #[must_use]
+    pub fn adc_stest(&mut self) -> AdcStestW<AnalogCntlSpec> {
+        AdcStestW::new(self, 9)
+    }
+    #[doc = "Bit 14 - Enable normal test clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rclk_pos_en(&mut self) -> RclkPosEnW<AnalogCntlSpec> {
+        RclkPosEnW::new(self, 14)
+    }
+    #[doc = "Bit 15 - Enable inverted test clock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rclk_neg_en(&mut self) -> RclkNegEnW<AnalogCntlSpec> {
+        RclkNegEnW::new(self, 15)
+    }
+    #[doc = "Bit 16 - Enable normal APB2CLK for test output"]
+    #[inline(always)]
+    #[must_use]
+    pub fn apb2clk_pos_en(&mut self) -> Apb2clkPosEnW<AnalogCntlSpec> {
+        Apb2clkPosEnW::new(self, 16)
+    }
+    #[doc = "Bit 17 - Enable inverted APB2CLK for test output"]
+    #[inline(always)]
+    #[must_use]
+    pub fn apb2clk_neg_en(&mut self) -> Apb2clkNegEnW<AnalogCntlSpec> {
+        Apb2clkNegEnW::new(self, 17)
+    }
+    #[doc = "Bit 18 - Enables pull down on analog pads"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tm_analog_pd_en(&mut self) -> TmAnalogPdEnW<AnalogCntlSpec> {
+        TmAnalogPdEnW::new(self, 18)
+    }
+    #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"]
+    #[inline(always)]
+    #[must_use]
+    pub fn jmp2boot(&mut self) -> Jmp2bootW<AnalogCntlSpec> {
+        Jmp2bootW::new(self, 19)
+    }
+    #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"]
+    #[inline(always)]
+    #[must_use]
+    pub fn skipboot(&mut self) -> SkipbootW<AnalogCntlSpec> {
+        SkipbootW::new(self, 20)
+    }
+}
+#[doc = "Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`analog_cntl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`analog_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AnalogCntlSpec;
+impl crate::RegisterSpec for AnalogCntlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`analog_cntl::R`](R) reader structure"]
+impl crate::Readable for AnalogCntlSpec {}
+#[doc = "`write(|w| ..)` method takes [`analog_cntl::W`](W) writer structure"]
+impl crate::Writable for AnalogCntlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ANALOG_CNTL to value 0"]
+impl crate::Resettable for AnalogCntlSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/areg_cal.rs
+++ b/va416xx/src/sysconfig/areg_cal.rs
@ -0,0 +1,22 @@
+#[doc = "Register `AREG_CAL` reader"]
+pub type R = crate::R<AregCalSpec>;
+#[doc = "Field `AREG_CAL` reader - Analog LDO Regulator Calibration bits"]
+pub type AregCalR = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:8 - Analog LDO Regulator Calibration bits"]
+    #[inline(always)]
+    pub fn areg_cal(&self) -> AregCalR {
+        AregCalR::new((self.bits & 0x01ff) as u16)
+    }
+}
+#[doc = "Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`areg_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AregCalSpec;
+impl crate::RegisterSpec for AregCalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`areg_cal::R`](R) reader structure"]
+impl crate::Readable for AregCalSpec {}
+#[doc = "`reset()` method sets AREG_CAL to value 0"]
+impl crate::Resettable for AregCalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/bg_cal.rs
+++ b/va416xx/src/sysconfig/bg_cal.rs
@ -0,0 +1,22 @@
+#[doc = "Register `BG_CAL` reader"]
+pub type R = crate::R<BgCalSpec>;
+#[doc = "Field `BG_CAL` reader - Bandgap Calibration bits"]
+pub type BgCalR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:2 - Bandgap Calibration bits"]
+    #[inline(always)]
+    pub fn bg_cal(&self) -> BgCalR {
+        BgCalR::new((self.bits & 7) as u8)
+    }
+}
+#[doc = "Bandgap Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bg_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BgCalSpec;
+impl crate::RegisterSpec for BgCalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bg_cal::R`](R) reader structure"]
+impl crate::Readable for BgCalSpec {}
+#[doc = "`reset()` method sets BG_CAL to value 0"]
+impl crate::Resettable for BgCalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/dac0_cal.rs
+++ b/va416xx/src/sysconfig/dac0_cal.rs
@ -0,0 +1,22 @@
+#[doc = "Register `DAC0_CAL` reader"]
+pub type R = crate::R<Dac0CalSpec>;
+#[doc = "Field `DAC0_CAL` reader - DAC0 Calibration bits"]
+pub type Dac0CalR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:4 - DAC0 Calibration bits"]
+    #[inline(always)]
+    pub fn dac0_cal(&self) -> Dac0CalR {
+        Dac0CalR::new((self.bits & 0x1f) as u8)
+    }
+}
+#[doc = "DAC0 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac0_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dac0CalSpec;
+impl crate::RegisterSpec for Dac0CalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dac0_cal::R`](R) reader structure"]
+impl crate::Readable for Dac0CalSpec {}
+#[doc = "`reset()` method sets DAC0_CAL to value 0"]
+impl crate::Resettable for Dac0CalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/dac1_cal.rs
+++ b/va416xx/src/sysconfig/dac1_cal.rs
@ -0,0 +1,22 @@
+#[doc = "Register `DAC1_CAL` reader"]
+pub type R = crate::R<Dac1CalSpec>;
+#[doc = "Field `DAC1_CAL` reader - DAC1 Calibration bits"]
+pub type Dac1CalR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:4 - DAC1 Calibration bits"]
+    #[inline(always)]
+    pub fn dac1_cal(&self) -> Dac1CalR {
+        Dac1CalR::new((self.bits & 0x1f) as u8)
+    }
+}
+#[doc = "DAC1 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac1_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Dac1CalSpec;
+impl crate::RegisterSpec for Dac1CalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dac1_cal::R`](R) reader structure"]
+impl crate::Readable for Dac1CalSpec {}
+#[doc = "`reset()` method sets DAC1_CAL to value 0"]
+impl crate::Resettable for Dac1CalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/dreg_cal.rs
+++ b/va416xx/src/sysconfig/dreg_cal.rs
@ -0,0 +1,22 @@
+#[doc = "Register `DREG_CAL` reader"]
+pub type R = crate::R<DregCalSpec>;
+#[doc = "Field `DREG_CAL` reader - Digital LDO Regulator Calibration bits"]
+pub type DregCalR = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:8 - Digital LDO Regulator Calibration bits"]
+    #[inline(always)]
+    pub fn dreg_cal(&self) -> DregCalR {
+        DregCalR::new((self.bits & 0x01ff) as u16)
+    }
+}
+#[doc = "Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dreg_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DregCalSpec;
+impl crate::RegisterSpec for DregCalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dreg_cal::R`](R) reader structure"]
+impl crate::Readable for DregCalSpec {}
+#[doc = "`reset()` method sets DREG_CAL to value 0"]
+impl crate::Resettable for DregCalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/ebi_cfg0.rs
+++ b/va416xx/src/sysconfig/ebi_cfg0.rs
@ -0,0 +1,115 @@
+#[doc = "Register `EBI_CFG0` reader"]
+pub type R = crate::R<EbiCfg0Spec>;
+#[doc = "Register `EBI_CFG0` writer"]
+pub type W = crate::W<EbiCfg0Spec>;
+#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"]
+pub type Addrlow0R = crate::FieldReader;
+#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"]
+pub type Addrlow0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"]
+pub type Addrhigh0R = crate::FieldReader;
+#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"]
+pub type Addrhigh0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"]
+pub type CfgreadcycleR = crate::FieldReader;
+#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"]
+pub type CfgreadcycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"]
+pub type CfgwritecycleR = crate::FieldReader;
+#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"]
+pub type CfgwritecycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"]
+pub type CfgturnaroundcycleR = crate::FieldReader;
+#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"]
+pub type CfgturnaroundcycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"]
+pub type CfgsizeR = crate::BitReader;
+#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"]
+pub type CfgsizeW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&self) -> Addrlow0R {
+        Addrlow0R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&self) -> Addrhigh0R {
+        Addrhigh0R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&self) -> CfgreadcycleR {
+        CfgreadcycleR::new(((self.bits >> 16) & 7) as u8)
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&self) -> CfgwritecycleR {
+        CfgwritecycleR::new(((self.bits >> 19) & 7) as u8)
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&self) -> CfgturnaroundcycleR {
+        CfgturnaroundcycleR::new(((self.bits >> 22) & 7) as u8)
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&self) -> CfgsizeR {
+        CfgsizeR::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn addrlow0(&mut self) -> Addrlow0W<EbiCfg0Spec> {
+        Addrlow0W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn addrhigh0(&mut self) -> Addrhigh0W<EbiCfg0Spec> {
+        Addrhigh0W::new(self, 8)
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cfgreadcycle(&mut self) -> CfgreadcycleW<EbiCfg0Spec> {
+        CfgreadcycleW::new(self, 16)
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cfgwritecycle(&mut self) -> CfgwritecycleW<EbiCfg0Spec> {
+        CfgwritecycleW::new(self, 19)
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cfgturnaroundcycle(&mut self) -> CfgturnaroundcycleW<EbiCfg0Spec> {
+        CfgturnaroundcycleW::new(self, 22)
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cfgsize(&mut self) -> CfgsizeW<EbiCfg0Spec> {
+        CfgsizeW::new(self, 25)
+    }
+}
+#[doc = "EBI Config Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ebi_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ebi_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EbiCfg0Spec;
+impl crate::RegisterSpec for EbiCfg0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ebi_cfg0::R`](R) reader structure"]
+impl crate::Readable for EbiCfg0Spec {}
+#[doc = "`write(|w| ..)` method takes [`ebi_cfg0::W`](W) writer structure"]
+impl crate::Writable for EbiCfg0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EBI_CFG0 to value 0"]
+impl crate::Resettable for EbiCfg0Spec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/ef_config.rs
+++ b/va416xx/src/sysconfig/ef_config.rs
@ -0,0 +1,92 @@
+#[doc = "Register `EF_CONFIG` reader"]
+pub type R = crate::R<EfConfigSpec>;
+#[doc = "Field `ROM_SPEED` reader - Specifies the speed of ROM_SCK"]
+pub type RomSpeedR = crate::FieldReader;
+#[doc = "Field `ROM_SIZE` reader - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"]
+pub type RomSizeR = crate::FieldReader;
+#[doc = "Field `ROM_NOCHECK` reader - When set to 1, the ROM check is skipped"]
+pub type RomNocheckR = crate::BitReader;
+#[doc = "Field `BOOT_DELAY` reader - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"]
+pub type BootDelayR = crate::FieldReader;
+#[doc = "Field `ROM_READ` reader - SPI ROM read instruction code"]
+pub type RomReadR = crate::FieldReader;
+#[doc = "Field `ROM_LATENCY` reader - Number of bits of latency from Address until data from the SPI ROM"]
+pub type RomLatencyR = crate::FieldReader;
+#[doc = "Field `ROM_ADDRESS` reader - ROM Address Mode"]
+pub type RomAddressR = crate::FieldReader;
+#[doc = "Field `ROM_DLYCAP` reader - ROM SPI Delayed capture"]
+pub type RomDlycapR = crate::BitReader;
+#[doc = "Field `ROM_STATUS` reader - The first data byte from the SPI ROM following an address is taken as a status byte"]
+pub type RomStatusR = crate::BitReader;
+#[doc = "Field `RM` reader - This bit controls the internal RAM read timing and must be maintained at this value"]
+pub type RmR = crate::BitReader;
+#[doc = "Field `WM` reader - This bit controls the internal RAM write timing and must be maintained at this value"]
+pub type WmR = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:1 - Specifies the speed of ROM_SCK"]
+    #[inline(always)]
+    pub fn rom_speed(&self) -> RomSpeedR {
+        RomSpeedR::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:5 - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"]
+    #[inline(always)]
+    pub fn rom_size(&self) -> RomSizeR {
+        RomSizeR::new(((self.bits >> 2) & 0x0f) as u8)
+    }
+    #[doc = "Bit 6 - When set to 1, the ROM check is skipped"]
+    #[inline(always)]
+    pub fn rom_nocheck(&self) -> RomNocheckR {
+        RomNocheckR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bits 7:9 - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"]
+    #[inline(always)]
+    pub fn boot_delay(&self) -> BootDelayR {
+        BootDelayR::new(((self.bits >> 7) & 7) as u8)
+    }
+    #[doc = "Bits 10:17 - SPI ROM read instruction code"]
+    #[inline(always)]
+    pub fn rom_read(&self) -> RomReadR {
+        RomReadR::new(((self.bits >> 10) & 0xff) as u8)
+    }
+    #[doc = "Bits 18:22 - Number of bits of latency from Address until data from the SPI ROM"]
+    #[inline(always)]
+    pub fn rom_latency(&self) -> RomLatencyR {
+        RomLatencyR::new(((self.bits >> 18) & 0x1f) as u8)
+    }
+    #[doc = "Bits 23:24 - ROM Address Mode"]
+    #[inline(always)]
+    pub fn rom_address(&self) -> RomAddressR {
+        RomAddressR::new(((self.bits >> 23) & 3) as u8)
+    }
+    #[doc = "Bit 25 - ROM SPI Delayed capture"]
+    #[inline(always)]
+    pub fn rom_dlycap(&self) -> RomDlycapR {
+        RomDlycapR::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The first data byte from the SPI ROM following an address is taken as a status byte"]
+    #[inline(always)]
+    pub fn rom_status(&self) -> RomStatusR {
+        RomStatusR::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - This bit controls the internal RAM read timing and must be maintained at this value"]
+    #[inline(always)]
+    pub fn rm(&self) -> RmR {
+        RmR::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - This bit controls the internal RAM write timing and must be maintained at this value"]
+    #[inline(always)]
+    pub fn wm(&self) -> WmR {
+        WmR::new(((self.bits >> 28) & 1) != 0)
+    }
+}
+#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EfConfigSpec;
+impl crate::RegisterSpec for EfConfigSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ef_config::R`](R) reader structure"]
+impl crate::Readable for EfConfigSpec {}
+#[doc = "`reset()` method sets EF_CONFIG to value 0x0a80_0c40"]
+impl crate::Resettable for EfConfigSpec {
+    const RESET_VALUE: u32 = 0x0a80_0c40;
+}
--- a/va416xx/src/sysconfig/ef_id0.rs
+++ b/va416xx/src/sysconfig/ef_id0.rs
@ -0,0 +1,18 @@
+#[doc = "Register `EF_ID0` reader"]
+pub type R = crate::R<EfId0Spec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "EFuse ID0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EfId0Spec;
+impl crate::RegisterSpec for EfId0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ef_id0::R`](R) reader structure"]
+impl crate::Readable for EfId0Spec {}
+#[doc = "`reset()` method sets EF_ID0 to value 0"]
+impl crate::Resettable for EfId0Spec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/ef_id1.rs
+++ b/va416xx/src/sysconfig/ef_id1.rs
@ -0,0 +1,18 @@
+#[doc = "Register `EF_ID1` reader"]
+pub type R = crate::R<EfId1Spec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "EFuse ID1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EfId1Spec;
+impl crate::RegisterSpec for EfId1Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ef_id1::R`](R) reader structure"]
+impl crate::Readable for EfId1Spec {}
+#[doc = "`reset()` method sets EF_ID1 to value 0"]
+impl crate::Resettable for EfId1Spec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/hbo_cal.rs
+++ b/va416xx/src/sysconfig/hbo_cal.rs
@ -0,0 +1,29 @@
+#[doc = "Register `HBO_CAL` reader"]
+pub type R = crate::R<HboCalSpec>;
+#[doc = "Field `HBO_CAL` reader - Heart Beat OSC Calibration bits"]
+pub type HboCalR = crate::FieldReader;
+#[doc = "Field `OSC_CAL` reader - 1MHz OSC Calibration bit"]
+pub type OscCalR = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:2 - Heart Beat OSC Calibration bits"]
+    #[inline(always)]
+    pub fn hbo_cal(&self) -> HboCalR {
+        HboCalR::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - 1MHz OSC Calibration bit"]
+    #[inline(always)]
+    pub fn osc_cal(&self) -> OscCalR {
+        OscCalR::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[doc = "Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hbo_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HboCalSpec;
+impl crate::RegisterSpec for HboCalSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hbo_cal::R`](R) reader structure"]
+impl crate::Readable for HboCalSpec {}
+#[doc = "`reset()` method sets HBO_CAL to value 0"]
+impl crate::Resettable for HboCalSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/irq_enb.rs
+++ b/va416xx/src/sysconfig/irq_enb.rs
@ -0,0 +1,115 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"]
+pub type RommbeR = crate::BitReader;
+#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"]
+pub type RommbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"]
+pub type RomsbeR = crate::BitReader;
+#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"]
+pub type RomsbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"]
+pub type Ram0mbeR = crate::BitReader;
+#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"]
+pub type Ram0mbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"]
+pub type Ram0sbeR = crate::BitReader;
+#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"]
+pub type Ram0sbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"]
+pub type Ram1mbeR = crate::BitReader;
+#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"]
+pub type Ram1mbeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"]
+pub type Ram1sbeR = crate::BitReader;
+#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"]
+pub type Ram1sbeW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&self) -> RommbeR {
+        RommbeR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&self) -> RomsbeR {
+        RomsbeR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0mbe(&self) -> Ram0mbeR {
+        Ram0mbeR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0sbe(&self) -> Ram0sbeR {
+        Ram0sbeR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1mbe(&self) -> Ram1mbeR {
+        Ram1mbeR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1sbe(&self) -> Ram1sbeR {
+        Ram1sbeR::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rommbe(&mut self) -> RommbeW<IrqEnbSpec> {
+        RommbeW::new(self, 0)
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn romsbe(&mut self) -> RomsbeW<IrqEnbSpec> {
+        RomsbeW::new(self, 1)
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ram0mbe(&mut self) -> Ram0mbeW<IrqEnbSpec> {
+        Ram0mbeW::new(self, 2)
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ram0sbe(&mut self) -> Ram0sbeW<IrqEnbSpec> {
+        Ram0sbeW::new(self, 3)
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ram1mbe(&mut self) -> Ram1mbeW<IrqEnbSpec> {
+        Ram1mbeW::new(self, 4)
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ram1sbe(&mut self) -> Ram1sbeW<IrqEnbSpec> {
+        Ram1sbeW::new(self, 5)
+    }
+}
+#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/perid.rs
+++ b/va416xx/src/sysconfig/perid.rs
@ -0,0 +1,36 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+#[doc = "Field `MANUFACTURER_ID` reader - MANUFACTURER_ID"]
+pub type ManufacturerIdR = crate::FieldReader<u16>;
+#[doc = "Field `PERIPHERAL_ID` reader - PERIPHERAL_ID"]
+pub type PeripheralIdR = crate::FieldReader;
+#[doc = "Field `PERIPHERAL_VER` reader - PERIPHERAL_VER"]
+pub type PeripheralVerR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:11 - MANUFACTURER_ID"]
+    #[inline(always)]
+    pub fn manufacturer_id(&self) -> ManufacturerIdR {
+        ManufacturerIdR::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 16:23 - PERIPHERAL_ID"]
+    #[inline(always)]
+    pub fn peripheral_id(&self) -> PeripheralIdR {
+        PeripheralIdR::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - PERIPHERAL_VER"]
+    #[inline(always)]
+    pub fn peripheral_ver(&self) -> PeripheralVerR {
+        PeripheralVerR::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0280_07e9"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0280_07e9;
+}
--- a/va416xx/src/sysconfig/peripheral_reset.rs
+++ b/va416xx/src/sysconfig/peripheral_reset.rs
@ -0,0 +1,490 @@
+#[doc = "Register `PERIPHERAL_RESET` reader"]
+pub type R = crate::R<PeripheralResetSpec>;
+#[doc = "Register `PERIPHERAL_RESET` writer"]
+pub type W = crate::W<PeripheralResetSpec>;
+#[doc = "Field `SPI0` reader - Resetn of SPI0"]
+pub type Spi0R = crate::BitReader;
+#[doc = "Field `SPI0` writer - Resetn of SPI0"]
+pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI1` reader - Resetn of SPI1"]
+pub type Spi1R = crate::BitReader;
+#[doc = "Field `SPI1` writer - Resetn of SPI1"]
+pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI2` reader - Resetn of SPI2"]
+pub type Spi2R = crate::BitReader;
+#[doc = "Field `SPI2` writer - Resetn of SPI2"]
+pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI3` reader - Resetn of SPI3"]
+pub type Spi3R = crate::BitReader;
+#[doc = "Field `SPI3` writer - Resetn of SPI3"]
+pub type Spi3W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART0` reader - Resetn of UART0"]
+pub type Uart0R = crate::BitReader;
+#[doc = "Field `UART0` writer - Resetn of UART0"]
+pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART1` reader - Resetn of UART1"]
+pub type Uart1R = crate::BitReader;
+#[doc = "Field `UART1` writer - Resetn of UART1"]
+pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART2` reader - Resetn of UART2"]
+pub type Uart2R = crate::BitReader;
+#[doc = "Field `UART2` writer - Resetn of UART2"]
+pub type Uart2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C0` reader - Resetn of I2C0"]
+pub type I2c0R = crate::BitReader;
+#[doc = "Field `I2C0` writer - Resetn of I2C0"]
+pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C1` reader - Resetn of I2C1"]
+pub type I2c1R = crate::BitReader;
+#[doc = "Field `I2C1` writer - Resetn of I2C1"]
+pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C2` reader - Resetn of I2C2"]
+pub type I2c2R = crate::BitReader;
+#[doc = "Field `I2C2` writer - Resetn of I2C2"]
+pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAN0` reader - Resetn of CAN0"]
+pub type Can0R = crate::BitReader;
+#[doc = "Field `CAN0` writer - Resetn of CAN0"]
+pub type Can0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAN1` reader - Resetn of CAN1"]
+pub type Can1R = crate::BitReader;
+#[doc = "Field `CAN1` writer - Resetn of CAN1"]
+pub type Can1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRNG` reader - Resetn of TRNG"]
+pub type TrngR = crate::BitReader;
+#[doc = "Field `TRNG` writer - Resetn of TRNG"]
+pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC` reader - Resetn of ADC"]
+pub type AdcR = crate::BitReader;
+#[doc = "Field `ADC` writer - Resetn of ADC"]
+pub type AdcW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DAC` reader - Resetn of DAC"]
+pub type DacR = crate::BitReader;
+#[doc = "Field `DAC` writer - Resetn of DAC"]
+pub type DacW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DMA` reader - Resetn of DMA"]
+pub type DmaR = crate::BitReader;
+#[doc = "Field `DMA` writer - Resetn of DMA"]
+pub type DmaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EBI` reader - Resetn of EBI"]
+pub type EbiR = crate::BitReader;
+#[doc = "Field `EBI` writer - Resetn of EBI"]
+pub type EbiW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ETH` reader - Resetn of Ethernet"]
+pub type EthR = crate::BitReader;
+#[doc = "Field `ETH` writer - Resetn of Ethernet"]
+pub type EthW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPW` reader - Resetn of SpaceWire"]
+pub type SpwR = crate::BitReader;
+#[doc = "Field `SPW` writer - Resetn of SpaceWire"]
+pub type SpwW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLKGEN` reader - RESETn of PLL in Clock Generation Module"]
+pub type ClkgenR = crate::BitReader;
+#[doc = "Field `CLKGEN` writer - RESETn of PLL in Clock Generation Module"]
+pub type ClkgenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ` reader - Resetn of IRQ Router"]
+pub type IrqR = crate::BitReader;
+#[doc = "Field `IRQ` writer - Resetn of IRQ Router"]
+pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IOCONFIG` reader - Resetn of IO CONFIG"]
+pub type IoconfigR = crate::BitReader;
+#[doc = "Field `IOCONFIG` writer - Resetn of IO CONFIG"]
+pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UTILITY` reader - Resetn of UTILITY peripheral"]
+pub type UtilityR = crate::BitReader;
+#[doc = "Field `UTILITY` writer - Resetn of UTILITY peripheral"]
+pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDOG` reader - Resetn of WDOG"]
+pub type WdogR = crate::BitReader;
+#[doc = "Field `WDOG` writer - Resetn of WDOG"]
+pub type WdogW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTA` reader - Resetn of PORTA"]
+pub type PortaR = crate::BitReader;
+#[doc = "Field `PORTA` writer - Resetn of PORTA"]
+pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTB` reader - Resetn of PORTB"]
+pub type PortbR = crate::BitReader;
+#[doc = "Field `PORTB` writer - Resetn of PORTB"]
+pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTC` reader - Resetn of PORTC"]
+pub type PortcR = crate::BitReader;
+#[doc = "Field `PORTC` writer - Resetn of PORTC"]
+pub type PortcW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTD` reader - Resetn of PORTD"]
+pub type PortdR = crate::BitReader;
+#[doc = "Field `PORTD` writer - Resetn of PORTD"]
+pub type PortdW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTE` reader - Resetn of PORTE"]
+pub type PorteR = crate::BitReader;
+#[doc = "Field `PORTE` writer - Resetn of PORTE"]
+pub type PorteW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTF` reader - Resetn of PORTF"]
+pub type PortfR = crate::BitReader;
+#[doc = "Field `PORTF` writer - Resetn of PORTF"]
+pub type PortfW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PORTG` reader - Resetn of PORTG"]
+pub type PortgR = crate::BitReader;
+#[doc = "Field `PORTG` writer - Resetn of PORTG"]
+pub type PortgW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Resetn of SPI0"]
+    #[inline(always)]
+    pub fn spi0(&self) -> Spi0R {
+        Spi0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Resetn of SPI1"]
+    #[inline(always)]
+    pub fn spi1(&self) -> Spi1R {
+        Spi1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Resetn of SPI2"]
+    #[inline(always)]
+    pub fn spi2(&self) -> Spi2R {
+        Spi2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Resetn of SPI3"]
+    #[inline(always)]
+    pub fn spi3(&self) -> Spi3R {
+        Spi3R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Resetn of UART0"]
+    #[inline(always)]
+    pub fn uart0(&self) -> Uart0R {
+        Uart0R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Resetn of UART1"]
+    #[inline(always)]
+    pub fn uart1(&self) -> Uart1R {
+        Uart1R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Resetn of UART2"]
+    #[inline(always)]
+    pub fn uart2(&self) -> Uart2R {
+        Uart2R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Resetn of I2C0"]
+    #[inline(always)]
+    pub fn i2c0(&self) -> I2c0R {
+        I2c0R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Resetn of I2C1"]
+    #[inline(always)]
+    pub fn i2c1(&self) -> I2c1R {
+        I2c1R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Resetn of I2C2"]
+    #[inline(always)]
+    pub fn i2c2(&self) -> I2c2R {
+        I2c2R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Resetn of CAN0"]
+    #[inline(always)]
+    pub fn can0(&self) -> Can0R {
+        Can0R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Resetn of CAN1"]
+    #[inline(always)]
+    pub fn can1(&self) -> Can1R {
+        Can1R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Resetn of TRNG"]
+    #[inline(always)]
+    pub fn trng(&self) -> TrngR {
+        TrngR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Resetn of ADC"]
+    #[inline(always)]
+    pub fn adc(&self) -> AdcR {
+        AdcR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - Resetn of DAC"]
+    #[inline(always)]
+    pub fn dac(&self) -> DacR {
+        DacR::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Resetn of DMA"]
+    #[inline(always)]
+    pub fn dma(&self) -> DmaR {
+        DmaR::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Resetn of EBI"]
+    #[inline(always)]
+    pub fn ebi(&self) -> EbiR {
+        EbiR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Resetn of Ethernet"]
+    #[inline(always)]
+    pub fn eth(&self) -> EthR {
+        EthR::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Resetn of SpaceWire"]
+    #[inline(always)]
+    pub fn spw(&self) -> SpwR {
+        SpwR::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"]
+    #[inline(always)]
+    pub fn clkgen(&self) -> ClkgenR {
+        ClkgenR::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - Resetn of IRQ Router"]
+    #[inline(always)]
+    pub fn irq(&self) -> IrqR {
+        IrqR::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Resetn of IO CONFIG"]
+    #[inline(always)]
+    pub fn ioconfig(&self) -> IoconfigR {
+        IoconfigR::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Resetn of UTILITY peripheral"]
+    #[inline(always)]
+    pub fn utility(&self) -> UtilityR {
+        UtilityR::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Resetn of WDOG"]
+    #[inline(always)]
+    pub fn wdog(&self) -> WdogR {
+        WdogR::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - Resetn of PORTA"]
+    #[inline(always)]
+    pub fn porta(&self) -> PortaR {
+        PortaR::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - Resetn of PORTB"]
+    #[inline(always)]
+    pub fn portb(&self) -> PortbR {
+        PortbR::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - Resetn of PORTC"]
+    #[inline(always)]
+    pub fn portc(&self) -> PortcR {
+        PortcR::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - Resetn of PORTD"]
+    #[inline(always)]
+    pub fn portd(&self) -> PortdR {
+        PortdR::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - Resetn of PORTE"]
+    #[inline(always)]
+    pub fn porte(&self) -> PorteR {
+        PorteR::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - Resetn of PORTF"]
+    #[inline(always)]
+    pub fn portf(&self) -> PortfR {
+        PortfR::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - Resetn of PORTG"]
+    #[inline(always)]
+    pub fn portg(&self) -> PortgR {
+        PortgR::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Resetn of SPI0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi0(&mut self) -> Spi0W<PeripheralResetSpec> {
+        Spi0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Resetn of SPI1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi1(&mut self) -> Spi1W<PeripheralResetSpec> {
+        Spi1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Resetn of SPI2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi2(&mut self) -> Spi2W<PeripheralResetSpec> {
+        Spi2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Resetn of SPI3"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spi3(&mut self) -> Spi3W<PeripheralResetSpec> {
+        Spi3W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Resetn of UART0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart0(&mut self) -> Uart0W<PeripheralResetSpec> {
+        Uart0W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Resetn of UART1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart1(&mut self) -> Uart1W<PeripheralResetSpec> {
+        Uart1W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Resetn of UART2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn uart2(&mut self) -> Uart2W<PeripheralResetSpec> {
+        Uart2W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Resetn of I2C0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c0(&mut self) -> I2c0W<PeripheralResetSpec> {
+        I2c0W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Resetn of I2C1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c1(&mut self) -> I2c1W<PeripheralResetSpec> {
+        I2c1W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Resetn of I2C2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn i2c2(&mut self) -> I2c2W<PeripheralResetSpec> {
+        I2c2W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Resetn of CAN0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn can0(&mut self) -> Can0W<PeripheralResetSpec> {
+        Can0W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Resetn of CAN1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn can1(&mut self) -> Can1W<PeripheralResetSpec> {
+        Can1W::new(self, 11)
+    }
+    #[doc = "Bit 12 - Resetn of TRNG"]
+    #[inline(always)]
+    #[must_use]
+    pub fn trng(&mut self) -> TrngW<PeripheralResetSpec> {
+        TrngW::new(self, 12)
+    }
+    #[doc = "Bit 13 - Resetn of ADC"]
+    #[inline(always)]
+    #[must_use]
+    pub fn adc(&mut self) -> AdcW<PeripheralResetSpec> {
+        AdcW::new(self, 13)
+    }
+    #[doc = "Bit 14 - Resetn of DAC"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dac(&mut self) -> DacW<PeripheralResetSpec> {
+        DacW::new(self, 14)
+    }
+    #[doc = "Bit 15 - Resetn of DMA"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dma(&mut self) -> DmaW<PeripheralResetSpec> {
+        DmaW::new(self, 15)
+    }
+    #[doc = "Bit 16 - Resetn of EBI"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ebi(&mut self) -> EbiW<PeripheralResetSpec> {
+        EbiW::new(self, 16)
+    }
+    #[doc = "Bit 17 - Resetn of Ethernet"]
+    #[inline(always)]
+    #[must_use]
+    pub fn eth(&mut self) -> EthW<PeripheralResetSpec> {
+        EthW::new(self, 17)
+    }
+    #[doc = "Bit 18 - Resetn of SpaceWire"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spw(&mut self) -> SpwW<PeripheralResetSpec> {
+        SpwW::new(self, 18)
+    }
+    #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"]
+    #[inline(always)]
+    #[must_use]
+    pub fn clkgen(&mut self) -> ClkgenW<PeripheralResetSpec> {
+        ClkgenW::new(self, 19)
+    }
+    #[doc = "Bit 20 - Resetn of IRQ Router"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq(&mut self) -> IrqW<PeripheralResetSpec> {
+        IrqW::new(self, 20)
+    }
+    #[doc = "Bit 21 - Resetn of IO CONFIG"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ioconfig(&mut self) -> IoconfigW<PeripheralResetSpec> {
+        IoconfigW::new(self, 21)
+    }
+    #[doc = "Bit 22 - Resetn of UTILITY peripheral"]
+    #[inline(always)]
+    #[must_use]
+    pub fn utility(&mut self) -> UtilityW<PeripheralResetSpec> {
+        UtilityW::new(self, 22)
+    }
+    #[doc = "Bit 23 - Resetn of WDOG"]
+    #[inline(always)]
+    #[must_use]
+    pub fn wdog(&mut self) -> WdogW<PeripheralResetSpec> {
+        WdogW::new(self, 23)
+    }
+    #[doc = "Bit 24 - Resetn of PORTA"]
+    #[inline(always)]
+    #[must_use]
+    pub fn porta(&mut self) -> PortaW<PeripheralResetSpec> {
+        PortaW::new(self, 24)
+    }
+    #[doc = "Bit 25 - Resetn of PORTB"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portb(&mut self) -> PortbW<PeripheralResetSpec> {
+        PortbW::new(self, 25)
+    }
+    #[doc = "Bit 26 - Resetn of PORTC"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portc(&mut self) -> PortcW<PeripheralResetSpec> {
+        PortcW::new(self, 26)
+    }
+    #[doc = "Bit 27 - Resetn of PORTD"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portd(&mut self) -> PortdW<PeripheralResetSpec> {
+        PortdW::new(self, 27)
+    }
+    #[doc = "Bit 28 - Resetn of PORTE"]
+    #[inline(always)]
+    #[must_use]
+    pub fn porte(&mut self) -> PorteW<PeripheralResetSpec> {
+        PorteW::new(self, 28)
+    }
+    #[doc = "Bit 29 - Resetn of PORTF"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portf(&mut self) -> PortfW<PeripheralResetSpec> {
+        PortfW::new(self, 29)
+    }
+    #[doc = "Bit 30 - Resetn of PORTG"]
+    #[inline(always)]
+    #[must_use]
+    pub fn portg(&mut self) -> PortgW<PeripheralResetSpec> {
+        PortgW::new(self, 30)
+    }
+}
+#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeripheralResetSpec;
+impl crate::RegisterSpec for PeripheralResetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`peripheral_reset::R`](R) reader structure"]
+impl crate::Readable for PeripheralResetSpec {}
+#[doc = "`write(|w| ..)` method takes [`peripheral_reset::W`](W) writer structure"]
+impl crate::Writable for PeripheralResetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPHERAL_RESET to value 0x7f7b_efff"]
+impl crate::Resettable for PeripheralResetSpec {
+    const RESET_VALUE: u32 = 0x7f7b_efff;
+}
--- a/va416xx/src/sysconfig/pmu_ctrl.rs
+++ b/va416xx/src/sysconfig/pmu_ctrl.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PMU_CTRL` reader"]
+pub type R = crate::R<PmuCtrlSpec>;
+#[doc = "Register `PMU_CTRL` writer"]
+pub type W = crate::W<PmuCtrlSpec>;
+#[doc = "Field `LVL_SLCT` reader - Select the POK detect level"]
+pub type LvlSlctR = crate::FieldReader;
+#[doc = "Field `LVL_SLCT` writer - Select the POK detect level"]
+pub type LvlSlctW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - Select the POK detect level"]
+    #[inline(always)]
+    pub fn lvl_slct(&self) -> LvlSlctR {
+        LvlSlctR::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Select the POK detect level"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lvl_slct(&mut self) -> LvlSlctW<PmuCtrlSpec> {
+        LvlSlctW::new(self, 0)
+    }
+}
+#[doc = "PMU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PmuCtrlSpec;
+impl crate::RegisterSpec for PmuCtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pmu_ctrl::R`](R) reader structure"]
+impl crate::Readable for PmuCtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`pmu_ctrl::W`](W) writer structure"]
+impl crate::Writable for PmuCtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PMU_CTRL to value 0"]
+impl crate::Resettable for PmuCtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/procid.rs
+++ b/va416xx/src/sysconfig/procid.rs
@ -0,0 +1,18 @@
+#[doc = "Register `PROCID` reader"]
+pub type R = crate::R<ProcidSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ProcidSpec;
+impl crate::RegisterSpec for ProcidSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`procid::R`](R) reader structure"]
+impl crate::Readable for ProcidSpec {}
+#[doc = "`reset()` method sets PROCID to value 0x0400_57e3"]
+impl crate::Resettable for ProcidSpec {
+    const RESET_VALUE: u32 = 0x0400_57e3;
+}
--- a/va416xx/src/sysconfig/ram0_mbe.rs
+++ b/va416xx/src/sysconfig/ram0_mbe.rs
@ -0,0 +1,40 @@
+#[doc = "Register `RAM0_MBE` reader"]
+pub type R = crate::R<Ram0MbeSpec>;
+#[doc = "Register `RAM0_MBE` writer"]
+pub type W = crate::W<Ram0MbeSpec>;
+#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"]
+pub type CountR = crate::FieldReader<u16>;
+#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"]
+pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> CountR {
+        CountR::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    #[must_use]
+    pub fn count(&mut self) -> CountW<Ram0MbeSpec> {
+        CountW::new(self, 0)
+    }
+}
+#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_mbe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_mbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Ram0MbeSpec;
+impl crate::RegisterSpec for Ram0MbeSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ram0_mbe::R`](R) reader structure"]
+impl crate::Readable for Ram0MbeSpec {}
+#[doc = "`write(|w| ..)` method takes [`ram0_mbe::W`](W) writer structure"]
+impl crate::Writable for Ram0MbeSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RAM0_MBE to value 0"]
+impl crate::Resettable for Ram0MbeSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/ram0_sbe.rs
+++ b/va416xx/src/sysconfig/ram0_sbe.rs
@ -0,0 +1,40 @@
+#[doc = "Register `RAM0_SBE` reader"]
+pub type R = crate::R<Ram0SbeSpec>;
+#[doc = "Register `RAM0_SBE` writer"]
+pub type W = crate::W<Ram0SbeSpec>;
+#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"]
+pub type CountR = crate::FieldReader<u16>;
+#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"]
+pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> CountR {
+        CountR::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    #[must_use]
+    pub fn count(&mut self) -> CountW<Ram0SbeSpec> {
+        CountW::new(self, 0)
+    }
+}
+#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_sbe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Ram0SbeSpec;
+impl crate::RegisterSpec for Ram0SbeSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ram0_sbe::R`](R) reader structure"]
+impl crate::Readable for Ram0SbeSpec {}
+#[doc = "`write(|w| ..)` method takes [`ram0_sbe::W`](W) writer structure"]
+impl crate::Writable for Ram0SbeSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RAM0_SBE to value 0"]
+impl crate::Resettable for Ram0SbeSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/refresh_config_h.rs
+++ b/va416xx/src/sysconfig/refresh_config_h.rs
@ -0,0 +1,55 @@
+#[doc = "Register `REFRESH_CONFIG_H` reader"]
+pub type R = crate::R<RefreshConfigHSpec>;
+#[doc = "Register `REFRESH_CONFIG_H` writer"]
+pub type W = crate::W<RefreshConfigHSpec>;
+#[doc = "Field `DIVCOUNT` reader - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub type DivcountR = crate::FieldReader;
+#[doc = "Field `DIVCOUNT` writer - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub type DivcountW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `TESTMODE` reader - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+pub type TestmodeR = crate::FieldReader;
+#[doc = "Field `TESTMODE` writer - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+pub type TestmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    pub fn divcount(&self) -> DivcountR {
+        DivcountR::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+    #[inline(always)]
+    pub fn testmode(&self) -> TestmodeR {
+        TestmodeR::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    #[must_use]
+    pub fn divcount(&mut self) -> DivcountW<RefreshConfigHSpec> {
+        DivcountW::new(self, 0)
+    }
+    #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+    #[inline(always)]
+    #[must_use]
+    pub fn testmode(&mut self) -> TestmodeW<RefreshConfigHSpec> {
+        TestmodeW::new(self, 30)
+    }
+}
+#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_h::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RefreshConfigHSpec;
+impl crate::RegisterSpec for RefreshConfigHSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`refresh_config_h::R`](R) reader structure"]
+impl crate::Readable for RefreshConfigHSpec {}
+#[doc = "`write(|w| ..)` method takes [`refresh_config_h::W`](W) writer structure"]
+impl crate::Writable for RefreshConfigHSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets REFRESH_CONFIG_H to value 0"]
+impl crate::Resettable for RefreshConfigHSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/refresh_config_l.rs
+++ b/va416xx/src/sysconfig/refresh_config_l.rs
@ -0,0 +1,40 @@
+#[doc = "Register `REFRESH_CONFIG_L` reader"]
+pub type R = crate::R<RefreshConfigLSpec>;
+#[doc = "Register `REFRESH_CONFIG_L` writer"]
+pub type W = crate::W<RefreshConfigLSpec>;
+#[doc = "Field `DIVCOUNT` reader - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub type DivcountR = crate::FieldReader<u32>;
+#[doc = "Field `DIVCOUNT` writer - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub type DivcountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    pub fn divcount(&self) -> DivcountR {
+        DivcountR::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    #[must_use]
+    pub fn divcount(&mut self) -> DivcountW<RefreshConfigLSpec> {
+        DivcountW::new(self, 0)
+    }
+}
+#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_l::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_l::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RefreshConfigLSpec;
+impl crate::RegisterSpec for RefreshConfigLSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`refresh_config_l::R`](R) reader structure"]
+impl crate::Readable for RefreshConfigLSpec {}
+#[doc = "`write(|w| ..)` method takes [`refresh_config_l::W`](W) writer structure"]
+impl crate::Writable for RefreshConfigLSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets REFRESH_CONFIG_L to value 0x0f"]
+impl crate::Resettable for RefreshConfigLSpec {
+    const RESET_VALUE: u32 = 0x0f;
+}
--- a/va416xx/src/sysconfig/rom_prot.rs
+++ b/va416xx/src/sysconfig/rom_prot.rs
@ -0,0 +1,40 @@
+#[doc = "Register `ROM_PROT` reader"]
+pub type R = crate::R<RomProtSpec>;
+#[doc = "Register `ROM_PROT` writer"]
+pub type W = crate::W<RomProtSpec>;
+#[doc = "Field `WREN` reader - ROM Write Enable Bit"]
+pub type WrenR = crate::BitReader;
+#[doc = "Field `WREN` writer - ROM Write Enable Bit"]
+pub type WrenW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - ROM Write Enable Bit"]
+    #[inline(always)]
+    pub fn wren(&self) -> WrenR {
+        WrenR::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ROM Write Enable Bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn wren(&mut self) -> WrenW<RomProtSpec> {
+        WrenW::new(self, 0)
+    }
+}
+#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomProtSpec;
+impl crate::RegisterSpec for RomProtSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_prot::R`](R) reader structure"]
+impl crate::Readable for RomProtSpec {}
+#[doc = "`write(|w| ..)` method takes [`rom_prot::W`](W) writer structure"]
+impl crate::Writable for RomProtSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ROM_PROT to value 0"]
+impl crate::Resettable for RomProtSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/rom_retries.rs
+++ b/va416xx/src/sysconfig/rom_retries.rs
@ -0,0 +1,22 @@
+#[doc = "Register `ROM_RETRIES` reader"]
+pub type R = crate::R<RomRetriesSpec>;
+#[doc = "Field `COUNT` reader - Count of ROM block Retries"]
+pub type CountR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:7 - Count of ROM block Retries"]
+    #[inline(always)]
+    pub fn count(&self) -> CountR {
+        CountR::new((self.bits & 0xff) as u8)
+    }
+}
+#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomRetriesSpec;
+impl crate::RegisterSpec for RomRetriesSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_retries::R`](R) reader structure"]
+impl crate::Readable for RomRetriesSpec {}
+#[doc = "`reset()` method sets ROM_RETRIES to value 0"]
+impl crate::Resettable for RomRetriesSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/rom_scrub.rs
+++ b/va416xx/src/sysconfig/rom_scrub.rs
@ -0,0 +1,48 @@
+#[doc = "Register `ROM_SCRUB` reader"]
+pub type R = crate::R<RomScrubSpec>;
+#[doc = "Register `ROM_SCRUB` writer"]
+pub type W = crate::W<RomScrubSpec>;
+#[doc = "Field `VALUE` reader - Counter divide value"]
+pub type ValueR = crate::FieldReader<u32>;
+#[doc = "Field `VALUE` writer - Counter divide value"]
+pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+#[doc = "Field `RESET` writer - Reset Counter"]
+pub type ResetW<'a, REG> = crate::BitWriter1C<'a, REG>;
+impl R {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&self) -> ValueR {
+        ValueR::new(self.bits & 0x00ff_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    #[must_use]
+    pub fn value(&mut self) -> ValueW<RomScrubSpec> {
+        ValueW::new(self, 0)
+    }
+    #[doc = "Bit 31 - Reset Counter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn reset(&mut self) -> ResetW<RomScrubSpec> {
+        ResetW::new(self, 31)
+    }
+}
+#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RomScrubSpec;
+impl crate::RegisterSpec for RomScrubSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rom_scrub::R`](R) reader structure"]
+impl crate::Readable for RomScrubSpec {}
+#[doc = "`write(|w| ..)` method takes [`rom_scrub::W`](W) writer structure"]
+impl crate::Writable for RomScrubSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000;
+}
+#[doc = "`reset()` method sets ROM_SCRUB to value 0"]
+impl crate::Resettable for RomScrubSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/rst_stat.rs
+++ b/va416xx/src/sysconfig/rst_stat.rs
@ -0,0 +1,107 @@
+#[doc = "Register `RST_STAT` reader"]
+pub type R = crate::R<RstStatSpec>;
+#[doc = "Register `RST_STAT` writer"]
+pub type W = crate::W<RstStatSpec>;
+#[doc = "Field `POR` reader - Power On Reset Status"]
+pub type PorR = crate::BitReader;
+#[doc = "Field `POR` writer - Power On Reset Status"]
+pub type PorW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXTRST` reader - External Reset Status"]
+pub type ExtrstR = crate::BitReader;
+#[doc = "Field `EXTRST` writer - External Reset Status"]
+pub type ExtrstW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"]
+pub type SysrstreqR = crate::BitReader;
+#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"]
+pub type SysrstreqW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"]
+pub type LookupR = crate::BitReader;
+#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"]
+pub type LookupW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"]
+pub type WatchdogR = crate::BitReader;
+#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"]
+pub type WatchdogW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEMERR` reader - Memory Error Reset Status"]
+pub type MemerrR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&self) -> PorR {
+        PorR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&self) -> ExtrstR {
+        ExtrstR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&self) -> SysrstreqR {
+        SysrstreqR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&self) -> LookupR {
+        LookupR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&self) -> WatchdogR {
+        WatchdogR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    pub fn memerr(&self) -> MemerrR {
+        MemerrR::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn por(&mut self) -> PorW<RstStatSpec> {
+        PorW::new(self, 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn extrst(&mut self) -> ExtrstW<RstStatSpec> {
+        ExtrstW::new(self, 1)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sysrstreq(&mut self) -> SysrstreqW<RstStatSpec> {
+        SysrstreqW::new(self, 2)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lookup(&mut self) -> LookupW<RstStatSpec> {
+        LookupW::new(self, 3)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn watchdog(&mut self) -> WatchdogW<RstStatSpec> {
+        WatchdogW::new(self, 4)
+    }
+}
+#[doc = "System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RstStatSpec;
+impl crate::RegisterSpec for RstStatSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rst_stat::R`](R) reader structure"]
+impl crate::Readable for RstStatSpec {}
+#[doc = "`write(|w| ..)` method takes [`rst_stat::W`](W) writer structure"]
+impl crate::Writable for RstStatSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RST_STAT to value 0"]
+impl crate::Resettable for RstStatSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/spw_m4_ctrl.rs
+++ b/va416xx/src/sysconfig/spw_m4_ctrl.rs
@ -0,0 +1,70 @@
+#[doc = "Register `SPW_M4_CTRL` reader"]
+pub type R = crate::R<SpwM4CtrlSpec>;
+#[doc = "Register `SPW_M4_CTRL` writer"]
+pub type W = crate::W<SpwM4CtrlSpec>;
+#[doc = "Field `REG_WR_KEY` reader - Fuse-analog register writes enabled when key = 0xfeed"]
+pub type RegWrKeyR = crate::FieldReader<u16>;
+#[doc = "Field `REG_WR_KEY` writer - Fuse-analog register writes enabled when key = 0xfeed"]
+pub type RegWrKeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `SPW_PAD_EN` reader - SPW pad enable"]
+pub type SpwPadEnR = crate::BitReader;
+#[doc = "Field `SPW_PAD_EN` writer - SPW pad enable"]
+pub type SpwPadEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LREN` reader - Lockup reset enable"]
+pub type LrenR = crate::BitReader;
+#[doc = "Field `LREN` writer - Lockup reset enable"]
+pub type LrenW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"]
+    #[inline(always)]
+    pub fn reg_wr_key(&self) -> RegWrKeyR {
+        RegWrKeyR::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 16 - SPW pad enable"]
+    #[inline(always)]
+    pub fn spw_pad_en(&self) -> SpwPadEnR {
+        SpwPadEnR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Lockup reset enable"]
+    #[inline(always)]
+    pub fn lren(&self) -> LrenR {
+        LrenR::new(((self.bits >> 17) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"]
+    #[inline(always)]
+    #[must_use]
+    pub fn reg_wr_key(&mut self) -> RegWrKeyW<SpwM4CtrlSpec> {
+        RegWrKeyW::new(self, 0)
+    }
+    #[doc = "Bit 16 - SPW pad enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn spw_pad_en(&mut self) -> SpwPadEnW<SpwM4CtrlSpec> {
+        SpwPadEnW::new(self, 16)
+    }
+    #[doc = "Bit 17 - Lockup reset enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lren(&mut self) -> LrenW<SpwM4CtrlSpec> {
+        LrenW::new(self, 17)
+    }
+}
+#[doc = "SPW M4 control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spw_m4_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SpwM4CtrlSpec;
+impl crate::RegisterSpec for SpwM4CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`spw_m4_ctrl::R`](R) reader structure"]
+impl crate::Readable for SpwM4CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`spw_m4_ctrl::W`](W) writer structure"]
+impl crate::Writable for SpwM4CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SPW_M4_CTRL to value 0x0003_0000"]
+impl crate::Resettable for SpwM4CtrlSpec {
+    const RESET_VALUE: u32 = 0x0003_0000;
+}
--- a/va416xx/src/sysconfig/sw_clkdiv10.rs
+++ b/va416xx/src/sysconfig/sw_clkdiv10.rs
@ -0,0 +1,40 @@
+#[doc = "Register `SW_CLKDIV10` reader"]
+pub type R = crate::R<SwClkdiv10Spec>;
+#[doc = "Register `SW_CLKDIV10` writer"]
+pub type W = crate::W<SwClkdiv10Spec>;
+#[doc = "Field `SW_CLKDIV10` reader - Defines the initial value for the SpW clock, defaults to divide by ten"]
+pub type SwClkdiv10R = crate::FieldReader;
+#[doc = "Field `SW_CLKDIV10` writer - Defines the initial value for the SpW clock, defaults to divide by ten"]
+pub type SwClkdiv10W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"]
+    #[inline(always)]
+    pub fn sw_clkdiv10(&self) -> SwClkdiv10R {
+        SwClkdiv10R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sw_clkdiv10(&mut self) -> SwClkdiv10W<SwClkdiv10Spec> {
+        SwClkdiv10W::new(self, 0)
+    }
+}
+#[doc = "Initial SpW Clock Divider Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_clkdiv10::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_clkdiv10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SwClkdiv10Spec;
+impl crate::RegisterSpec for SwClkdiv10Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sw_clkdiv10::R`](R) reader structure"]
+impl crate::Readable for SwClkdiv10Spec {}
+#[doc = "`write(|w| ..)` method takes [`sw_clkdiv10::W`](W) writer structure"]
+impl crate::Writable for SwClkdiv10Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SW_CLKDIV10 to value 0x09"]
+impl crate::Resettable for SwClkdiv10Spec {
+    const RESET_VALUE: u32 = 0x09;
+}
--- a/va416xx/src/sysconfig/tim_clk_enable.rs
+++ b/va416xx/src/sysconfig/tim_clk_enable.rs
@ -0,0 +1,40 @@
+#[doc = "Register `TIM_CLK_ENABLE` reader"]
+pub type R = crate::R<TimClkEnableSpec>;
+#[doc = "Register `TIM_CLK_ENABLE` writer"]
+pub type W = crate::W<TimClkEnableSpec>;
+#[doc = "Field `TIMERS` reader - Clock enable of a given TIMER"]
+pub type TimersR = crate::FieldReader<u32>;
+#[doc = "Field `TIMERS` writer - Clock enable of a given TIMER"]
+pub type TimersW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Clock enable of a given TIMER"]
+    #[inline(always)]
+    pub fn timers(&self) -> TimersR {
+        TimersR::new(self.bits & 0x00ff_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Clock enable of a given TIMER"]
+    #[inline(always)]
+    #[must_use]
+    pub fn timers(&mut self) -> TimersW<TimClkEnableSpec> {
+        TimersW::new(self, 0)
+    }
+}
+#[doc = "TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TimClkEnableSpec;
+impl crate::RegisterSpec for TimClkEnableSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tim_clk_enable::R`](R) reader structure"]
+impl crate::Readable for TimClkEnableSpec {}
+#[doc = "`write(|w| ..)` method takes [`tim_clk_enable::W`](W) writer structure"]
+impl crate::Writable for TimClkEnableSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"]
+impl crate::Resettable for TimClkEnableSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/sysconfig/tim_reset.rs
+++ b/va416xx/src/sysconfig/tim_reset.rs
@ -0,0 +1,40 @@
+#[doc = "Register `TIM_RESET` reader"]
+pub type R = crate::R<TimResetSpec>;
+#[doc = "Register `TIM_RESET` writer"]
+pub type W = crate::W<TimResetSpec>;
+#[doc = "Field `TIM_RESET` reader - Reset of a given TIMER"]
+pub type TimResetR = crate::FieldReader<u32>;
+#[doc = "Field `TIM_RESET` writer - Reset of a given TIMER"]
+pub type TimResetW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Reset of a given TIMER"]
+    #[inline(always)]
+    pub fn tim_reset(&self) -> TimResetR {
+        TimResetR::new(self.bits & 0x00ff_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Reset of a given TIMER"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tim_reset(&mut self) -> TimResetW<TimResetSpec> {
+        TimResetW::new(self, 0)
+    }
+}
+#[doc = "TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TimResetSpec;
+impl crate::RegisterSpec for TimResetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tim_reset::R`](R) reader structure"]
+impl crate::Readable for TimResetSpec {}
+#[doc = "`write(|w| ..)` method takes [`tim_reset::W`](W) writer structure"]
+impl crate::Writable for TimResetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"]
+impl crate::Resettable for TimResetSpec {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}
--- a/va416xx/src/sysconfig/wakeup_cnt.rs
+++ b/va416xx/src/sysconfig/wakeup_cnt.rs
@ -0,0 +1,55 @@
+#[doc = "Register `WAKEUP_CNT` reader"]
+pub type R = crate::R<WakeupCntSpec>;
+#[doc = "Register `WAKEUP_CNT` writer"]
+pub type W = crate::W<WakeupCntSpec>;
+#[doc = "Field `WKUP_CNT` reader - Used to set a time to wake up the processor after the device has been put in a low power state"]
+pub type WkupCntR = crate::FieldReader;
+#[doc = "Field `WKUP_CNT` writer - Used to set a time to wake up the processor after the device has been put in a low power state"]
+pub type WkupCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CNTSTRT` reader - Launch SLP mode in analog block"]
+pub type CntstrtR = crate::BitReader;
+#[doc = "Field `CNTSTRT` writer - Launch SLP mode in analog block"]
+pub type CntstrtW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"]
+    #[inline(always)]
+    pub fn wkup_cnt(&self) -> WkupCntR {
+        WkupCntR::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - Launch SLP mode in analog block"]
+    #[inline(always)]
+    pub fn cntstrt(&self) -> CntstrtR {
+        CntstrtR::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"]
+    #[inline(always)]
+    #[must_use]
+    pub fn wkup_cnt(&mut self) -> WkupCntW<WakeupCntSpec> {
+        WkupCntW::new(self, 0)
+    }
+    #[doc = "Bit 3 - Launch SLP mode in analog block"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cntstrt(&mut self) -> CntstrtW<WakeupCntSpec> {
+        CntstrtW::new(self, 3)
+    }
+}
+#[doc = "Wakeup Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WakeupCntSpec;
+impl crate::RegisterSpec for WakeupCntSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wakeup_cnt::R`](R) reader structure"]
+impl crate::Readable for WakeupCntSpec {}
+#[doc = "`write(|w| ..)` method takes [`wakeup_cnt::W`](W) writer structure"]
+impl crate::Writable for WakeupCntSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WAKEUP_CNT to value 0x07"]
+impl crate::Resettable for WakeupCntSpec {
+    const RESET_VALUE: u32 = 0x07;
+}