Monorepo for Rust support of VA416XX family of radiation hardened MCUs
This commit is contained in:
40
va416xx/src/tim0/cascade0.rs
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40
va416xx/src/tim0/cascade0.rs
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@ -0,0 +1,40 @@
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#[doc = "Register `CASCADE0` reader"]
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pub type R = crate::R<Cascade0Spec>;
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#[doc = "Register `CASCADE0` writer"]
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pub type W = crate::W<Cascade0Spec>;
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#[doc = "Field `CASSEL` reader - Cascade Selection"]
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pub type CasselR = crate::FieldReader;
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#[doc = "Field `CASSEL` writer - Cascade Selection"]
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pub type CasselW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
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impl R {
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#[doc = "Bits 0:7 - Cascade Selection"]
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#[inline(always)]
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pub fn cassel(&self) -> CasselR {
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CasselR::new((self.bits & 0xff) as u8)
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}
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}
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impl W {
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#[doc = "Bits 0:7 - Cascade Selection"]
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#[inline(always)]
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#[must_use]
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pub fn cassel(&mut self) -> CasselW<Cascade0Spec> {
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CasselW::new(self, 0)
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}
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}
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#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Cascade0Spec;
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impl crate::RegisterSpec for Cascade0Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`cascade0::R`](R) reader structure"]
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impl crate::Readable for Cascade0Spec {}
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#[doc = "`write(|w| ..)` method takes [`cascade0::W`](W) writer structure"]
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impl crate::Writable for Cascade0Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CASCADE0 to value 0"]
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impl crate::Resettable for Cascade0Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/tim0/cnt_value.rs
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27
va416xx/src/tim0/cnt_value.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CNT_VALUE` reader"]
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pub type R = crate::R<CntValueSpec>;
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#[doc = "Register `CNT_VALUE` writer"]
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pub type W = crate::W<CntValueSpec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct CntValueSpec;
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impl crate::RegisterSpec for CntValueSpec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`cnt_value::R`](R) reader structure"]
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impl crate::Readable for CntValueSpec {}
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#[doc = "`write(|w| ..)` method takes [`cnt_value::W`](W) writer structure"]
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impl crate::Writable for CntValueSpec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CNT_VALUE to value 0"]
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impl crate::Resettable for CntValueSpec {
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const RESET_VALUE: u32 = 0;
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}
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175
va416xx/src/tim0/csd_ctrl.rs
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175
va416xx/src/tim0/csd_ctrl.rs
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@ -0,0 +1,175 @@
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#[doc = "Register `CSD_CTRL` reader"]
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pub type R = crate::R<CsdCtrlSpec>;
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#[doc = "Register `CSD_CTRL` writer"]
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pub type W = crate::W<CsdCtrlSpec>;
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#[doc = "Field `CSDEN0` reader - Cascade 0 Enable"]
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pub type Csden0R = crate::BitReader;
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#[doc = "Field `CSDEN0` writer - Cascade 0 Enable"]
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pub type Csden0W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDINV0` reader - Cascade 0 Invert"]
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pub type Csdinv0R = crate::BitReader;
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#[doc = "Field `CSDINV0` writer - Cascade 0 Invert"]
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pub type Csdinv0W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDEN1` reader - Cascade 1 Enable"]
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pub type Csden1R = crate::BitReader;
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#[doc = "Field `CSDEN1` writer - Cascade 1 Enable"]
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pub type Csden1W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDINV1` reader - Cascade 1 Invert"]
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pub type Csdinv1R = crate::BitReader;
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#[doc = "Field `CSDINV1` writer - Cascade 1 Invert"]
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pub type Csdinv1W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `DCASOP` reader - Dual Cascade Operation (0:AND, 1:OR)"]
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pub type DcasopR = crate::BitReader;
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#[doc = "Field `DCASOP` writer - Dual Cascade Operation (0:AND, 1:OR)"]
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pub type DcasopW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDTRG0` reader - Cascade 0 Enabled as Trigger"]
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pub type Csdtrg0R = crate::BitReader;
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#[doc = "Field `CSDTRG0` writer - Cascade 0 Enabled as Trigger"]
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pub type Csdtrg0W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDTRG1` reader - Cascade 1 Enabled as Trigger"]
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pub type Csdtrg1R = crate::BitReader;
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#[doc = "Field `CSDTRG1` writer - Cascade 1 Enabled as Trigger"]
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pub type Csdtrg1W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDEN2` reader - Cascade 2 Enable"]
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pub type Csden2R = crate::BitReader;
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#[doc = "Field `CSDEN2` writer - Cascade 2 Enable"]
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pub type Csden2W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDINV2` reader - Cascade 2 Invert"]
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pub type Csdinv2R = crate::BitReader;
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#[doc = "Field `CSDINV2` writer - Cascade 2 Invert"]
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pub type Csdinv2W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `CSDTRG2` reader - Cascade 2 Trigger mode"]
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pub type Csdtrg2R = crate::BitReader;
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#[doc = "Field `CSDTRG2` writer - Cascade 2 Trigger mode"]
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pub type Csdtrg2W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Cascade 0 Enable"]
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#[inline(always)]
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pub fn csden0(&self) -> Csden0R {
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Csden0R::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - Cascade 0 Invert"]
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#[inline(always)]
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pub fn csdinv0(&self) -> Csdinv0R {
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Csdinv0R::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - Cascade 1 Enable"]
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#[inline(always)]
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pub fn csden1(&self) -> Csden1R {
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Csden1R::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - Cascade 1 Invert"]
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#[inline(always)]
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pub fn csdinv1(&self) -> Csdinv1R {
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Csdinv1R::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
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#[inline(always)]
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pub fn dcasop(&self) -> DcasopR {
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DcasopR::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
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#[inline(always)]
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pub fn csdtrg0(&self) -> Csdtrg0R {
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Csdtrg0R::new(((self.bits >> 6) & 1) != 0)
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}
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#[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
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#[inline(always)]
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pub fn csdtrg1(&self) -> Csdtrg1R {
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Csdtrg1R::new(((self.bits >> 7) & 1) != 0)
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}
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#[doc = "Bit 8 - Cascade 2 Enable"]
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#[inline(always)]
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pub fn csden2(&self) -> Csden2R {
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Csden2R::new(((self.bits >> 8) & 1) != 0)
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}
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#[doc = "Bit 9 - Cascade 2 Invert"]
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#[inline(always)]
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pub fn csdinv2(&self) -> Csdinv2R {
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Csdinv2R::new(((self.bits >> 9) & 1) != 0)
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}
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#[doc = "Bit 10 - Cascade 2 Trigger mode"]
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#[inline(always)]
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pub fn csdtrg2(&self) -> Csdtrg2R {
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Csdtrg2R::new(((self.bits >> 10) & 1) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Cascade 0 Enable"]
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#[inline(always)]
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#[must_use]
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pub fn csden0(&mut self) -> Csden0W<CsdCtrlSpec> {
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Csden0W::new(self, 0)
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}
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#[doc = "Bit 1 - Cascade 0 Invert"]
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#[inline(always)]
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#[must_use]
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pub fn csdinv0(&mut self) -> Csdinv0W<CsdCtrlSpec> {
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Csdinv0W::new(self, 1)
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}
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#[doc = "Bit 2 - Cascade 1 Enable"]
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#[inline(always)]
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#[must_use]
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pub fn csden1(&mut self) -> Csden1W<CsdCtrlSpec> {
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Csden1W::new(self, 2)
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}
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#[doc = "Bit 3 - Cascade 1 Invert"]
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#[inline(always)]
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#[must_use]
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pub fn csdinv1(&mut self) -> Csdinv1W<CsdCtrlSpec> {
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Csdinv1W::new(self, 3)
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}
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#[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
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#[inline(always)]
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#[must_use]
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pub fn dcasop(&mut self) -> DcasopW<CsdCtrlSpec> {
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DcasopW::new(self, 4)
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}
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#[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
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#[inline(always)]
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#[must_use]
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pub fn csdtrg0(&mut self) -> Csdtrg0W<CsdCtrlSpec> {
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Csdtrg0W::new(self, 6)
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}
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#[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
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#[inline(always)]
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#[must_use]
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pub fn csdtrg1(&mut self) -> Csdtrg1W<CsdCtrlSpec> {
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Csdtrg1W::new(self, 7)
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}
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#[doc = "Bit 8 - Cascade 2 Enable"]
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#[inline(always)]
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#[must_use]
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pub fn csden2(&mut self) -> Csden2W<CsdCtrlSpec> {
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Csden2W::new(self, 8)
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}
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#[doc = "Bit 9 - Cascade 2 Invert"]
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#[inline(always)]
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#[must_use]
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pub fn csdinv2(&mut self) -> Csdinv2W<CsdCtrlSpec> {
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Csdinv2W::new(self, 9)
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}
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#[doc = "Bit 10 - Cascade 2 Trigger mode"]
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#[inline(always)]
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#[must_use]
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pub fn csdtrg2(&mut self) -> Csdtrg2W<CsdCtrlSpec> {
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Csdtrg2W::new(self, 10)
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}
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}
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#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct CsdCtrlSpec;
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impl crate::RegisterSpec for CsdCtrlSpec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`csd_ctrl::R`](R) reader structure"]
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impl crate::Readable for CsdCtrlSpec {}
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#[doc = "`write(|w| ..)` method takes [`csd_ctrl::W`](W) writer structure"]
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impl crate::Writable for CsdCtrlSpec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CSD_CTRL to value 0"]
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impl crate::Resettable for CsdCtrlSpec {
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const RESET_VALUE: u32 = 0;
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}
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258
va416xx/src/tim0/ctrl.rs
Normal file
258
va416xx/src/tim0/ctrl.rs
Normal file
@ -0,0 +1,258 @@
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#[doc = "Register `CTRL` reader"]
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pub type R = crate::R<CtrlSpec>;
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#[doc = "Register `CTRL` writer"]
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pub type W = crate::W<CtrlSpec>;
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#[doc = "Field `ENABLE` reader - Counter Enable"]
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pub type EnableR = crate::BitReader;
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#[doc = "Field `ENABLE` writer - Counter Enable"]
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pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `ACTIVE` reader - Counter Active"]
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pub type ActiveR = crate::BitReader;
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#[doc = "Field `AUTO_DISABLE` reader - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
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pub type AutoDisableR = crate::BitReader;
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#[doc = "Field `AUTO_DISABLE` writer - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
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pub type AutoDisableW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `AUTO_DEACTIVATE` reader - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
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pub type AutoDeactivateR = crate::BitReader;
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#[doc = "Field `AUTO_DEACTIVATE` writer - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
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pub type AutoDeactivateW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `IRQ_ENB` reader - Interrupt Enable"]
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pub type IrqEnbR = crate::BitReader;
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#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"]
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pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Counter Status Selection\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[repr(u8)]
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pub enum StatusSel {
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#[doc = "0: Single cycle pulse when the counter reaches 0"]
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Done = 0,
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#[doc = "1: Returns the counter ACTIVE bit"]
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Active = 1,
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#[doc = "2: Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."]
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Toggle = 2,
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#[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
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Pwma = 3,
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#[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
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Pwmb = 4,
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#[doc = "5: Returns the counter ENABLED bit"]
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Enabled = 5,
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#[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
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PwmaActive = 6,
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}
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impl From<StatusSel> for u8 {
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#[inline(always)]
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fn from(variant: StatusSel) -> Self {
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variant as _
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||||
}
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}
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impl crate::FieldSpec for StatusSel {
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type Ux = u8;
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}
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impl crate::IsEnum for StatusSel {}
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#[doc = "Field `STATUS_SEL` reader - Counter Status Selection"]
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pub type StatusSelR = crate::FieldReader<StatusSel>;
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impl StatusSelR {
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#[doc = "Get enumerated values variant"]
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#[inline(always)]
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pub const fn variant(&self) -> Option<StatusSel> {
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match self.bits {
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0 => Some(StatusSel::Done),
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1 => Some(StatusSel::Active),
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2 => Some(StatusSel::Toggle),
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3 => Some(StatusSel::Pwma),
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4 => Some(StatusSel::Pwmb),
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5 => Some(StatusSel::Enabled),
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6 => Some(StatusSel::PwmaActive),
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_ => None,
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}
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}
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#[doc = "Single cycle pulse when the counter reaches 0"]
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#[inline(always)]
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pub fn is_done(&self) -> bool {
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*self == StatusSel::Done
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}
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#[doc = "Returns the counter ACTIVE bit"]
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#[inline(always)]
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pub fn is_active(&self) -> bool {
|
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*self == StatusSel::Active
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}
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#[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."]
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#[inline(always)]
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pub fn is_toggle(&self) -> bool {
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*self == StatusSel::Toggle
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}
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#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
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#[inline(always)]
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pub fn is_pwma(&self) -> bool {
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*self == StatusSel::Pwma
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}
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#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
|
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#[inline(always)]
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pub fn is_pwmb(&self) -> bool {
|
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*self == StatusSel::Pwmb
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}
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#[doc = "Returns the counter ENABLED bit"]
|
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#[inline(always)]
|
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pub fn is_enabled(&self) -> bool {
|
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*self == StatusSel::Enabled
|
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}
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||||
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
|
||||
#[inline(always)]
|
||||
pub fn is_pwma_active(&self) -> bool {
|
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*self == StatusSel::PwmaActive
|
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}
|
||||
}
|
||||
#[doc = "Field `STATUS_SEL` writer - Counter Status Selection"]
|
||||
pub type StatusSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, StatusSel>;
|
||||
impl<'a, REG> StatusSelW<'a, REG>
|
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where
|
||||
REG: crate::Writable + crate::RegisterSpec,
|
||||
REG::Ux: From<u8>,
|
||||
{
|
||||
#[doc = "Single cycle pulse when the counter reaches 0"]
|
||||
#[inline(always)]
|
||||
pub fn done(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::Done)
|
||||
}
|
||||
#[doc = "Returns the counter ACTIVE bit"]
|
||||
#[inline(always)]
|
||||
pub fn active(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::Active)
|
||||
}
|
||||
#[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."]
|
||||
#[inline(always)]
|
||||
pub fn toggle(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::Toggle)
|
||||
}
|
||||
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
|
||||
#[inline(always)]
|
||||
pub fn pwma(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::Pwma)
|
||||
}
|
||||
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
|
||||
#[inline(always)]
|
||||
pub fn pwmb(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::Pwmb)
|
||||
}
|
||||
#[doc = "Returns the counter ENABLED bit"]
|
||||
#[inline(always)]
|
||||
pub fn enabled(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::Enabled)
|
||||
}
|
||||
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
|
||||
#[inline(always)]
|
||||
pub fn pwma_active(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(StatusSel::PwmaActive)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `STATUS_INV` reader - Invert the Output Status"]
|
||||
pub type StatusInvR = crate::BitReader;
|
||||
#[doc = "Field `STATUS_INV` writer - Invert the Output Status"]
|
||||
pub type StatusInvW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `REQ_STOP` reader - Stop Request"]
|
||||
pub type ReqStopR = crate::BitReader;
|
||||
#[doc = "Field `REQ_STOP` writer - Stop Request"]
|
||||
pub type ReqStopW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Counter Enable"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) -> EnableR {
|
||||
EnableR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Counter Active"]
|
||||
#[inline(always)]
|
||||
pub fn active(&self) -> ActiveR {
|
||||
ActiveR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
|
||||
#[inline(always)]
|
||||
pub fn auto_disable(&self) -> AutoDisableR {
|
||||
AutoDisableR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
|
||||
#[inline(always)]
|
||||
pub fn auto_deactivate(&self) -> AutoDeactivateR {
|
||||
AutoDeactivateR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - Interrupt Enable"]
|
||||
#[inline(always)]
|
||||
pub fn irq_enb(&self) -> IrqEnbR {
|
||||
IrqEnbR::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 5:7 - Counter Status Selection"]
|
||||
#[inline(always)]
|
||||
pub fn status_sel(&self) -> StatusSelR {
|
||||
StatusSelR::new(((self.bits >> 5) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bit 8 - Invert the Output Status"]
|
||||
#[inline(always)]
|
||||
pub fn status_inv(&self) -> StatusInvR {
|
||||
StatusInvR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - Stop Request"]
|
||||
#[inline(always)]
|
||||
pub fn req_stop(&self) -> ReqStopR {
|
||||
ReqStopR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Counter Enable"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn enable(&mut self) -> EnableW<CtrlSpec> {
|
||||
EnableW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn auto_disable(&mut self) -> AutoDisableW<CtrlSpec> {
|
||||
AutoDisableW::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn auto_deactivate(&mut self) -> AutoDeactivateW<CtrlSpec> {
|
||||
AutoDeactivateW::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - Interrupt Enable"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn irq_enb(&mut self) -> IrqEnbW<CtrlSpec> {
|
||||
IrqEnbW::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 5:7 - Counter Status Selection"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn status_sel(&mut self) -> StatusSelW<CtrlSpec> {
|
||||
StatusSelW::new(self, 5)
|
||||
}
|
||||
#[doc = "Bit 8 - Invert the Output Status"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn status_inv(&mut self) -> StatusInvW<CtrlSpec> {
|
||||
StatusInvW::new(self, 8)
|
||||
}
|
||||
#[doc = "Bit 9 - Stop Request"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn req_stop(&mut self) -> ReqStopW<CtrlSpec> {
|
||||
ReqStopW::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CtrlSpec;
|
||||
impl crate::RegisterSpec for CtrlSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
|
||||
impl crate::Readable for CtrlSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
|
||||
impl crate::Writable for CtrlSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CTRL to value 0"]
|
||||
impl crate::Resettable for CtrlSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
40
va416xx/src/tim0/enable.rs
Normal file
40
va416xx/src/tim0/enable.rs
Normal file
@ -0,0 +1,40 @@
|
||||
#[doc = "Register `ENABLE` reader"]
|
||||
pub type R = crate::R<EnableSpec>;
|
||||
#[doc = "Register `ENABLE` writer"]
|
||||
pub type W = crate::W<EnableSpec>;
|
||||
#[doc = "Field `ENABLE` reader - Counter Enable"]
|
||||
pub type EnableR = crate::BitReader;
|
||||
#[doc = "Field `ENABLE` writer - Counter Enable"]
|
||||
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Counter Enable"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) -> EnableR {
|
||||
EnableR::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Counter Enable"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn enable(&mut self) -> EnableW<EnableSpec> {
|
||||
EnableW::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct EnableSpec;
|
||||
impl crate::RegisterSpec for EnableSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`enable::R`](R) reader structure"]
|
||||
impl crate::Readable for EnableSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"]
|
||||
impl crate::Writable for EnableSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets ENABLE to value 0"]
|
||||
impl crate::Resettable for EnableSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
18
va416xx/src/tim0/perid.rs
Normal file
18
va416xx/src/tim0/perid.rs
Normal file
@ -0,0 +1,18 @@
|
||||
#[doc = "Register `PERID` reader"]
|
||||
pub type R = crate::R<PeridSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PeridSpec;
|
||||
impl crate::RegisterSpec for PeridSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
|
||||
impl crate::Readable for PeridSpec {}
|
||||
#[doc = "`reset()` method sets PERID to value 0x0211_07e9"]
|
||||
impl crate::Resettable for PeridSpec {
|
||||
const RESET_VALUE: u32 = 0x0211_07e9;
|
||||
}
|
||||
27
va416xx/src/tim0/pwm_value.rs
Normal file
27
va416xx/src/tim0/pwm_value.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `PWM_VALUE` reader"]
|
||||
pub type R = crate::R<PwmValueSpec>;
|
||||
#[doc = "Register `PWM_VALUE` writer"]
|
||||
pub type W = crate::W<PwmValueSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PwmValueSpec;
|
||||
impl crate::RegisterSpec for PwmValueSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`pwm_value::R`](R) reader structure"]
|
||||
impl crate::Readable for PwmValueSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`pwm_value::W`](W) writer structure"]
|
||||
impl crate::Writable for PwmValueSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets PWM_VALUE to value 0"]
|
||||
impl crate::Resettable for PwmValueSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va416xx/src/tim0/pwma_value.rs
Normal file
27
va416xx/src/tim0/pwma_value.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `PWMA_VALUE` reader"]
|
||||
pub type R = crate::R<PwmaValueSpec>;
|
||||
#[doc = "Register `PWMA_VALUE` writer"]
|
||||
pub type W = crate::W<PwmaValueSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PwmaValueSpec;
|
||||
impl crate::RegisterSpec for PwmaValueSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`pwma_value::R`](R) reader structure"]
|
||||
impl crate::Readable for PwmaValueSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`pwma_value::W`](W) writer structure"]
|
||||
impl crate::Writable for PwmaValueSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets PWMA_VALUE to value 0"]
|
||||
impl crate::Resettable for PwmaValueSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va416xx/src/tim0/pwmb_value.rs
Normal file
27
va416xx/src/tim0/pwmb_value.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `PWMB_VALUE` reader"]
|
||||
pub type R = crate::R<PwmbValueSpec>;
|
||||
#[doc = "Register `PWMB_VALUE` writer"]
|
||||
pub type W = crate::W<PwmbValueSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PwmbValueSpec;
|
||||
impl crate::RegisterSpec for PwmbValueSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`pwmb_value::R`](R) reader structure"]
|
||||
impl crate::Readable for PwmbValueSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`pwmb_value::W`](W) writer structure"]
|
||||
impl crate::Writable for PwmbValueSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets PWMB_VALUE to value 0"]
|
||||
impl crate::Resettable for PwmbValueSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
27
va416xx/src/tim0/rst_value.rs
Normal file
27
va416xx/src/tim0/rst_value.rs
Normal file
@ -0,0 +1,27 @@
|
||||
#[doc = "Register `RST_VALUE` reader"]
|
||||
pub type R = crate::R<RstValueSpec>;
|
||||
#[doc = "Register `RST_VALUE` writer"]
|
||||
pub type W = crate::W<RstValueSpec>;
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct RstValueSpec;
|
||||
impl crate::RegisterSpec for RstValueSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`rst_value::R`](R) reader structure"]
|
||||
impl crate::Readable for RstValueSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`rst_value::W`](W) writer structure"]
|
||||
impl crate::Writable for RstValueSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets RST_VALUE to value 0"]
|
||||
impl crate::Resettable for RstValueSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Reference in New Issue
Block a user