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add all submodules as regular code

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Robin Müller 2024-06-11 13:48:42 +02:00
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.gitmodules vendored
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[submodule "va416xx-hal"]
path = va416xx-hal
url = https://egit.irs.uni-stuttgart.de/rust/va416xx-hal.git
[submodule "vorago-peb1"]
path = vorago-peb1
url = https://egit.irs.uni-stuttgart.de/rust/vorago-peb1.git

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Subproject commit f9b5f99604daa79102e8efefa645989829bfcd51

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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb
# runner = "arm-none-eabi-gdb -q -x jlink.gdb"
# runner = "gdb-multiarch -q -x jlink.gdb"
# runner = "gdb -q -x openocd.gdb"
# runner = "gdb-multiarch -q -x jlink.gdb"
rustflags = [
# This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
# See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
"-C", "link-arg=--nmagic",
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
# target = "thumbv8m.base-none-eabi" # Cortex-M23
# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU)
# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb
# runner = "arm-none-eabi-gdb -q -x jlink/jlink.gdb"
# runner = "gdb-multiarch -q -x jlink/jlink.gdb"
# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb"
# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb"
rustflags = [
# This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
# See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
"-C", "link-arg=--nmagic",
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
# target = "thumbv8m.base-none-eabi" # Cortex-M23
# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU)
# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

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/target
Cargo.lock

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{
// Use IntelliSense to learn about possible attributes.
// Hover to view descriptions of existing attributes.
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0",
"configurations": [
{
"type": "cortex-debug",
"request": "launch",
"name": "Debug LED Blinky",
// The user should start the J-Link server themselves for now. This is because the
// Cortex-Debug will issue a reset command, which is problematic even with
// a valid JLinkScript file
"servertype": "external",
"gdbTarget": "localhost:2331",
"gdbPath": "/usr/bin/gdb-multiarch",
"cwd": "${workspaceRoot}",
"device": "Cortex-M4",
"svdFile": "../va416xx/svd/va416xx-base.svd",
"preLaunchTask": "rust: cargo build led blinky",
"executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/blinky",
"interface": "swd",
"runToMain": true,
},
]
}

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{
// See https://go.microsoft.com/fwlink/?LinkId=733558
// for the documentation about the tasks.json format
"version": "2.0.0",
"tasks": [
{
"label": "rust: cargo build led blinky",
"type": "shell",
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
"args": [
"build", "--example", "blinky"
],
"group": {
"kind": "build",
"isDefault": true
}
},
]
}

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[package]
name = "va416xx-hal"
version = "0.1.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA416xx family of MCUs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-hal"
repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-hal"
license = "Apache-2.0"
keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-m = "0.7"
cortex-m-rt = "0.7.1"
nb = "1"
[dependencies.va416xx]
path = "../va416xx"
version = "0.1.0"
[features]
rt = ["va416xx/rt"]
[dev-dependencies]
panic-rtt-target = { version = "0.1", features = ["cortex-m"] }
rtt-target = { version = "0.3", features = ["cortex-m"] }
panic-halt = "0.2"
[profile.dev]
debug = true
lto = false
[profile.release]
lto = true
debug = true

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Rust Hardware Abstraction Layer (HAL) crate for the Vorago VA416xx family of MCUs
This software contains code developed at the University of Stuttgart.

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# HAL for the Vorago VA416xx MCU family
This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional
hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx).
It is the result of reading the datasheet for the device and encoding a type-safe layer over the
raw PAC. This crate also implements traits specified by the
[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
various drivers in the embedded rust ecosystem.
## Supported Boards
The first way to use this HAL will probably be with the
[PEB1 development board](https://www.voragotech.com/products/peb1va416x0-development-kit).
The BSP provided for this board also contains instructions how to flash the board.
## Building
Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain.
If you have not installed it yet, you can do so with
```sh
rustup target add thumbv7em-none-eabihf
```
After that, you can use `cargo build` to build the development version of the crate.
If you have not done this yet, it is recommended to read some of the excellent resources
available to learn Rust:
- [Rust Embedded Book](https://docs.rust-embedded.org/book/)
- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/)
## Using the `.cargo/config.toml` file
Use the following command to have a starting `config.toml` file
```sh
cp .cargo/def-config.toml .cargo/config.toml
```
You then can adapt the `config.toml` to your needs. For example, you can configure runners
to conveniently flash with `cargo run`.
## Setting up your own binary crate
TODO

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//! Simple blinky example
#![no_main]
#![no_std]
use cortex_m_rt::{entry};
use panic_halt as _;
use va416xx_hal::pac;
// Mask for the LED
const LED_PG5: u32 = 1 << 5;
#[entry]
fn main() -> ! {
let dp = pac::Peripherals::take().unwrap();
// Enable all peripheral clocks
dp.SYSCONFIG
.peripheral_clk_enable
.modify(|_, w| unsafe { w.bits(0xffffffff) });
dp.PORTG.dir().modify(|_, w| unsafe { w.bits(LED_PG5) });
dp.PORTG.datamask().modify(|_, w| unsafe { w.bits(LED_PG5)});
for _ in 0..10 {
dp.PORTG
.clrout()
.write(|w| unsafe { w.bits(LED_PG5) });
cortex_m::asm::delay(5_000_000);
dp.PORTG
.setout()
.write(|w| unsafe { w.bits(LED_PG5) });
cortex_m::asm::delay(5_000_000);
}
loop {
dp.PORTG
.togout()
.write(|w| unsafe { w.bits(LED_PG5) });
cortex_m::asm::delay(25_000_000);
}
}

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//! Code to test RTT logger functionality
#![no_main]
#![no_std]
use cortex_m_rt::entry;
use panic_halt as _;
use rtt_target::{rprintln, rtt_init_print};
use va416xx as _;
#[entry]
fn main() -> ! {
rtt_init_print!();
rprintln!("-- RTT Demo --");
let mut counter = 0;
loop {
rprintln!("{}: Hello, world!", counter);
counter += 1;
cortex_m::asm::delay(75_000_000);
}
}

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#!/bin/bash
# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary
# to disable ROM protection to allow flashing
JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \
-LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript

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/*********************************************************************
* SEGGER Microcontroller GmbH *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 1995 - 2018 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
----------------------------------------------------------------------
File : JLinkSettings.JLinkScript
Purpose : J-Link target setup file for VORAGO VA416xx
---------------------------END-OF-HEADER------------------------------
*/
int DisableRomProt(void) {
JLINK_SYS_Report("VA416XX: Disabling ROM protection");
return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1
}
int DisableWatchdog(void) {
JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551
JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable)
}
int SetupTarget (void) {
JLINK_SYS_Report("SetupTarget()");
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* AfterResetTarget
*/
int AfterResetTarget (void) {
JLINK_SYS_Report("AfterResetTarget()");
// disable watchdog and unlock code RAM for write
DisableWatchdog();
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* BeforeTargetDownload
*/
int BeforeTargetDownload (void) {
JLINK_SYS_Report("BeforeTargetDownload()");
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* AfterTargetDownload
*/
int AfterTargetDownload (void) {
JLINK_SYS_Report("AfterTargetDownload()");
return DisableRomProt(); // ROM_PROT = 0x0
}
/*********************************************************************
*
* HandleBeforeFlashProg
*/
int HandleBeforeFlashProg(void) {
JLINK_SYS_Report("HandleBeforeFlashProg()");
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* HandleAfterFlashProg
*/
int HandleAfterFlashProg(void) {
JLINK_SYS_Report("HandleAfterFlashProg()");
return DisableRomProt(); // ROM_PROT = 0x0
}

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target remote localhost:2331
# For some reason, this is problematic even if the JLinkScript disabled the remote
# write protection. Therefore, don't do it for now
# This is only problematic on board RevA
# monitor reset
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
load
continue

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target remote localhost:2331
# Reset is problematic on RevA, okay for RevB
monitor reset
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
load
continue

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MEMORY
{
FLASH : ORIGIN = 0x00000000, LENGTH = 256K
/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
}
/* This is where the call stack will be allocated. */
/* The stack is of the full descending type. */
/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
/* SRAM_0 can be used for all busses: Instruction, Data and System */
/* SRAM_1 only supports the system bus */
_stack_start = ORIGIN(RAM) + LENGTH(RAM) - 4;

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//! # API for clock related functionality
//!
//! This also includes functionality to enable the peripheral clocks
use va416xx::SYSCONFIG;
#[derive(Copy, Clone, PartialEq)]
pub enum PeripheralSelect {
Spi0 = 0,
Spi1 = 1,
Spi2 = 2,
Spi3 = 3,
Uart0 = 4,
Uart1 = 5,
Uart2 = 6,
I2c0 = 7,
I2c1 = 8,
I2c2 = 9,
Can0 = 10,
Can1 = 11,
Rng = 12,
Adc = 13,
Dac = 14,
Dma = 15,
Ebi = 16,
Eth = 17,
Spw = 18,
Clkgen = 19,
IrqRouter = 20,
IoConfig = 21,
Utility = 22,
Watchdog = 23,
PortA = 24,
PortB = 25,
PortC = 26,
PortD = 27,
PortE = 28,
PortF = 29,
PortG = 30
}
pub fn enable_peripheral_clock(syscfg: &mut SYSCONFIG, clock: PeripheralSelect) {
syscfg
.peripheral_clk_enable
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
}
pub fn disable_peripheral_clock(syscfg: &mut SYSCONFIG, clock: PeripheralSelect) {
syscfg
.peripheral_clk_enable
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
}

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#![no_std]
pub use va416xx;
pub use va416xx as pac;
pub mod clock;
pub mod time;

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//! Time units
//!
//! See [`Hertz`], [`KiloHertz`] and [`MegaHertz`] for creating increasingly higher frequencies.
//!
//! The [`U32Ext`] trait adds various methods like `.hz()`, `.mhz()`, etc to the `u32` primitive type,
//! allowing it to be converted into frequencies.
/// Bits per second
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct Bps(pub u32);
/// Hertz
///
/// Create a frequency specified in [Hertz](https://en.wikipedia.org/wiki/Hertz).
///
/// See also [`KiloHertz`] and [`MegaHertz`] for semantically correct ways of creating higher
/// frequencies.
///
/// # Examples
///
/// ## Create an 60 Hz frequency
///
/// ```rust
/// use stm32f1xx_hal::time::Hertz;
///
/// let freq = 60.hz();
/// ```
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct Hertz(pub u32);
/// Kilohertz
///
/// Create a frequency specified in kilohertz.
///
/// See also [`Hertz`] and [`MegaHertz`] for semantically correct ways of creating lower or higher
/// frequencies.
///
/// # Examples
///
/// ## Create a 100 Khz frequency
///
/// This example creates a 100 KHz frequency. This could be used to set an I2C data rate or PWM
/// frequency, etc.
///
/// ```rust
/// use stm32f1xx_hal::time::Hertz;
///
/// let freq = 100.khz();
/// ```
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct KiloHertz(pub u32);
/// Megahertz
///
/// Create a frequency specified in megahertz.
///
/// See also [`Hertz`] and [`KiloHertz`] for semantically correct ways of creating lower
/// frequencies.
///
/// # Examples
///
/// ## Create a an 8 MHz frequency
///
/// This example creates an 8 MHz frequency that could be used to configure an SPI peripheral, etc.
///
/// ```rust
/// use stm32f1xx_hal::time::Hertz;
///
/// let freq = 8.mhz();
/// ```
#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
pub struct MegaHertz(pub u32);
/// Time unit
#[derive(PartialEq, PartialOrd, Clone, Copy)]
pub struct MilliSeconds(pub u32);
#[derive(PartialEq, PartialOrd, Clone, Copy)]
pub struct MicroSeconds(pub u32);
/// Extension trait that adds convenience methods to the `u32` type
pub trait U32Ext {
/// Wrap in `Bps`
fn bps(self) -> Bps;
/// Wrap in `Hertz`
fn hz(self) -> Hertz;
/// Wrap in `KiloHertz`
fn khz(self) -> KiloHertz;
/// Wrap in `MegaHertz`
fn mhz(self) -> MegaHertz;
/// Wrap in `MilliSeconds`
fn ms(self) -> MilliSeconds;
/// Wrap in `MicroSeconds`
fn us(self) -> MicroSeconds;
}
impl U32Ext for u32 {
fn bps(self) -> Bps {
Bps(self)
}
fn hz(self) -> Hertz {
Hertz(self)
}
fn khz(self) -> KiloHertz {
KiloHertz(self)
}
fn mhz(self) -> MegaHertz {
MegaHertz(self)
}
fn ms(self) -> MilliSeconds {
MilliSeconds(self)
}
fn us(self) -> MicroSeconds {
MicroSeconds(self)
}
}
impl From<KiloHertz> for Hertz {
fn from(val: KiloHertz) -> Self {
Self(val.0 * 1_000)
}
}
impl From<MegaHertz> for Hertz {
fn from(val: MegaHertz) -> Self {
Self(val.0 * 1_000_000)
}
}
impl From<MegaHertz> for KiloHertz {
fn from(val: MegaHertz) -> Self {
Self(val.0 * 1_000)
}
}
impl From<MilliSeconds> for Hertz {
fn from(val: MilliSeconds) -> Self {
Self(1_000 / val.0)
}
}
impl From<MicroSeconds> for Hertz {
fn from(val: MicroSeconds) -> Self {
Self(1_000_000 / val.0)
}
}

1
vorago-peb1

@ -1 +0,0 @@
Subproject commit da0cd6180f2d27abc90981ebadbdde6704dccd45

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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb
# runner = "arm-none-eabi-gdb -q -x jlink/jlink.gdb"
# runner = "gdb-multiarch -q -x jlink/jlink.gdb"
# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb"
# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb"
rustflags = [
# This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
# See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
"-C", "link-arg=--nmagic",
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
# target = "thumbv8m.base-none-eabi" # Cortex-M23
# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU)
# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

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/target
Cargo.lock
/.cargo/config.toml

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[package]
name = "vorago-peb1"
version = "0.1.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "Board Support Crate for the Vorago PEB1 development board"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1"
license = "Apache-2.0"
keywords = ["no-std", "peb1", "cortex-m", "vorago", "va416xx"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-m = "0.7"
cortex-m-rt = "0.7.1"
embedded-hal = { version = "0.2.6", features = ["unproven"] }
[dependencies.va416xx-hal]
path = "../va416xx-hal"
version = "0.1.0"
[features]
rt = ["va416xx-hal/rt"]
[dev-dependencies]
panic-rtt-target = { version = "0.1", features = ["cortex-m"] }
rtt-target = { version = "0.3", features = ["cortex-m"] }
panic-halt = "0.2"
[profile.dev]
debug = true
lto = false
[profile.release]
lto = true
debug = true

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3
vorago-peb1/NOTICE Normal file
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Rust Board Support Package (BSP) crate for the Vorago PEB1 development board
This software contains code developed at the University of Stuttgart.

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vorago-peb1/README.md Normal file
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# Rust BSP for the Vorago PEB1 development board
## Using the `.cargo/config.toml` file
Use the following command to have a starting `config.toml` file
```sh
cp .cargo/def-config.toml .cargo/config.toml
```
You then can adapt the `config.toml` to your needs. For example, you can configure runners
to conveniently flash with `cargo run`.
## Notes on board revisions
On RevA, issuing the `monitor reset` command in the GDB application is problematic and will prevent
the flashed binary from working properly. On board revision B, this was not an issue.
For that reason, two different `*.gdb` files were provided in the `jlink` folder for each
board revision. If you are not using these files, make sure to correctly configure your flash
tools depending on which tool or board your are using.

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vorago-peb1/examples/blinky.rs Normal file
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//! Simple blinky example
#![no_main]
#![no_std]
use cortex_m_rt::entry;
use panic_halt as _;
use va416xx_hal::{
pac,
gpio::PinsG
};
use embedded_hal::digital::v2::{ToggleableOutputPin, OutputPin};
// Mask for the LED
const LED_PG5: u32 = 1 << 5;
#[allow(dead_code)]
enum LibType {
Pac,
Hal,
Bsp,
}
#[entry]
fn main() -> ! {
let mut dp = pac::Peripherals::take().unwrap();
let lib_type = LibType::Hal;
match lib_type {
LibType::Pac => {
// Enable all peripheral clocks
dp.SYSCONFIG
.peripheral_clk_enable
.modify(|_, w| w.portg().set_bit());
dp.PORTG.dir().modify(|_, w| unsafe { w.bits(LED_PG5) });
dp.PORTG
.datamask()
.modify(|_, w| unsafe { w.bits(LED_PG5) });
for _ in 0..10 {
dp.PORTG.clrout().write(|w| unsafe { w.bits(LED_PG5) });
cortex_m::asm::delay(5_000_000);
dp.PORTG.setout().write(|w| unsafe { w.bits(LED_PG5) });
cortex_m::asm::delay(5_000_000);
}
loop {
dp.PORTG.togout().write(|w| unsafe { w.bits(LED_PG5) });
cortex_m::asm::delay(25_000_000);
}
}
LibType::Hal => {
let portg = PinsG::new(&mut dp.SYSCONFIG, Some(dp.IOCONFIG), dp.PORTG);
// Enable all peripheral clocks
let mut led = portg.pg5.into_push_pull_output();
for _ in 0..10 {
led.set_low().ok();
cortex_m::asm::delay(5_000_000);
led.set_high().ok();
};
loop {
led.toggle().ok();
cortex_m::asm::delay(25_000_000);
}
}
LibType::Bsp => loop {},
}
}

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#!/bin/bash
# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary
# to disable ROM protection to allow flashing
JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \
-LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript

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/*********************************************************************
* SEGGER Microcontroller GmbH *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 1995 - 2018 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
----------------------------------------------------------------------
File : JLinkSettings.JLinkScript
Purpose : J-Link target setup file for VORAGO VA416xx
---------------------------END-OF-HEADER------------------------------
*/
int DisableRomProt(void) {
JLINK_SYS_Report("VA416XX: Disabling ROM protection");
return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1
}
int DisableWatchdog(void) {
JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551
JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable)
}
int SetupTarget (void) {
JLINK_SYS_Report("SetupTarget()");
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* AfterResetTarget
*/
int AfterResetTarget (void) {
JLINK_SYS_Report("AfterResetTarget()");
// disable watchdog and unlock code RAM for write
DisableWatchdog();
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* BeforeTargetDownload
*/
int BeforeTargetDownload (void) {
JLINK_SYS_Report("BeforeTargetDownload()");
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* AfterTargetDownload
*/
int AfterTargetDownload (void) {
JLINK_SYS_Report("AfterTargetDownload()");
return DisableRomProt(); // ROM_PROT = 0x0
}
/*********************************************************************
*
* HandleBeforeFlashProg
*/
int HandleBeforeFlashProg(void) {
JLINK_SYS_Report("HandleBeforeFlashProg()");
return DisableRomProt(); // ROM_PROT = 0x1
}
/*********************************************************************
*
* HandleAfterFlashProg
*/
int HandleAfterFlashProg(void) {
JLINK_SYS_Report("HandleAfterFlashProg()");
return DisableRomProt(); // ROM_PROT = 0x0
}

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target remote localhost:2331
# For some reason, this is problematic even if the JLinkScript disabled the remote
# write protection. Therefore, don't do it for now
# This is only problematic on board RevA
# monitor reset
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
load
continue

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target remote localhost:2331
# Reset is problematic on RevA, okay for RevB
monitor reset
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
load
continue

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MEMORY
{
FLASH : ORIGIN = 0x00000000, LENGTH = 256K
/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
}
/* This is where the call stack will be allocated. */
/* The stack is of the full descending type. */
/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
/* SRAM_0 can be used for all busses: Instruction, Data and System */
/* SRAM_1 only supports the system bus */
_stack_start = ORIGIN(RAM) + LENGTH(RAM);

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#![no_std]