continue CAN support
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@ -25,6 +25,7 @@ typenum = "1"
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bitflags = "2"
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bitbybit = "1.3"
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arbitrary-int = "1.3"
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derive-mmio = "0.4"
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fugit = "0.3"
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delegate = ">=0.12, <=0.13"
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heapless = "0.8"
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@ -1 +0,0 @@
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67
va416xx-hal/src/can/mod.rs
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67
va416xx-hal/src/can/mod.rs
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@ -0,0 +1,67 @@
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use arbitrary_int::{u2, u3, u4, u7};
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use crate::{clock::Clocks, enable_peripheral_clock, PeripheralSelect};
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pub mod regs;
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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pub enum CanId {
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Can0 = 0,
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Can1 = 1,
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}
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impl CanId {}
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pub struct Can {
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id: CanId,
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}
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pub trait Instance {
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const ID: CanId;
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const PERIPH_SEL: PeripheralSelect;
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}
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impl Instance for va416xx::Can0 {
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const ID: CanId = CanId::Can0;
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Can0;
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}
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impl Instance for va416xx::Can1 {
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const ID: CanId = CanId::Can1;
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Can1;
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}
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pub struct ClockConfig {
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prescaler: u7,
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tseg1: u4,
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tseg2: u3,
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sjw: u2,
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}
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impl ClockConfig {
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/// New clock configuration from the raw configuration values.
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pub fn new(prescaler: u7, tseg1: u4, tseg2: u3, sjw: u2) -> Self {
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Self {
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prescaler,
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tseg1,
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tseg2,
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sjw,
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}
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}
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}
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impl Can {
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pub fn new<CanI: Instance>(_can: CanI, clk_config: ClockConfig) -> Self {
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enable_peripheral_clock(CanI::PERIPH_SEL);
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let id = CanI::ID;
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let mut regs = if id == CanId::Can0 {
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unsafe { regs::Can::new_mmio_fixed_0() }
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} else {
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unsafe { regs::Can::new_mmio_fixed_1() }
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};
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for i in 0..15 {
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regs.msg_buf_block_mut(i).reset();
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}
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Self { id }
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}
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}
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298
va416xx-hal/src/can/regs.rs
Normal file
298
va416xx-hal/src/can/regs.rs
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@ -0,0 +1,298 @@
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//! Custom register definitions for the CAN register block to circumvent PAC API / SVD
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//! shortcomings.
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use arbitrary_int::{u2, u3, u4, u7};
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pub const CAN_0_BASE: usize = 0x4001_4000;
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pub const CAN_1_BASE: usize = 0x4001_4400;
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#[derive(Debug)]
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#[bitbybit::bitenum(u4)]
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pub enum BufferStatus {
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RxNotActive = 0b0000,
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RxReady = 0b0001,
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RxBusy0 = 0b0010,
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RxFull = 0b0100,
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RxBusy1 = 0b0101,
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RxOverrun = 0b0110,
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RxBusy2 = 0b0111,
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TxNotActive = 0b1000,
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TxRtr = 0b1010,
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TxOnce = 0b1100,
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TxBusy0 = 0b1101,
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TxOnceRtr = 0b1110,
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TxBusy2 = 0b1111,
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}
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/// Status control register for individual message buffers.
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#[bitbybit::bitfield(u32)]
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pub struct BufStatusAndControl {
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/// Data length code.
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#[bits(12..=15, rw)]
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dlc: u4,
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#[bits(4..=7, rw)]
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priority: u4,
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#[bits(0..=3, rw)]
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status: Option<BufferStatus>,
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}
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#[derive(Debug)]
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pub struct Data16Bit(arbitrary_int::UInt<u32, 16>);
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impl Data16Bit {
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pub fn new(value: u16) -> Self {
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Self(value.into())
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}
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pub fn value(&self) -> u16 {
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self.0.value() as u16
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}
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pub fn write(&mut self, value: u16) {
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self.0 = value.into();
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}
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct CanMsgBuf {
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stat_ctrl: BufStatusAndControl,
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timestamp: Data16Bit,
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data3: Data16Bit,
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data2: Data16Bit,
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data1: Data16Bit,
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data0: Data16Bit,
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id0: Data16Bit,
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id1: Data16Bit,
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}
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impl MmioCanMsgBuf<'_> {
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pub fn reset(&mut self) {
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self.write_stat_ctrl(BufStatusAndControl::new_with_raw_value(0));
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self.write_timestamp(Data16Bit::new(0));
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self.write_data3(Data16Bit::new(0));
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self.write_data2(Data16Bit::new(0));
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self.write_data1(Data16Bit::new(0));
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self.write_data0(Data16Bit::new(0));
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self.write_id1(Data16Bit::new(0));
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self.write_id0(Data16Bit::new(0));
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}
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug)]
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pub enum PinLogicLevel {
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DominantIsZero = 0b0,
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DominantIsOne = 0b1,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug)]
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pub enum ErrorInterruptType {
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/// EIPND bit is set on every error.
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EveryError = 0b0,
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/// EIPND bit is only set if error state changes as a result of a receive or transmit
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/// error counter increment.
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ErrorOnRxTxCounterChange = 0b1,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug)]
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pub enum DataDirection {
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FirstByteAtHighestAddr = 0b0,
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LastByteAtHighestAddr = 0b1,
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}
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#[bitbybit::bitfield(u32)]
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pub struct Control {
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#[bit(11, rw)]
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error_interrupt_type: ErrorInterruptType,
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/// Enables special diagnostics features of the CAN like LO, IGNACK, LOOPBACK, INTERNAL.
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#[bit(10, rw)]
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diag_enable: bool,
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/// CANTX and CANRX pins are internally connected to each other.
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#[bit(9, rw)]
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internal: bool,
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/// All messages sent by the CAN controller can also be received by a CAN buffer with a
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/// matching buffer ID.
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#[bit(8, rw)]
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loopback: bool,
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/// IGNACK feature. The CAN does not expect to receive an ACK bit.
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#[bit(7, rw)]
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ignore_ack: bool,
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/// LO feature. The CAN is only configured as a receiver.
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#[bit(6, rw)]
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listen_only: bool,
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#[bit(5, rw)]
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data_dir: DataDirection,
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#[bit(4, rw)]
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timestamp_enable: bool,
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#[bit(3, rw)]
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bufflock: bool,
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#[bit(2, rw)]
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tx_logic_level: PinLogicLevel,
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#[bit(1, rw)]
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rx_logic_level: PinLogicLevel,
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#[bit(0, rw)]
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enable: bool,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct TimingConfig {
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#[bits(0..=2, rw)]
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tseg2: u3,
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#[bits(3..=6, rw)]
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tseg1: u4,
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#[bits(7..=8, rw)]
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sync_jump_width: u2,
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#[bits(9..=15, rw)]
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prescaler: u7,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptEnable {
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#[bit(15, rw)]
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error: bool,
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#[bit(0, rw)]
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buffer: [bool; 15],
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptClear {
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#[bit(15, w)]
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error: bool,
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#[bit(0, w)]
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buffer: [bool; 15],
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptPending {
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#[bit(15, r)]
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error: bool,
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#[bit(0, r)]
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buffer: [bool; 15],
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct ErrorCounter {
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#[bits(0..=7, r)]
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transmit: u8,
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#[bits(8..=15, r)]
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receive: u8,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct Can {
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#[mmio(inner)]
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cmb0: CanMsgBuf,
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#[mmio(inner)]
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cmb1: CanMsgBuf,
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#[mmio(inner)]
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cmb2: CanMsgBuf,
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#[mmio(inner)]
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cmb3: CanMsgBuf,
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#[mmio(inner)]
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cmb4: CanMsgBuf,
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#[mmio(inner)]
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cmb5: CanMsgBuf,
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#[mmio(inner)]
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cmb6: CanMsgBuf,
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#[mmio(inner)]
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cmb7: CanMsgBuf,
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#[mmio(inner)]
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cmb8: CanMsgBuf,
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#[mmio(inner)]
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cmb9: CanMsgBuf,
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#[mmio(inner)]
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cmb10: CanMsgBuf,
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#[mmio(inner)]
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cmb11: CanMsgBuf,
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#[mmio(inner)]
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cmb12: CanMsgBuf,
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#[mmio(inner)]
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cmb13: CanMsgBuf,
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#[mmio(inner)]
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cmb14: CanMsgBuf,
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#[mmio(inner)]
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hcmb: CanMsgBuf,
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control: Control,
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timing: TimingConfig,
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/// Global mask extension.
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gmskx: u32,
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/// Global mask base.
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gmskb: u32,
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/// Basic mask extension.
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bmskx: u32,
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/// Basic mask base.
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bmskb: u32,
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ien: InterruptEnable,
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#[mmio(PureRead)]
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ipnd: InterruptPending,
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#[mmio(Write)]
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iclr: InterruptClear,
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/// Interrupt Code Enable Register.
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icen: InterruptEnable,
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#[mmio(PureRead)]
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status_pending: u32,
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#[mmio(PureRead)]
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error_counter: ErrorCounter,
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#[mmio(PureRead)]
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diag: u32,
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#[mmio(PureRead)]
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timer: u32,
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}
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impl Can {
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/// Create a new CAN MMIO instance for peripheral 0.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed_0() -> MmioCan<'static> {
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Self::new_mmio_at(CAN_0_BASE)
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}
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/// Create a new CAN MMIO instance for peripheral 1.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed_1() -> MmioCan<'static> {
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Self::new_mmio_at(CAN_1_BASE)
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}
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}
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impl MmioCan<'_> {
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// TODO: It would be nice if derive-mmio could generate this for us..
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pub fn msg_buf_block_mut(&mut self, idx: usize) -> MmioCanMsgBuf<'static> {
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assert!(idx < 16, "invalid index for CAN message buffer");
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match idx {
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0 => unsafe { self.steal_cmb0() },
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1 => unsafe { self.steal_cmb1() },
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2 => unsafe { self.steal_cmb2() },
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3 => unsafe { self.steal_cmb3() },
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4 => unsafe { self.steal_cmb4() },
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5 => unsafe { self.steal_cmb5() },
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6 => unsafe { self.steal_cmb6() },
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7 => unsafe { self.steal_cmb7() },
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8 => unsafe { self.steal_cmb8() },
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9 => unsafe { self.steal_cmb9() },
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10 => unsafe { self.steal_cmb10() },
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11 => unsafe { self.steal_cmb11() },
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12 => unsafe { self.steal_cmb12() },
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13 => unsafe { self.steal_cmb13() },
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14 => unsafe { self.steal_cmb14() },
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15 => unsafe { self.steal_hcmb() },
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_ => unreachable!(),
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}
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}
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}
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@ -396,16 +396,45 @@ impl Clocks {
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}
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/// Returns the frequency of the APB0 which is equal to the system clock.
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///
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/// This clock is the reference clock for the following peripherals:
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///
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/// - Ethernet
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/// - SpaceWire
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/// - IRQ Router
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/// - DMA
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/// - Clock Generator
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pub const fn apb0(&self) -> Hertz {
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self.sysclk()
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}
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/// Returns system clock divied by 2.
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///
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/// This clock is the reference clock for the following peripherals:
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///
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/// - Timer[15:0]
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/// - UART2
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/// - SPI
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/// - I2C
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/// - CAN
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/// - GPIO
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/// - IOCONFIG
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/// - System Config
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pub const fn apb1(&self) -> Hertz {
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self.apb1
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}
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/// Returns system clock divied by 4.
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///
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/// This clock is the reference clock for the following peripherals:
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///
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/// - Timer[23:16]
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/// - TRNG
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/// - UART[1:0]
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/// - DAC
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/// - ADC
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/// - Watchdog
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/// - Utility
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pub const fn apb2(&self) -> Hertz {
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self.apb2
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}
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@ -3,7 +3,9 @@
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//! ## Examples
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//!
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//! - [PEB1 accelerometer example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs)
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use crate::{clock::Clocks, pac, time::Hertz, typelevel::Sealed, PeripheralSelect, SyscfgExt as _};
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use crate::{
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clock::Clocks, enable_peripheral_clock, pac, time::Hertz, typelevel::Sealed, PeripheralSelect,
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};
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use core::{marker::PhantomData, ops::Deref};
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use embedded_hal::i2c::{self, Operation, SevenBitAddress, TenBitAddress};
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@ -318,13 +320,12 @@ impl<I2C> I2cBase<I2C> {
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impl<I2c: Instance> I2cBase<I2c> {
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pub fn new(
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i2c: I2c,
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syscfg: &mut pac::Sysconfig,
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clocks: &Clocks,
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speed_mode: I2cSpeed,
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ms_cfg: Option<&MasterConfig>,
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sl_cfg: Option<&SlaveConfig>,
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) -> Result<Self, ClockTooSlowForFastI2cError> {
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syscfg.enable_peripheral_clock(I2c::PERIPH_SEL);
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enable_peripheral_clock(I2c::PERIPH_SEL);
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let mut i2c_base = I2cBase {
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i2c,
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@ -476,13 +477,12 @@ pub struct I2cMaster<I2c, Addr = SevenBitAddress> {
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impl<I2c: Instance, Addr> I2cMaster<I2c, Addr> {
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pub fn new(
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i2c: I2c,
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sys_cfg: &mut pac::Sysconfig,
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cfg: MasterConfig,
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clocks: &Clocks,
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speed_mode: I2cSpeed,
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) -> Result<Self, ClockTooSlowForFastI2cError> {
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Ok(I2cMaster {
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i2c_base: I2cBase::new(i2c, sys_cfg, clocks, speed_mode, Some(&cfg), None)?,
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i2c_base: I2cBase::new(i2c, clocks, speed_mode, Some(&cfg), None)?,
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addr: PhantomData,
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}
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.enable_master())
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@ -737,13 +737,12 @@ pub struct I2cSlave<I2c, Addr = SevenBitAddress> {
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impl<I2c: Instance, Addr> I2cSlave<I2c, Addr> {
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fn new_generic(
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i2c: I2c,
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sys_cfg: &mut pac::Sysconfig,
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cfg: SlaveConfig,
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clocks: &Clocks,
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speed_mode: I2cSpeed,
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) -> Result<Self, ClockTooSlowForFastI2cError> {
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Ok(I2cSlave {
|
||||
i2c_base: I2cBase::new(i2c, sys_cfg, clocks, speed_mode, None, Some(&cfg))?,
|
||||
i2c_base: I2cBase::new(i2c, clocks, speed_mode, None, Some(&cfg))?,
|
||||
addr: PhantomData,
|
||||
}
|
||||
.enable_slave())
|
||||
@ -884,7 +883,6 @@ impl<I2c: Instance> I2cSlave<I2c, SevenBitAddress> {
|
||||
/// Create a new I2C slave for seven bit addresses
|
||||
pub fn new(
|
||||
i2c: I2c,
|
||||
sys_cfg: &mut pac::Sysconfig,
|
||||
cfg: SlaveConfig,
|
||||
clocks: &Clocks,
|
||||
speed_mode: I2cSpeed,
|
||||
@ -892,18 +890,17 @@ impl<I2c: Instance> I2cSlave<I2c, SevenBitAddress> {
|
||||
if let I2cAddress::TenBit(_) = cfg.addr {
|
||||
return Err(InitError::WrongAddrMode);
|
||||
}
|
||||
Ok(Self::new_generic(i2c, sys_cfg, cfg, clocks, speed_mode)?)
|
||||
Ok(Self::new_generic(i2c, cfg, clocks, speed_mode)?)
|
||||
}
|
||||
}
|
||||
|
||||
impl<I2c: Instance> I2cSlave<I2c, TenBitAddress> {
|
||||
pub fn new_ten_bit_addr(
|
||||
i2c: I2c,
|
||||
sys_cfg: &mut pac::Sysconfig,
|
||||
cfg: SlaveConfig,
|
||||
clocks: &Clocks,
|
||||
speed_mode: I2cSpeed,
|
||||
) -> Result<Self, ClockTooSlowForFastI2cError> {
|
||||
Self::new_generic(i2c, sys_cfg, cfg, clocks, speed_mode)
|
||||
Self::new_generic(i2c, cfg, clocks, speed_mode)
|
||||
}
|
||||
}
|
||||
|
||||
@ -97,39 +97,43 @@ pub enum PeripheralSelect {
|
||||
pub type PeripheralClock = PeripheralSelect;
|
||||
|
||||
#[inline(always)]
|
||||
pub fn enable_peripheral_clock(syscfg: &mut pac::Sysconfig, clock: PeripheralSelect) {
|
||||
syscfg
|
||||
pub fn enable_peripheral_clock(clock: PeripheralSelect) {
|
||||
// Safety: Only bit of peripheral is modified.
|
||||
unsafe { pac::Sysconfig::steal() }
|
||||
.peripheral_clk_enable()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn disable_peripheral_clock(syscfg: &mut pac::Sysconfig, clock: PeripheralSelect) {
|
||||
syscfg
|
||||
pub fn disable_peripheral_clock(clock: PeripheralSelect) {
|
||||
// Safety: Only bit of peripheral is modified.
|
||||
unsafe { pac::Sysconfig::steal() }
|
||||
.peripheral_clk_enable()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn assert_periph_reset(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) {
|
||||
syscfg
|
||||
pub fn assert_periph_reset(periph: PeripheralSelect) {
|
||||
// Safety: Only reset bit of peripheral is modified.
|
||||
unsafe { pac::Sysconfig::steal() }
|
||||
.peripheral_reset()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph as u8)) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn deassert_periph_reset(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) {
|
||||
syscfg
|
||||
pub fn deassert_periph_reset(periph: PeripheralSelect) {
|
||||
// Safety: Only rest bit of peripheral is modified.
|
||||
unsafe { pac::Sysconfig::steal() }
|
||||
.peripheral_reset()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph as u8)) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn assert_periph_reset_for_two_cycles(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) {
|
||||
assert_periph_reset(syscfg, periph);
|
||||
fn assert_periph_reset_for_two_cycles(periph: PeripheralSelect) {
|
||||
assert_periph_reset(periph);
|
||||
cortex_m::asm::nop();
|
||||
cortex_m::asm::nop();
|
||||
deassert_periph_reset(syscfg, periph);
|
||||
deassert_periph_reset(periph);
|
||||
}
|
||||
|
||||
#[derive(Debug, Eq, Copy, Clone, PartialEq)]
|
||||
@ -190,27 +194,27 @@ pub trait SyscfgExt {
|
||||
impl SyscfgExt for pac::Sysconfig {
|
||||
#[inline(always)]
|
||||
fn enable_peripheral_clock(&mut self, clock: PeripheralClock) {
|
||||
enable_peripheral_clock(self, clock)
|
||||
enable_peripheral_clock(clock)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn disable_peripheral_clock(&mut self, clock: PeripheralClock) {
|
||||
disable_peripheral_clock(self, clock)
|
||||
disable_peripheral_clock(clock)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn assert_periph_reset(&mut self, clock: PeripheralSelect) {
|
||||
assert_periph_reset(self, clock)
|
||||
assert_periph_reset(clock)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn deassert_periph_reset(&mut self, clock: PeripheralSelect) {
|
||||
deassert_periph_reset(self, clock)
|
||||
deassert_periph_reset(clock)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn assert_periph_reset_for_two_cycles(&mut self, periph: PeripheralSelect) {
|
||||
assert_periph_reset_for_two_cycles(self, periph)
|
||||
assert_periph_reset_for_two_cycles(periph)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -21,7 +21,7 @@ use crate::{
|
||||
pac,
|
||||
time::Hertz,
|
||||
typelevel::{NoneT, Sealed},
|
||||
PeripheralSelect, SyscfgExt as _,
|
||||
PeripheralSelect,
|
||||
};
|
||||
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
@ -1041,15 +1041,14 @@ where
|
||||
/// to be done once.
|
||||
/// * `syscfg` - Can be passed optionally to enable the peripheral clock
|
||||
pub fn new(
|
||||
syscfg: &mut pac::Sysconfig,
|
||||
clocks: &crate::clock::Clocks,
|
||||
spi: SpiI,
|
||||
pins: (Sck, Miso, Mosi),
|
||||
spi_cfg: SpiConfig,
|
||||
) -> Self {
|
||||
crate::enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
|
||||
crate::enable_peripheral_clock(SpiI::PERIPH_SEL);
|
||||
// This is done in the C HAL.
|
||||
syscfg.assert_periph_reset_for_two_cycles(SpiI::PERIPH_SEL);
|
||||
crate::assert_periph_reset_for_two_cycles(SpiI::PERIPH_SEL);
|
||||
let SpiConfig {
|
||||
clk,
|
||||
init_mode,
|
||||
|
||||
@ -18,7 +18,7 @@ use fugit::RateExtU32;
|
||||
use crate::clock::Clocks;
|
||||
use crate::gpio::PF13;
|
||||
use crate::time::Hertz;
|
||||
use crate::{disable_nvic_interrupt, enable_nvic_interrupt, PeripheralSelect, SyscfgExt as _};
|
||||
use crate::{disable_nvic_interrupt, enable_nvic_interrupt, PeripheralSelect};
|
||||
use crate::{
|
||||
gpio::{
|
||||
AltFunc1, AltFunc2, AltFunc3, Pin, PA2, PA3, PB14, PB15, PC14, PC4, PC5, PD11, PD12, PE2,
|
||||
@ -630,15 +630,14 @@ impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstanc
|
||||
Uart<UartInstance, (TxPinInst, RxPinInst)>
|
||||
{
|
||||
pub fn new(
|
||||
syscfg: &mut va416xx::Sysconfig,
|
||||
uart: UartInstance,
|
||||
pins: (TxPinInst, RxPinInst),
|
||||
config: impl Into<Config>,
|
||||
clocks: &Clocks,
|
||||
) -> Self {
|
||||
crate::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL);
|
||||
crate::enable_peripheral_clock(UartInstance::PERIPH_SEL);
|
||||
// This is done in the C HAL.
|
||||
syscfg.assert_periph_reset_for_two_cycles(UartInstance::PERIPH_SEL);
|
||||
crate::assert_periph_reset_for_two_cycles(UartInstance::PERIPH_SEL);
|
||||
Uart {
|
||||
inner: UartBase {
|
||||
uart,
|
||||
@ -651,13 +650,12 @@ impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstanc
|
||||
}
|
||||
|
||||
pub fn new_with_clock_freq(
|
||||
syscfg: &mut va416xx::Sysconfig,
|
||||
uart: UartInstance,
|
||||
pins: (TxPinInst, RxPinInst),
|
||||
config: impl Into<Config>,
|
||||
clock: impl Into<Hertz>,
|
||||
) -> Self {
|
||||
crate::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL);
|
||||
crate::enable_peripheral_clock(UartInstance::PERIPH_SEL);
|
||||
Uart {
|
||||
inner: UartBase {
|
||||
uart,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user