init commit

.cargo/def-config.toml

@@ -0,0 +1,38 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "gdb-multiarch -q -x jlink/jlink.gdb"
+# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb"
+# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb"
+
+# Probe-rs is currently problematic, possibly because of the
+# ROM protection?
+# runner = "probe-rs run --chip-description-path ./scripts/VA416xx_Series.yaml"
+# runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format", "{L} {s}"]
+
+
+rustflags = [
+  "-C",
+  "link-arg=-Tlink.x",
+  # "-C",
+  # "linker=flip-link",
+  # "-C",
+  # "link-arg=-Tdefmt.x",
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  "-C",
+  "link-arg=--nmagic",
+]
+
+[build]
+# (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right
+# target improves performance)
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+
+[alias]
+rb = "run --bin"
+rrb = "run --release --bin"
+
+[env]
+DEFMT_LOG = "info"

.gitignore

@@ -0,0 +1,16 @@
+# Generated by Cargo
+# will have compiled files and executables
+/target/
+/.vscode
+
+# Ignore user config
+/.cargo/config.toml
+
+# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries
+# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html
+Cargo.lock
+
+# These are backup files generated by rustfmt
+**/*.rs.bk
+
+/app.map

Cargo.toml

@@ -0,0 +1,17 @@
+[workspace]
+resolver = "2"
+members = [
+	"va416xx",
+	"va416xx-hal",
+	"vorago-peb1"
+]
+
+[profile.dev]
+lto = false
+debug = true
+
+[profile.release]
+# Can be problematic for debugging
+lto = true
+debug = true
+opt-level = 's'

LICENSE-APACHE

@@ -0,0 +1,201 @@
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+limitations under the License.

NOTICE

@@ -0,0 +1,3 @@
+Workspace to develop Rust for the VA416xx devices
+
+This software contains code developed at the University of Stuttgart.

README.md

@@ -0,0 +1,83 @@
+Vorago VA416xx Rust Support
+=========
+
+This crate collection provided support to write Rust applications for the VA416XX family
+of devices.
+
+## List of crates
+
+This workspace contains the following crates:
+
+- The `va416xx` PAC crate containing basic low-level register definition
+- The `va416xx-hal` HAL crate containing higher-level abstractions on top of
+  the PAC register crate.
+- The `vorago-peb1` BSP crate containing support for the PEB1 development
+  board.
+
+## Using the `.cargo/config.toml` file
+
+Use the following command to have a starting `config.toml` file
+
+```sh
+cp .cargo/def-config.toml .cargo/config.toml
+```
+
+You then can adapt the `config.toml` to your needs. For example, you can configure runners
+to conveniently flash with `cargo run`.
+
+## Using the sample VS Code files
+
+Use the following command to have a starting configuration for VS Code:
+
+```sh
+cp vscode .vscode -r
+```
+
+You can then adapt the files in `.vscode` to your needs.
+
+## Flashing, running and debugging with the command line
+
+### Prerequisites
+
+1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed
+2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar
+   cross-architecture debugger installed. All commands here assume `gdb-multiarch`.
+
+### Flashing and debugging the blinky application
+
+You can build the blinky example application with the following command
+
+```sh
+cargo build -p va416xx-hal --example blinky
+```
+
+Start the GDB server first. The server needs to be started with a certain configuration and with
+a JLink script to disable ROM protection.
+For example, on Debian based system the following command can be used to do this (this command
+is also run when running the `jlink-gdb.sh` script)
+
+```sh
+JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \
+  -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript
+```
+
+After this, you can flash and debug the application with the following command
+
+```sh
+gdb-mutliarch -q -x jlink/jlink.gdb target/thumbv7em-none-eabihf/debug/examples/blinky
+```
+
+Please note that you can automate all steps except starting the GDB server by using a cargo
+runner configuration, for example with the following lines in your `.cargo/config.toml` file:
+
+```toml
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "gdb-multiarch -q -x jlink/jlink.gdb"
+```
+
+After that, you can simply use `cargo run -p va416xx-hal --example blinky` to flash the blinky
+example.
+
+## Flashing, running and debugging with VS Code
+
+TODO

jlink-gdb.sh

@@ -0,0 +1,5 @@
+#!/bin/bash
+# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary
+# to disable ROM protection to allow flashing
+JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \
+  -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript

jlink/JLinkSettings.JLinkScript

@@ -0,0 +1,60 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*       Solutions for real time microcontroller applications         *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+----------------------------------------------------------------------
+File    : JLinkSettings.JLinkScript
+Purpose : J-Link target setup file for VORAGO VA416xx
+---------------------------END-OF-HEADER------------------------------
+*/
+
+/*********************************************************************
+*
+*       AfterResetTarget
+*/
+int AfterResetTarget (void) {
+  JLINK_SYS_Report("AfterResetTarget()");
+  return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*/
+int BeforeTargetDownload (void) {
+  JLINK_SYS_Report("BeforeTargetDownload()");
+  return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       AfterTargetDownload
+*/
+int AfterTargetDownload (void) {
+  JLINK_SYS_Report("AfterTargetDownload()");
+  return JLINK_MEM_WriteU32(0x40010010, 0x0); // ROM_PROT = 0x0
+}
+
+/*********************************************************************
+*
+*       HandleBeforeFlashProg
+*/
+int HandleBeforeFlashProg(void) {
+  JLINK_SYS_Report("HandleBeforeFlashProg()");
+  return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       HandleAfterFlashProg
+*/
+int HandleAfterFlashProg(void) {
+  JLINK_SYS_Report("HandleAfterFlashProg()");
+  return JLINK_MEM_WriteU32(0x40010010, 0x0); // ROM_PROT = 0x0
+}

jlink/jlink-reva.gdb

@@ -0,0 +1,13 @@
+target remote localhost:2331
+
+# For some reason, this is problematic even if the JLinkScript disabled the remote
+# write protection. Therefore, don't do it for now
+# This is only problematic on board RevA
+# monitor reset
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+load
+
+continue

jlink/jlink.gdb

@@ -0,0 +1,11 @@
+target remote localhost:2331
+
+# Reset is problematic on RevA, okay for RevB
+monitor reset
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+load
+
+continue

memory.x

@@ -0,0 +1,14 @@
+MEMORY
+{
+	FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+	/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
+	RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
+	SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
+/* SRAM_0 can be used for all busses: Instruction, Data and System */
+/* SRAM_1 only supports the system bus */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);

scripts/VA416xx_Series.yaml

@@ -0,0 +1,99 @@
+name: VA416xx Series
+generated_from_pack: true
+pack_file_release: 1.0.5
+variants:
+- name: VA416xx
+  cores:
+  - name: main
+    type: armv7em
+    core_access_options: !Arm
+      ap: 0
+      psel: 0x0
+  memory_map:
+  - !Ram
+    name: IRAM1
+    range:
+      start: 0x1fff8000
+      end: 0x20000000
+    cores:
+    - main
+  - !Nvm
+    name: IROM1
+    range:
+      start: 0x0
+      end: 0x40000
+    is_boot_memory: true
+    cores:
+    - main
+  - !Generic
+    name: IRAM2
+    range:
+      start: 0x20000000
+      end: 0x20008000
+    cores:
+    - main
+  flash_algorithms:
+  - va416_spi_fram_256kb
+  # - va416_ebiboot_fram_256kb
+  # - va416_ebi_fram_512kb
+flash_algorithms:
+- name: va416_spi_fram_256kb
+  description: VA416_SPI_FRAM_256KB
+  instructions: RfYMQMTyAQABaMkHCtEBaMkHBL8BaF/qwXED0QFoyQfy0AC/AWjJBgnVAWjJBkS/AWhf6sFhAtUBaMkG8tQDIQFicEdwRwC/WCAIIcTyAQDA8qgBQWBB8ggBTvJRUsTyAgHB9swiwfi4IAAiCmABaCHwCAEBYAC/AL8CaEX2DEFC8AgCxPIBAQJgAiAAv0hgQPIHQEH4DAxA8oIgQfgIDAMgCGIIaMAHCtEIaMAHBL8IaF/qwHAD0QhowAfy0AC/CGjABgnVCGjABkS/CGhf6sBgAtUIaMAG8tQGIMjyAAADIgpiQfgEDApo0gcK0Qpo0gcEvwpoX+rCcgPRCmjSB/LQAL8KaNIGCdUKaNIGRL8KaF/qwmIC1Qpo0gby1AMiCmJB+AQMCGjABwnRCGjABwS/CGhf6sBwAtEIaMAH8tAIaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AMgCGIBIEH4BAxP8ABAQfgEDAhowAcK0QhowAcEvwhoX+rAcAPRCGjAB/LQAL8IaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AMiACAKYnBHAL9F9gxBxPIBAQhowAcK0QhowAcEvwhoX+rAcAPRCGjAB/LQAL8IaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AYgyPIAAAMiCmJB+AQMCmjSBwrRCmjSBwS/Cmhf6sJyA9EKaNIH8tAAvwpo0gYJ1Qpo0gZEvwpoX+rCYgLVCmjSBvLUAyIKYgEi9zBB+AQsQfgEDAhowAcJ0QhowAcEvwhoX+rAcALRCGjAB/LQCGjABgnVCGjABkS/CGhf6sBgAtUIaMAG8tQDIgAgCmJwRwC/cLVF9gxBQPIGDAAgxPIBAcjyAAwDI0/wAg5P8ABCACQG4AC/ATS09YBvC2IA8KyAQfgEzA1o7QcK0Q1o7QcEvw1oX+rFdQPRDWjtB/LQAL8NaO0GCtUNaO0GRL8NaF/qxWUD1Q1o7Qby1AC/xPMHJQtiQfgE7EH4BFzlskH4BFwAJUH4BFwE4AU1/y1B+AQMTNAOaLYHBtQOaLYHXL8OaF/qhnY+1UH4BAwOaLYHCdQOaLYHXL8OaF/qhnYC1A5otgfy1UH4BAwOaLYHCtQOaLYHXL8OaF/qhnYD1A5otgfy1QC/QfgEDA5otgcK1A5otgdcvw5oX+qGdgPUDmi2B/LVAL9B+AQMDmi2B7zUDmi2B1y/Dmhf6oZ2tdQOaLYH8tWx5w5otgez1bznDWitBwrUDWitB1y/DWhf6oV1A9QNaK0H8tUAv0H4BCwNaO0HCtENaO0HBL8NaF/qxXUD0Q1o7Qfy0AC/DWjtBn/1Wq8NaO0GRL8NaF/qxWV/9VKvDWjtBvDUTecAIHC9ACBwR4C1grBF9gxOxPIBDgAjAZPe+AAw2wcN0d74ADDbBwS/3vgAMF/qw3ME0d74ADDbB+7QAL/e+AAw2wYM1d74ADDbBkS/3vgAMF/qw2MD1d74ADDbBu7UAyPO+CAwBiPI8gADTvgEPN74ADDbBwzR3vgAMNsHBL/e+AAwX+rDcwPR3vgAMNsH7tDe+AAw2wYM1d74ADDbBkS/3vgAMF/qw2MD1d74ADDbBu7UAyPO+CAwAiNN9vAMTvgEPMDzB0PP9v98TvgEPMDzByPAsgEpTvgEPE74BAxA8JKA3vgAAIAHAPEGgd74AACAB1y/3vgAAF/qgHAA8fyA3vgAAIAHXL/e+AAAX+qAcADx8oDe+AAAgAdcv974AABf6oBwAPHogN74AACAB1y/3vgAAF/qgHAA8d6A3vgAAIAHXL/e+AAAX+qAcADx1IDe+AAAgAdcv974AABf6oBwAPHKgN74AACAB1y/3vgAAF/qgHAA8cCA3vgAAIAHXL/e+AAAX+qAcADxtoDe+AAAgAdcv974AABf6oBwAPGsgN74AACAB1y/3vgAAF/qgHAA8aKA3vgAAIAHXL/e+AAAX+qAcADxmIDe+AAAgAdcv974AABf6oBwAPGOgBzxGQx/9H+vheAAvxL4AQsBOU74BAxe+AQMASkAkAGYAPEBAAGQP/Rur2BG3vgAMJsH69Te+AAwmwdcv974ADBf6oNz4tTe+AAwmwdcv974ADBf6oNz2dTe+AAwmwdcv974ADBf6oNz0NTe+AAwmwdcv974ADBf6oNzx9Te+AAwmwdcv974ADBf6oNzvtTe+AAwmwdcv974ADBf6oNztdTe+AAwmwdcv974ADBf6oNzrNTe+AAwmwdcv974ADBf6oNzo9Te+AAwmwdcv974ADBf6oNzmtTe+AAwmwdcv974ADBf6oNzkdTe+AAwmwdcv974ADBf6oNzP/WIr974ADCbB1y/3vgAMF/qg3M/9X6vGTB/9IuvASACsIC9EHgA8QBATvgEDN74AADABwzR3vgAAMAHBL/e+AAAX+rAcAPR3vgAAMAH7tDe+AAAwAYM1d74AADABkS/3vgAAF/qwGAD1d74AADABu7UAyDO+CAAACACsIC9AL8AIHBHsLVF9gxExPIBBCNo2wcJ0SNo2wcEvyNoX+rDcwLRI2jbB/LQI2jbBgnVI2jbBkS/I2hf6sNjAtUjaNsG8tQDIyNiRPgEPMDzB0NE+AQ8wPMHI0T4BDzDskT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwBs0/wAAxP8AAOAL9E+ATMI2hbBwrUI2hbB1y/I2hf6kNzA9QjaFsH8tUAv1T4BDwVeNuynUIo0Q7xAQ6ORQLxAQLj0U/wAEJE+AQsImjSBwrRImjSBwS/Imhf6sJyA9EiaNIH8tAAvyJo0gYJ1SJo0gZEvyJoX+rCYgLVImjSBvLUAyIIRCJisL1wRLC9AAAAAAAA
+  pc_init: 0x49
+  pc_uninit: 0x1ad
+  pc_program_page: 0x40d
+  pc_erase_sector: 0x409
+  pc_erase_all: 0x27d
+  data_section_offset: 0x8d8
+  flash_properties:
+    address_range:
+      start: 0x0
+      end: 0x40000
+    page_size: 0x100
+    erased_byte_value: 0x0
+    program_page_timeout: 3000
+    erase_sector_timeout: 3000
+    sectors:
+    - size: 0x2000
+      address: 0x0
+- name: va416_ebiboot_fram_256kb
+  description: VA416_EBIBOOT_256KB
+  instructions: QfKAAsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HywALE8gECUvggMCP0wEND6kExQvggEHBHAL9B8gASxPIBAlL4IDAj9MBDQ+pBMUL4IBBwRwC/QfJAEsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HyiADE8gEAAmgBIWHzTjICYEJoYfNOMkJggmhh804ygmDCaGHzTjLCYAJpYfNOMgJhQmlh804yQmGCaWHzTjKCYcJpYfNOMsJhAmph804yAmJCamHzTjJCYoJqYfNOMoJiwmph804ywmICa2HzTjICY0JrYfNOMkJjgmth804ygmPCa2HzTjLCYwJsYfNOMgJkQmxh804yQmSCbGHzTjKCZMJsYfNOMsJkAm1h804yAmVCbWHzTjJCZYJtYfNOMoJlwm1h804ywmUCbmHzTjICZkJuYfNOMkJmgm5h804ygmbCbmHzTjLCZgJvYfNOMgJnQm9h804yQmeCb2HzTjKCZ8JvYfNOMsJn0PiAIGHzTjLA+IAg0PiEIGHzTjLA+IQg0PiIIGHzTjLA+Igg0PiMIGHzTjLA+Iwg0PiQIGHzTjLA+JAg0PiUIGHzTjLA+JQg0PiYIGHzTjLA+Jgg0PicIGHzTjLA+Jwg0PioIGHzTjLA+Kgg0PisIGHzTjLA+Kwg0PiwIGHzTjLA+LAg0Pi0IGHzTjLA+LQg0Pi4IGHzTjLA+Lgg0Pi8IGHzTjLA+LwgcEcQtVgkACDE8gEEw/Y5QGBgIGhA9IAwIGD/9xj/T/YAccDytjEAIGFhEL0AvwAgcEeAtU/wwEBP9IAhAPA7+AAggL0AvwAgcEcB8AEDGURLCCnQWR4A8cBAAykD8AMME9Mj8AMDMvgIGwQ7IPgIGzL4Bhwg+AYcMvgEHCD4BBwy+AIcIPgCHO3RvPEADwvQEYi88QEPAYAG0FGIvPECD0GAHL+RiIGAACBwRwC/ACBwRwhEcEdP8AACALUTRpRGlkYgOSK/oOgMUKDoDFCx8SABv/T3rwkHKL+g6AxQSL8MwF34BOuJACi/QPgEKwi/cEdIvyD4AisR8IBPGL8A+AErcEcAAAAAAAA=
+  pc_init: 0x225
+  pc_uninit: 0x251
+  pc_program_page: 0x26d
+  pc_erase_sector: 0x269
+  pc_erase_all: 0x255
+  data_section_offset: 0x328
+  flash_properties:
+    address_range:
+      start: 0x0
+      end: 0x40000
+    page_size: 0x100
+    erased_byte_value: 0x0
+    program_page_timeout: 3000
+    erase_sector_timeout: 3000
+    sectors:
+    - size: 0x2000
+      address: 0x0
+- name: va416_ebi_fram_512kb
+  description: VA416_EBI_512KB
+  instructions: QfKAAsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HywALE8gECUvggMCP0wEND6kExQvggEHBHAL9B8gASxPIBAlL4IDAj9MBDQ+pBMUL4IBBwRwC/QfJAEsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HyiADE8gEAAmgBIWHzTjICYEJoYfNOMkJggmhh804ygmDCaGHzTjLCYAJpYfNOMgJhQmlh804yQmGCaWHzTjKCYcJpYfNOMsJhAmph804yAmJCamHzTjJCYoJqYfNOMoJiwmph804ywmICa2HzTjICY0JrYfNOMkJjgmth804ygmPCa2HzTjLCYwJsYfNOMgJkQmxh804yQmSCbGHzTjKCZMJsYfNOMsJkAm1h804yAmVCbWHzTjJCZYJtYfNOMoJlwm1h804ywmUCbmHzTjICZkJuYfNOMkJmgm5h804ygmbCbmHzTjLCZgJvYfNOMgJnQm9h804yQmeCb2HzTjKCZ8JvYfNOMsJn0PiAIGHzTjLA+IAg0PiEIGHzTjLA+IQg0PiIIGHzTjLA+Igg0PiMIGHzTjLA+Iwg0PiQIGHzTjLA+JAg0PiUIGHzTjLA+JQg0PiYIGHzTjLA+Jgg0PicIGHzTjLA+Jwg0PioIGHzTjLA+Kgg0PisIGHzTjLA+Kwg0PiwIGHzTjLA+LAg0Pi0IGHzTjLA+LQg0Pi4IGHzTjLA+Lgg0Pi8IGHzTjLA+LwgcEcQtVgkxPIBBCBoQPSAMCBgACDD9jlAYGD/9xj/T/YAcMDytjBgYU7yhBDO8gAAT/QAUQFgRvIAAb/zT4/E8gABGCC/82+PiGAwIgAgCmAQvQAgcEeAtU/wgFBP9AAhAPB4+AAggL0AvwAgcEcB8AEDGURLCCfQWR4DKQPwAwwT0yPwAwMy+AgbBDsg+AgbMvgGHCD4Bhwy+AQcIPgEHDL4Ahwg+AIc7dG88QAPC9ARiLzxAQ8BgAbQUYi88QIPQYAcv5GIgYAAIHBHAL8AIHBHLenwRQHwAQMZRF/qUQwr0OJGvPEBD5i/T/ABCsrxAA6q8QEIACMw+BNQMvgTYLVCItGYRRjQAutDBQDrQwZ3iGyIp0IT0Q7rAwe8HAzQtIipiIxCDdH5HAbQ8YjsiKFCCdEEM5pF3tFgRL3o8IUBMwLgAjMA4AMzT+pDDGBEvejwhU/wAAIAtRNGlEaWRiA5Ir+g6AxQoOgMULHxIAG/9PevCQcov6DoDFBIvwzAXfgE64kAKL9A+AQrCL9wR0i/IPgCKxHwgE8YvwD4AStwRwAAAAA=
+  pc_init: 0x225
+  pc_uninit: 0x275
+  pc_program_page: 0x291
+  pc_erase_sector: 0x28d
+  pc_erase_all: 0x279
+  data_section_offset: 0x3c4
+  flash_properties:
+    address_range:
+      start: 0x10000000
+      end: 0x10080000
+    page_size: 0x100
+    erased_byte_value: 0x0
+    program_page_timeout: 3000
+    erase_sector_timeout: 3000
+    sectors:
+    - size: 0x2000
+      address: 0x0

scripts/prep-flash.gdb

@@ -0,0 +1,8 @@
+target remote localhost:2331
+
+echo Disabling watchdog\n
+set *0x400210C0 = 0x1ACCE551
+set *0x40021008 = 0x0
+
+echo Disabling Instruction Memory protection\n
+set *0x40010010 = 0x1

scripts/prep-flash.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+# Alternative way to unlock the ROM protection of the VA416XX to allow flashing
+gdb-multiarch -q --batch -ex 'source prep-flash.gdb'

va416xx-hal/.cargo/config.toml

@@ -0,0 +1,38 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb
+# runner = "arm-none-eabi-gdb -q -x jlink.gdb"
+# runner = "gdb-multiarch -q -x jlink.gdb"
+# runner = "gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x jlink.gdb"
+
+rustflags = [
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  "-C", "link-arg=--nmagic",
+
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"        # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"        # Cortex-M3
+# target = "thumbv7em-none-eabi"       # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf"     # Cortex-M4F and Cortex-M7F (with FPU)
+# target = "thumbv8m.base-none-eabi"   # Cortex-M23
+# target = "thumbv8m.main-none-eabi"   # Cortex-M33 (no FPU)
+# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

va416xx-hal/.cargo/def-config.toml

@@ -0,0 +1,39 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb
+# runner = "arm-none-eabi-gdb -q -x jlink/jlink.gdb"
+# runner = "gdb-multiarch -q -x jlink/jlink.gdb"
+
+# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb"
+# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb"
+
+rustflags = [
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  "-C", "link-arg=--nmagic",
+
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"        # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"        # Cortex-M3
+# target = "thumbv7em-none-eabi"       # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf"     # Cortex-M4F and Cortex-M7F (with FPU)
+# target = "thumbv8m.base-none-eabi"   # Cortex-M23
+# target = "thumbv8m.main-none-eabi"   # Cortex-M33 (no FPU)
+# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

va416xx-hal/.gitignore

@@ -0,0 +1,2 @@
+/target
+Cargo.lock

va416xx-hal/Cargo.toml

@@ -0,0 +1,32 @@
+[package]
+name = "va416xx-hal"
+version = "0.1.0"
+authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
+edition = "2021"
+description = "HAL for the Vorago VA416xx family of MCUs"
+homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-hal"
+repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-hal"
+license = "Apache-2.0"
+keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"]
+categories = ["embedded", "no-std", "hardware-support"]
+
+[dependencies]
+cortex-m = "0.7"
+cortex-m-rt = "0.7"
+nb = "1"
+paste = "1"
+embedded-hal = "1"
+typenum = "1.12.0"
+
+[dependencies.va416xx]
+path = "../va416xx"
+version = "0.1.0"
+
+[features]
+rt = ["va416xx/rt"]
+
+[dev-dependencies]
+panic-rtt-target = { version = "0.1.3" }
+rtt-target = { version = "0.5" }
+panic-halt = "0.2"
+cortex-m = { version = "0.7.6", features = ["critical-section-single-core"]}

va416xx-hal/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+
+   "You" (or "Your") shall mean an individual or Legal Entity
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+
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va416xx-hal/NOTICE

@@ -0,0 +1,3 @@
+Rust Hardware Abstraction Layer (HAL) crate for the Vorago VA416xx family of MCUs
+
+This software contains code developed at the University of Stuttgart.

va416xx-hal/README.md

@@ -0,0 +1,47 @@
+# HAL for the Vorago VA416xx MCU family
+
+This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional
+hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx).
+
+It is the result of reading the datasheet for the device and encoding a type-safe layer over the
+raw PAC. This crate also implements traits specified by the
+[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
+various drivers in the embedded rust ecosystem.
+
+## Supported Boards
+
+ The first way to use this HAL will probably be with the
+ [PEB1 development board](https://www.voragotech.com/products/peb1va416x0-development-kit).
+ The BSP provided for this board also contains instructions how to flash the board.
+
+## Building
+
+Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain.
+If you have not installed it yet, you can do so with
+
+```sh
+rustup target add thumbv7em-none-eabihf
+```
+
+After that, you can use `cargo build` to build the development version of the crate.
+
+If you have not done this yet, it is recommended to read some of the excellent resources
+available to learn Rust:
+
+- [Rust Embedded Book](https://docs.rust-embedded.org/book/)
+- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/)
+
+## Using the `.cargo/config.toml` file
+
+Use the following command to have a starting `config.toml` file
+
+```sh
+cp .cargo/def-config.toml .cargo/config.toml
+```
+
+You then can adapt the `config.toml` to your needs. For example, you can configure runners
+to conveniently flash with `cargo run`.
+
+## Setting up your own binary crate
+
+TODO

va416xx-hal/examples/blinky-pac.rs

@@ -0,0 +1,34 @@
+//! Simple blinky example
+#![no_main]
+#![no_std]
+
+use cortex_m_rt::entry;
+use panic_halt as _;
+use va416xx_hal::pac;
+
+// Mask for the LED
+const LED_PG5: u32 = 1 << 5;
+
+#[entry]
+fn main() -> ! {
+    // SAFETY: Peripherals are only stolen once here.
+    let dp = unsafe { pac::Peripherals::steal() };
+    // Enable all peripheral clocks
+    dp.sysconfig
+        .peripheral_clk_enable()
+        .modify(|_, w| unsafe { w.bits(0xffffffff) });
+    dp.portg.dir().modify(|_, w| unsafe { w.bits(LED_PG5) });
+    dp.portg
+        .datamask()
+        .modify(|_, w| unsafe { w.bits(LED_PG5) });
+    for _ in 0..10 {
+        dp.portg.clrout().write(|w| unsafe { w.bits(LED_PG5) });
+        cortex_m::asm::delay(2_000_000);
+        dp.portg.setout().write(|w| unsafe { w.bits(LED_PG5) });
+        cortex_m::asm::delay(2_000_000);
+    }
+    loop {
+        dp.portg.togout().write(|w| unsafe { w.bits(LED_PG5) });
+        cortex_m::asm::delay(2_000_000);
+    }
+}

va416xx-hal/examples/blinky.rs

@@ -0,0 +1,21 @@
+//! Simple blinky example using the HAL
+#![no_main]
+#![no_std]
+
+use cortex_m_rt::entry;
+use embedded_hal::digital::StatefulOutputPin;
+use panic_halt as _;
+use va416xx_hal::{gpio::PinsG, pac};
+
+#[entry]
+fn main() -> ! {
+    // SAFETY: Peripherals are only stolen once here.
+    let mut dp = unsafe { pac::Peripherals::steal() };
+    let portg = PinsG::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portg);
+    let mut led = portg.pg5.into_readable_push_pull_output();
+    //let mut delay = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
+    loop {
+        cortex_m::asm::delay(2_000_000);
+        led.toggle().ok();
+    }
+}

va416xx-hal/examples/rtt-log.rs

@@ -0,0 +1,38 @@
+//! Code to test RTT logger functionality.
+#![no_main]
+#![no_std]
+
+use cortex_m_rt::entry;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
+use va416xx as _;
+use va416xx_hal::pac;
+
+// Mask for the LED
+const LED_PG5: u32 = 1 << 5;
+
+#[entry]
+fn main() -> ! {
+    // SAFETY: Peripherals are only stolen once here.
+    let dp = unsafe { pac::Peripherals::steal() };
+    // Enable all peripheral clocks
+    dp.sysconfig
+        .peripheral_clk_enable()
+        .modify(|_, w| unsafe { w.bits(0xffffffff) });
+    dp.portg.dir().modify(|_, w| unsafe { w.bits(LED_PG5) });
+    dp.portg
+        .datamask()
+        .modify(|_, w| unsafe { w.bits(LED_PG5) });
+
+    rtt_init_print!();
+    rprintln!("-- RTT Demo --");
+    let mut counter = 0;
+    loop {
+        rprintln!("{}: Hello, world!", counter);
+        // Still toggle LED. If there are issues with the RTT log, the LED
+        // blinking ensures that the application is actually running.
+        dp.portg.togout().write(|w| unsafe { w.bits(LED_PG5) });
+        counter += 1;
+        cortex_m::asm::delay(10_000_000);
+    }
+}

va416xx-hal/jlink-gdb.sh

@@ -0,0 +1,5 @@
+#!/bin/bash
+# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary
+# to disable ROM protection to allow flashing
+JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \
+  -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript

va416xx-hal/jlink/JLinkSettings.JLinkScript

@@ -0,0 +1,77 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*       Solutions for real time microcontroller applications         *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+----------------------------------------------------------------------
+File    : JLinkSettings.JLinkScript
+Purpose : J-Link target setup file for VORAGO VA416xx
+---------------------------END-OF-HEADER------------------------------
+*/
+
+int DisableRomProt(void) {
+  JLINK_SYS_Report("VA416XX: Disabling ROM protection");
+  return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1
+}
+
+int DisableWatchdog(void) {
+  JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551
+  JLINK_MEM_WriteU32(0x40021008, 0x0);        // WDOGCONTROL = 0x0 (diable)
+}
+
+int SetupTarget (void) {
+  JLINK_SYS_Report("SetupTarget()");
+  return DisableRomProt(); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       AfterResetTarget
+*/
+int AfterResetTarget (void) {
+  JLINK_SYS_Report("AfterResetTarget()");
+  // disable watchdog and unlock code RAM for write
+  DisableWatchdog();
+  return DisableRomProt(); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*/
+int BeforeTargetDownload (void) {
+  JLINK_SYS_Report("BeforeTargetDownload()");
+  return DisableRomProt(); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       AfterTargetDownload
+*/
+int AfterTargetDownload (void) {
+  JLINK_SYS_Report("AfterTargetDownload()");
+  return DisableRomProt(); // ROM_PROT = 0x0
+}
+
+/*********************************************************************
+*
+*       HandleBeforeFlashProg
+*/
+int HandleBeforeFlashProg(void) {
+  JLINK_SYS_Report("HandleBeforeFlashProg()");
+  return DisableRomProt(); // ROM_PROT = 0x1
+}
+
+/*********************************************************************
+*
+*       HandleAfterFlashProg
+*/
+int HandleAfterFlashProg(void) {
+  JLINK_SYS_Report("HandleAfterFlashProg()");
+  return DisableRomProt(); // ROM_PROT = 0x0
+}

va416xx-hal/jlink/jlink-reva.gdb

@@ -0,0 +1,13 @@
+target remote localhost:2331
+
+# For some reason, this is problematic even if the JLinkScript disabled the remote
+# write protection. Therefore, don't do it for now
+# This is only problematic on board RevA
+# monitor reset
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+load
+
+continue

va416xx-hal/jlink/jlink.gdb

@@ -0,0 +1,11 @@
+target remote localhost:2331
+
+# Reset is problematic on RevA, okay for RevB
+monitor reset
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+load
+
+continue

va416xx-hal/memory.x

@@ -0,0 +1,14 @@
+MEMORY
+{
+	FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+	/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
+	RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
+	SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
+/* SRAM_0 can be used for all busses: Instruction, Data and System */
+/* SRAM_1 only supports the system bus */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM) - 4;

va416xx-hal/src/clock.rs

@@ -0,0 +1,63 @@
+//! This also includes functionality to enable the peripheral clocks
+use va416xx::Sysconfig;
+
+#[derive(Copy, Clone, PartialEq)]
+pub enum PeripheralSelect {
+    Spi0 = 0,
+    Spi1 = 1,
+    Spi2 = 2,
+    Spi3 = 3,
+    Uart0 = 4,
+    Uart1 = 5,
+    Uart2 = 6,
+    I2c0 = 7,
+    I2c1 = 8,
+    I2c2 = 9,
+    Can0 = 10,
+    Can1 = 11,
+    Rng = 12,
+    Adc = 13,
+    Dac = 14,
+    Dma = 15,
+    Ebi = 16,
+    Eth = 17,
+    Spw = 18,
+    Clkgen = 19,
+    IrqRouter = 20,
+    IoConfig = 21,
+    Utility = 22,
+    Watchdog = 23,
+    PortA = 24,
+    PortB = 25,
+    PortC = 26,
+    PortD = 27,
+    PortE = 28,
+    PortF = 29,
+    PortG = 30,
+}
+
+pub type PeripheralClocks = PeripheralSelect;
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterClkSel {
+    SysClk = 0,
+    Clk1 = 1,
+    Clk2 = 2,
+    Clk3 = 3,
+    Clk4 = 4,
+    Clk5 = 5,
+    Clk6 = 6,
+    Clk7 = 7,
+}
+
+pub fn enable_peripheral_clock(syscfg: &mut Sysconfig, clock: PeripheralSelect) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
+}
+
+pub fn disable_peripheral_clock(syscfg: &mut Sysconfig, clock: PeripheralSelect) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
+}

va416xx-hal/src/gpio/dynpin.rs

@@ -0,0 +1,453 @@
+use embedded_hal::digital::{ErrorKind, ErrorType, InputPin, OutputPin, StatefulOutputPin};
+
+use super::{
+    reg::RegisterInterface, FilterClkSel, FilterType, InterruptEdge, InterruptLevel, Pin, PinId,
+    PinMode, PinState,
+};
+
+//==================================================================================================
+//  DynPinMode configurations
+//==================================================================================================
+
+/// Value-level `enum` for disabled configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynDisabled {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for input configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynInput {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for output configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynOutput {
+    PushPull,
+    OpenDrain,
+    ReadablePushPull,
+    ReadableOpenDrain,
+}
+
+pub type DynAlternate = crate::FunSel;
+
+//==================================================================================================
+//  DynPinMode
+//==================================================================================================
+
+/// Value-level `enum` representing pin modes
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynPinMode {
+    Input(DynInput),
+    Output(DynOutput),
+    Alternate(DynAlternate),
+}
+
+/// Value-level variant of [`DynPinMode`] for floating input mode
+pub const DYN_FLOATING_INPUT: DynPinMode = DynPinMode::Input(DynInput::Floating);
+/// Value-level variant of [`DynPinMode`] for pull-down input mode
+pub const DYN_PULL_DOWN_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullDown);
+/// Value-level variant of [`DynPinMode`] for pull-up input mode
+pub const DYN_PULL_UP_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullUp);
+
+/// Value-level variant of [`DynPinMode`] for push-pull output mode
+pub const DYN_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::PushPull);
+/// Value-level variant of [`DynPinMode`] for open-drain output mode
+pub const DYN_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::OpenDrain);
+/// Value-level variant of [`DynPinMode`] for readable push-pull output mode
+pub const DYN_RD_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadablePushPull);
+/// Value-level variant of [`DynPinMode`] for readable opendrain output mode
+pub const DYN_RD_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadableOpenDrain);
+
+/// Value-level variant of [`DynPinMode`] for function select 1
+pub const DYN_ALT_FUNC_1: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel1);
+/// Value-level variant of [`DynPinMode`] for function select 2
+pub const DYN_ALT_FUNC_2: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel2);
+/// Value-level variant of [`DynPinMode`] for function select 3
+pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3);
+
+//==================================================================================================
+//  DynGroup & DynPinId
+//==================================================================================================
+
+/// Value-level `enum` for pin groups
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum DynGroup {
+    A,
+    B,
+    C,
+    D,
+    E,
+    F,
+    G,
+}
+
+/// Value-level `struct` representing pin IDs
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub struct DynPinId {
+    pub group: DynGroup,
+    pub num: u8,
+}
+
+//==============================================================================
+//  DynRegisters
+//==============================================================================
+
+/// Provide a safe register interface for [`DynPin`]s
+///
+/// This `struct` takes ownership of a [`DynPinId`] and provides an API to
+/// access the corresponding regsiters.
+struct DynRegisters {
+    id: DynPinId,
+}
+
+// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
+// guarantees that each pin is a singleton, so this implementation is safe.
+unsafe impl RegisterInterface for DynRegisters {
+    #[inline]
+    fn id(&self) -> DynPinId {
+        self.id
+    }
+}
+
+impl DynRegisters {
+    /// Create a new instance of [`DynRegisters`]
+    ///
+    /// # Safety
+    ///
+    /// Users must never create two simultaneous instances of this `struct` with
+    /// the same [`DynPinId`]
+    #[inline]
+    unsafe fn new(id: DynPinId) -> Self {
+        DynRegisters { id }
+    }
+}
+
+//==============================================================================
+//  Error
+//==============================================================================
+
+/// GPIO error type
+///
+/// [`DynPin`]s are not tracked and verified at compile-time, so run-time
+/// operations are fallible. This `enum` represents the corresponding errors.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct InvalidPinTypeError(pub(crate) ());
+
+impl embedded_hal::digital::Error for InvalidPinTypeError {
+    fn kind(&self) -> embedded_hal::digital::ErrorKind {
+        ErrorKind::Other
+    }
+}
+
+//==================================================================================================
+//  DynPin
+//==================================================================================================
+
+/// A value-level pin, parameterized by [`DynPinId`] and [`DynPinMode`]
+///
+/// This type acts as a type-erased version of [`Pin`]. Every pin is represented
+/// by the same type, and pins are tracked and distinguished at run-time.
+pub struct DynPin {
+    regs: DynRegisters,
+    mode: DynPinMode,
+}
+
+impl DynPin {
+    /// Create a new [`DynPin`]
+    ///
+    /// # Safety
+    ///
+    /// Each [`DynPin`] must be a singleton. For a given [`DynPinId`], there
+    /// must be at most one corresponding [`DynPin`] in existence at any given
+    /// time.  Violating this requirement is `unsafe`.
+    #[inline]
+    unsafe fn new(id: DynPinId, mode: DynPinMode) -> Self {
+        DynPin {
+            regs: DynRegisters::new(id),
+            mode,
+        }
+    }
+
+    /// Return a copy of the pin ID
+    #[inline]
+    pub fn id(&self) -> DynPinId {
+        self.regs.id
+    }
+
+    /// Return a copy of the pin mode
+    #[inline]
+    pub fn mode(&self) -> DynPinMode {
+        self.mode
+    }
+
+    /// Convert the pin to the requested [`DynPinMode`]
+    #[inline]
+    pub fn into_mode(&mut self, mode: DynPinMode) {
+        // Only modify registers if we are actually changing pin mode
+        if mode != self.mode {
+            self.regs.change_mode(mode);
+            self.mode = mode;
+        }
+    }
+
+    #[inline]
+    pub fn into_funsel_1(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_1);
+    }
+
+    #[inline]
+    pub fn into_funsel_2(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_2);
+    }
+
+    #[inline]
+    pub fn into_funsel_3(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_3);
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(&mut self) {
+        self.into_mode(DYN_FLOATING_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(&mut self) {
+        self.into_mode(DYN_PULL_DOWN_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(&mut self) {
+        self.into_mode(DYN_PULL_UP_INPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(&mut self) {
+        self.into_mode(DYN_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_open_drain_output(&mut self) {
+        self.into_mode(DYN_OPEN_DRAIN_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(&mut self) {
+        self.into_mode(DYN_RD_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_open_drain_output(&mut self) {
+        self.into_mode(DYN_RD_OPEN_DRAIN_OUTPUT);
+    }
+
+    common_reg_if_functions!();
+
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn delay(self, delay_1: bool, delay_2: bool) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.delay(delay_1, delay_2);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    pub fn pulse_mode(
+        self,
+        enable: bool,
+        default_state: PinState,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.pulse_mode(enable, default_state);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn filter_type(
+        self,
+        filter: FilterType,
+        clksel: FilterClkSel,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) => {
+                self.regs.filter_type(filter, clksel);
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+
+    pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.regs.interrupt_edge(edge_type);
+                self.irq_enb();
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+
+    pub fn interrupt_level(
+        mut self,
+        level_type: InterruptLevel,
+    ) -> Result<Self, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.regs.interrupt_level(level_type);
+                self.irq_enb();
+                Ok(self)
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+
+    #[inline]
+    fn _read(&self) -> Result<bool, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DYN_RD_OPEN_DRAIN_OUTPUT | DYN_RD_PUSH_PULL_OUTPUT => {
+                Ok(self.regs.read_pin())
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+    #[inline]
+    fn _write(&mut self, bit: bool) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.regs.write_pin(bit);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(())),
+        }
+    }
+
+    #[inline]
+    fn _is_low(&self) -> Result<bool, InvalidPinTypeError> {
+        self._read().map(|v| !v)
+    }
+    #[inline]
+    fn _is_high(&self) -> Result<bool, InvalidPinTypeError> {
+        self._read()
+    }
+    #[inline]
+    fn _set_low(&mut self) -> Result<(), InvalidPinTypeError> {
+        self._write(false)
+    }
+    #[inline]
+    fn _set_high(&mut self) -> Result<(), InvalidPinTypeError> {
+        self._write(true)
+    }
+}
+
+//==============================================================================
+//  Convert between Pin and DynPin
+//==============================================================================
+
+impl<I, M> From<Pin<I, M>> for DynPin
+where
+    I: PinId,
+    M: PinMode,
+{
+    /// Erase the type-level information in a [`Pin`] and return a value-level
+    /// [`DynPin`]
+    #[inline]
+    fn from(_pin: Pin<I, M>) -> Self {
+        // The `Pin` is consumed, so it is safe to replace it with the
+        // corresponding `DynPin`
+        unsafe { DynPin::new(I::DYN, M::DYN) }
+    }
+}
+
+impl<I, M> TryFrom<DynPin> for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Error = InvalidPinTypeError;
+
+    /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
+    ///
+    /// There is no way for the compiler to know if the conversion will be
+    /// successful at compile-time. We must verify the conversion at run-time
+    /// or refuse to perform it.
+    #[inline]
+    fn try_from(pin: DynPin) -> Result<Self, Self::Error> {
+        if pin.regs.id == I::DYN && pin.mode == M::DYN {
+            // The `DynPin` is consumed, so it is safe to replace it with the
+            // corresponding `Pin`
+            Ok(unsafe { Self::new() })
+        } else {
+            Err(InvalidPinTypeError(()))
+        }
+    }
+}
+
+//==============================================================================
+// Embedded HAL v1 traits
+//==============================================================================
+
+impl ErrorType for DynPin {
+    type Error = InvalidPinTypeError;
+}
+
+impl OutputPin for DynPin {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self._set_high()
+    }
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self._set_low()
+    }
+}
+
+impl InputPin for DynPin {
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        self._is_high()
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        self._is_low()
+    }
+}
+
+impl StatefulOutputPin for DynPin {
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        self._is_high()
+    }
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        self._is_low()
+    }
+}

va416xx-hal/src/gpio/mod.rs

@@ -0,0 +1,82 @@
+//! # API for the GPIO peripheral
+//!
+//! The implementation of this GPIO module is heavily based on the
+//! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/index.html).
+//!
+//! This API provides two different submodules, [`mod@pins`] and [`dynpins`],
+//! representing two different ways to handle GPIO pins. The default, [`mod@pins`],
+//! is a type-level API that tracks the state of each pin at compile-time. The
+//! alternative, [`dynpins`] is a type-erased, value-level API that tracks the
+//! state of each pin at run-time.
+//!
+//! The type-level API is strongly preferred. By representing the state of each
+//! pin within the type system, the compiler can detect logic errors at
+//! compile-time. Furthermore, the type-level API has absolutely zero run-time
+//! cost.
+//!
+//! If needed, [`dynpins`] can be used to erase the type-level differences
+//! between pins. However, by doing so, pins must now be tracked at run-time,
+//! and each pin has a non-zero memory footprint.
+//!
+//! ## Examples
+//!
+//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/blinky.rs)
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct IsMaskedError(pub(crate) ());
+
+macro_rules! common_reg_if_functions {
+    () => {
+        paste::paste!(
+            #[inline]
+            pub fn datamask(&self) -> bool {
+                self.regs.datamask()
+            }
+
+            #[inline]
+            pub fn clear_datamask(self) -> Self {
+                self.regs.clear_datamask();
+                self
+            }
+
+            #[inline]
+            pub fn set_datamask(self) -> Self {
+                self.regs.set_datamask();
+                self
+            }
+
+            #[inline]
+            pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+                self.regs.read_pin_masked()
+            }
+
+            #[inline]
+            pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+                self.regs.read_pin_masked().map(|v| !v)
+            }
+
+            #[inline]
+            pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+                self.regs.write_pin_masked(true)
+            }
+
+            #[inline]
+            pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+                self.regs.write_pin_masked(false)
+            }
+
+            fn irq_enb(&mut self) {
+                self.regs.enable_irq();
+            }
+        );
+    };
+}
+
+pub mod pin;
+pub use pin::*;
+
+pub mod dynpin;
+pub use dynpin::*;
+
+mod reg;

va416xx-hal/src/gpio/pin.rs

@@ -0,0 +1,826 @@
+use core::{convert::Infallible, marker::PhantomData, mem::transmute};
+
+pub use crate::clock::FilterClkSel;
+use crate::Sealed;
+use embedded_hal::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin};
+use va416xx::{Porta, Portb, Portc, Portd, Porte, Portf, Portg};
+
+use super::{
+    reg::RegisterInterface, DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode,
+};
+
+//==================================================================================================
+//  Errors and Definitions
+//==================================================================================================
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum InterruptEdge {
+    HighToLow,
+    LowToHigh,
+    BothEdges,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum InterruptLevel {
+    Low = 0,
+    High = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum PinState {
+    Low = 0,
+    High = 1,
+}
+
+//==================================================================================================
+// Input configuration
+//==================================================================================================
+
+/// Type-level enum for input configurations
+///
+/// The valid options are [`Floating`], [`PullDown`] and [`PullUp`].
+pub trait InputConfig: Sealed {
+    /// Corresponding [`DynInput`](super::DynInput)
+    const DYN: DynInput;
+}
+
+pub enum Floating {}
+pub enum PullDown {}
+pub enum PullUp {}
+
+impl InputConfig for Floating {
+    const DYN: DynInput = DynInput::Floating;
+}
+impl InputConfig for PullDown {
+    const DYN: DynInput = DynInput::PullDown;
+}
+impl InputConfig for PullUp {
+    const DYN: DynInput = DynInput::PullUp;
+}
+
+impl Sealed for Floating {}
+impl Sealed for PullDown {}
+impl Sealed for PullUp {}
+
+/// Type-level variant of [`PinMode`] for floating input mode
+pub type InputFloating = Input<Floating>;
+/// Type-level variant of [`PinMode`] for pull-down input mode
+pub type InputPullDown = Input<PullDown>;
+/// Type-level variant of [`PinMode`] for pull-up input mode
+pub type InputPullUp = Input<PullUp>;
+
+/// Type-level variant of [`PinMode`] for input modes
+///
+/// Type `C` is one of three input configurations: [`Floating`], [`PullDown`] or
+/// [`PullUp`]
+pub struct Input<C: InputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: InputConfig> Sealed for Input<C> {}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterType {
+    SystemClock = 0,
+    DirectInputWithSynchronization = 1,
+    FilterOneClockCycle = 2,
+    FilterTwoClockCycles = 3,
+    FilterThreeClockCycles = 4,
+    FilterFourClockCycles = 5,
+}
+
+//==================================================================================================
+// Output configuration
+//==================================================================================================
+
+pub trait OutputConfig: Sealed {
+    const DYN: DynOutput;
+}
+
+pub trait ReadableOutput: Sealed {}
+
+/// Type-level variant of [`OutputConfig`] for a push-pull configuration
+pub enum PushPull {}
+/// Type-level variant of [`OutputConfig`] for an open drain configuration
+pub enum OpenDrain {}
+
+/// Type-level variant of [`OutputConfig`] for a readable push-pull configuration
+pub enum ReadablePushPull {}
+/// Type-level variant of [`OutputConfig`] for a readable open-drain configuration
+pub enum ReadableOpenDrain {}
+
+impl Sealed for PushPull {}
+impl Sealed for OpenDrain {}
+impl Sealed for ReadableOpenDrain {}
+impl Sealed for ReadablePushPull {}
+impl ReadableOutput for ReadableOpenDrain {}
+impl ReadableOutput for ReadablePushPull {}
+
+impl OutputConfig for PushPull {
+    const DYN: DynOutput = DynOutput::PushPull;
+}
+impl OutputConfig for OpenDrain {
+    const DYN: DynOutput = DynOutput::OpenDrain;
+}
+impl OutputConfig for ReadablePushPull {
+    const DYN: DynOutput = DynOutput::ReadablePushPull;
+}
+impl OutputConfig for ReadableOpenDrain {
+    const DYN: DynOutput = DynOutput::ReadableOpenDrain;
+}
+
+/// Type-level variant of [`PinMode`] for output modes
+///
+/// Type `C` is one of four output configurations: [`PushPull`], [`OpenDrain`] or
+/// their respective readable versions
+pub struct Output<C: OutputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: OutputConfig> Sealed for Output<C> {}
+
+/// Type-level variant of [`PinMode`] for push-pull output mode
+pub type PushPullOutput = Output<PushPull>;
+/// Type-level variant of [`PinMode`] for open drain output mode
+pub type OutputOpenDrain = Output<OpenDrain>;
+
+pub type OutputReadablePushPull = Output<ReadablePushPull>;
+pub type OutputReadableOpenDrain = Output<ReadableOpenDrain>;
+
+//==================================================================================================
+//  Alternate configurations
+//==================================================================================================
+
+/// Type-level enum for alternate peripheral function configurations
+pub trait AlternateConfig: Sealed {
+    const DYN: DynAlternate;
+}
+
+pub enum Funsel1 {}
+pub enum Funsel2 {}
+pub enum Funsel3 {}
+
+impl AlternateConfig for Funsel1 {
+    const DYN: DynAlternate = DynAlternate::Sel1;
+}
+impl AlternateConfig for Funsel2 {
+    const DYN: DynAlternate = DynAlternate::Sel2;
+}
+impl AlternateConfig for Funsel3 {
+    const DYN: DynAlternate = DynAlternate::Sel3;
+}
+
+impl Sealed for Funsel1 {}
+impl Sealed for Funsel2 {}
+impl Sealed for Funsel3 {}
+
+/// Type-level variant of [`PinMode`] for alternate peripheral functions
+///
+/// Type `C` is an [`AlternateConfig`]
+pub struct Alternate<C: AlternateConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: AlternateConfig> Sealed for Alternate<C> {}
+
+pub type AltFunc1 = Alternate<Funsel1>;
+pub type AltFunc2 = Alternate<Funsel2>;
+pub type AltFunc3 = Alternate<Funsel3>;
+
+/// Type alias for the [`PinMode`] at reset
+pub type Reset = InputFloating;
+
+//==================================================================================================
+//  Pin modes
+//==================================================================================================
+
+/// Type-level enum representing pin modes
+///
+/// The valid options are [`Input`], [`Output`] and [`Alternate`].
+pub trait PinMode: Sealed {
+    /// Corresponding [`DynPinMode`](super::DynPinMode)
+    const DYN: DynPinMode;
+}
+
+impl<C: InputConfig> PinMode for Input<C> {
+    const DYN: DynPinMode = DynPinMode::Input(C::DYN);
+}
+impl<C: OutputConfig> PinMode for Output<C> {
+    const DYN: DynPinMode = DynPinMode::Output(C::DYN);
+}
+impl<C: AlternateConfig> PinMode for Alternate<C> {
+    const DYN: DynPinMode = DynPinMode::Alternate(C::DYN);
+}
+
+//==================================================================================================
+//  Pin IDs
+//==================================================================================================
+
+/// Type-level enum for pin IDs
+pub trait PinId: Sealed {
+    /// Corresponding [`DynPinId`](super::DynPinId)
+    const DYN: DynPinId;
+}
+
+macro_rules! pin_id {
+    ($Group:ident, $Id:ident, $NUM:literal) => {
+        // Need paste macro to use ident in doc attribute
+        paste::paste! {
+            #[doc = "Pin ID representing pin " $Id]
+            pub enum $Id {}
+            impl Sealed for $Id {}
+            impl PinId for $Id {
+                const DYN: DynPinId = DynPinId {
+                    group: DynGroup::$Group,
+                    num: $NUM,
+                };
+            }
+        }
+    };
+}
+
+//==================================================================================================
+//  Pin
+//==================================================================================================
+
+/// A type-level GPIO pin, parameterized by [`PinId`] and [`PinMode`] types
+
+pub struct Pin<I: PinId, M: PinMode> {
+    pub(in crate::gpio) regs: Registers<I>,
+    mode: PhantomData<M>,
+}
+
+impl<I: PinId, M: PinMode> Pin<I, M> {
+    /// Create a new [`Pin`]
+    ///
+    /// # Safety
+    ///
+    /// Each [`Pin`] must be a singleton. For a given [`PinId`], there must be
+    /// at most one corresponding [`Pin`] in existence at any given time.
+    /// Violating this requirement is `unsafe`.
+    #[inline]
+    pub(crate) unsafe fn new() -> Pin<I, M> {
+        Pin {
+            regs: Registers::new(),
+            mode: PhantomData,
+        }
+    }
+
+    /// Convert the pin to the requested [`PinMode`]
+    #[inline]
+    pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
+        // Only modify registers if we are actually changing pin mode
+        // This check should compile away
+        if N::DYN != M::DYN {
+            self.regs.change_mode::<N>();
+        }
+        // Safe because we drop the existing Pin
+        unsafe { Pin::new() }
+    }
+
+    /// Configure the pin for function select 1. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_1(self) -> Pin<I, AltFunc1> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 2. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_2(self) -> Pin<I, AltFunc2> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 3. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_3(self) -> Pin<I, AltFunc3> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(self) -> Pin<I, InputFloating> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(self) -> Pin<I, InputPullDown> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(self) -> Pin<I, InputPullUp> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(self) -> Pin<I, PushPullOutput> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(self) -> Pin<I, OutputReadablePushPull> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable open-drain output
+    #[inline]
+    pub fn into_readable_open_drain_output(self) -> Pin<I, OutputReadableOpenDrain> {
+        self.into_mode()
+    }
+
+    common_reg_if_functions!();
+
+    #[inline]
+    pub(crate) fn _set_high(&mut self) {
+        self.regs.write_pin(true)
+    }
+
+    #[inline]
+    pub(crate) fn _set_low(&mut self) {
+        self.regs.write_pin(false)
+    }
+
+    #[inline]
+    pub(crate) fn _is_low(&self) -> bool {
+        !self.regs.read_pin()
+    }
+
+    #[inline]
+    pub(crate) fn _is_high(&self) -> bool {
+        self.regs.read_pin()
+    }
+}
+
+//==============================================================================
+//  AnyPin
+//==============================================================================
+
+/// Type class for [`Pin`] types
+///
+/// This trait uses the [`AnyKind`] trait pattern to create a [type class] for
+/// [`Pin`] types. See the `AnyKind` documentation for more details on the
+/// pattern.
+///
+/// ## `v1` Compatibility
+///
+/// Normally, this trait would use `Is<Type = SpecificPin<Self>>` as a super
+/// trait. But doing so would restrict implementations to only the `v2` `Pin`
+/// type in this module. To aid in backwards compatibility, we want to implement
+/// `AnyPin` for the `v1` `Pin` type as well. This is possible for a few
+/// reasons. First, both structs are zero-sized, so there is no meaningful
+/// memory layout to begin with. And even if there were, the `v1` `Pin` type is
+/// a newtype wrapper around a `v2` `Pin`, and single-field structs are
+/// guaranteed to have the same layout as the field, even for `repr(Rust)`.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+/// [type class]: crate::typelevel#type-classes
+pub trait AnyPin
+where
+    Self: Sealed,
+    Self: From<SpecificPin<Self>>,
+    Self: Into<SpecificPin<Self>>,
+    Self: AsRef<SpecificPin<Self>>,
+    Self: AsMut<SpecificPin<Self>>,
+{
+    /// [`PinId`] of the corresponding [`Pin`]
+    type Id: PinId;
+    /// [`PinMode`] of the corresponding [`Pin`]
+    type Mode: PinMode;
+}
+
+impl<I, M> Sealed for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+}
+
+impl<I, M> AnyPin for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Id = I;
+    type Mode = M;
+}
+
+/// Type alias to recover the specific [`Pin`] type from an implementation of
+/// [`AnyPin`]
+///
+/// See the [`AnyKind`] documentation for more details on the pattern.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+pub type SpecificPin<P> = Pin<<P as AnyPin>::Id, <P as AnyPin>::Mode>;
+
+impl<P: AnyPin> AsRef<P> for SpecificPin<P> {
+    #[inline]
+    fn as_ref(&self) -> &P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
+    #[inline]
+    fn as_mut(&mut self) -> &mut P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+//==================================================================================================
+//  Additional functionality
+//==================================================================================================
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Self {
+        self.regs.interrupt_edge(edge_type);
+        self.irq_enb();
+        self
+    }
+
+    pub fn interrupt_level(mut self, level_type: InterruptLevel) -> Self {
+        self.regs.interrupt_level(level_type);
+        self.irq_enb();
+        self
+    }
+}
+
+impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn delay(self, delay_1: bool, delay_2: bool) -> Self {
+        self.regs.delay(delay_1, delay_2);
+        self
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    pub fn pulse_mode(self, enable: bool, default_state: PinState) -> Self {
+        self.regs.pulse_mode(enable, default_state);
+        self
+    }
+
+    pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Self {
+        self.regs.interrupt_edge(edge_type);
+        self.irq_enb();
+        self
+    }
+
+    pub fn interrupt_level(mut self, level_type: InterruptLevel) -> Self {
+        self.regs.interrupt_level(level_type);
+        self.irq_enb();
+        self
+    }
+}
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn filter_type(self, filter: FilterType, clksel: FilterClkSel) -> Self {
+        self.regs.filter_type(filter, clksel);
+        self
+    }
+}
+
+//==================================================================================================
+//  Embedded HAL traits
+//==================================================================================================
+
+impl<I, M> ErrorType for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Error = Infallible;
+}
+
+impl<I: PinId, C: OutputConfig> OutputPin for Pin<I, Output<C>> {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self._set_high();
+        Ok(())
+    }
+
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self._set_low();
+        Ok(())
+    }
+}
+
+impl<I, C> InputPin for Pin<I, Input<C>>
+where
+    I: PinId,
+    C: InputConfig,
+{
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+impl<I, C> StatefulOutputPin for Pin<I, Output<C>>
+where
+    I: PinId,
+    C: OutputConfig + ReadableOutput,
+{
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_high())
+    }
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+//==================================================================================================
+//  Registers
+//==================================================================================================
+
+/// Provide a safe register interface for [`Pin`]s
+///
+/// This `struct` takes ownership of a [`PinId`] and provides an API to
+/// access the corresponding registers.
+pub(in crate::gpio) struct Registers<I: PinId> {
+    id: PhantomData<I>,
+}
+
+// [`Registers`] takes ownership of the [`PinId`], and [`Pin`] guarantees that
+// each pin is a singleton, so this implementation is safe.
+unsafe impl<I: PinId> RegisterInterface for Registers<I> {
+    #[inline]
+    fn id(&self) -> DynPinId {
+        I::DYN
+    }
+}
+
+impl<I: PinId> Registers<I> {
+    /// Create a new instance of [`Registers`]
+    ///
+    /// # Safety
+    ///
+    /// Users must never create two simultaneous instances of this `struct` with
+    /// the same [`PinId`]
+    #[inline]
+    unsafe fn new() -> Self {
+        Registers { id: PhantomData }
+    }
+
+    /// Provide a type-level equivalent for the
+    /// [`RegisterInterface::change_mode`] method.
+    #[inline]
+    pub(in crate::gpio) fn change_mode<M: PinMode>(&mut self) {
+        RegisterInterface::change_mode(self, M::DYN);
+    }
+}
+
+//==================================================================================================
+//  Pin definitions
+//==================================================================================================
+
+macro_rules! pins {
+    (
+        $Port:ident, $PinsName:ident, $($Id:ident,)+,
+    ) => {
+        paste::paste!(
+            /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
+            pub struct $PinsName {
+                iocfg: Option<va416xx::Ioconfig>,
+                port: $Port,
+                $(
+                    #[doc = "Pin " $Id]
+                    pub [<$Id:lower>]: Pin<$Id, Reset>,
+                )+
+            }
+
+            impl $PinsName {
+                /// Create a new struct containing all the Pins. Passing the IOCONFIG peripheral
+                /// is optional because it might be required to create pin definitions for both
+                /// ports.
+                #[inline]
+                pub fn new(
+                    syscfg: &mut va416xx::Sysconfig,
+                    iocfg: Option<va416xx::Ioconfig>,
+                    port: $Port
+                ) -> $PinsName {
+                    syscfg.peripheral_clk_enable().modify(|_, w| {
+                        w.[<$Port:lower>]().set_bit();
+                        w.ioconfig().set_bit()
+                    });
+                    $PinsName {
+                        iocfg,
+                        port,
+                        // Safe because we only create one `Pin` per `PinId`
+                        $(
+                            [<$Id:lower>]: unsafe { Pin::new() },
+                        )+
+                    }
+                }
+
+                /// Get the peripheral ID
+                /// Safety: Read-only register
+                pub fn get_perid() -> u32 {
+                    let port = unsafe { &(*$Port::ptr()) };
+                    port.perid().read().bits()
+                }
+
+                /// Consumes the Pins struct and returns the port definitions
+                pub fn release(self) -> (Option<va416xx::Ioconfig>, $Port) {
+                    (self.iocfg, self.port)
+                }
+            }
+        );
+    }
+}
+
+macro_rules! declare_pins {
+    (
+        $Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+]
+    ) => {
+        pins!($Port, $PinsName, $($Id,)+,);
+        $(
+            pin_id!($Group, $Id, $NUM);
+        )+
+    }
+}
+
+declare_pins!(
+    A,
+    PinsA,
+    Porta,
+    [
+        (PA0, 0),
+        (PA1, 1),
+        (PA2, 2),
+        (PA3, 3),
+        (PA4, 4),
+        (PA5, 5),
+        (PA6, 6),
+        (PA7, 7),
+        (PA8, 8),
+        (PA9, 9),
+        (PA10, 10),
+        (PA11, 11),
+        (PA12, 12),
+        (PA13, 13),
+        (PA14, 14),
+        (PA15, 15),
+    ]
+);
+
+declare_pins!(
+    B,
+    PinsB,
+    Portb,
+    [
+        (PB0, 0),
+        (PB1, 1),
+        (PB2, 2),
+        (PB3, 3),
+        (PB4, 4),
+        (PB5, 5),
+        (PB6, 6),
+        (PB7, 7),
+        (PB8, 8),
+        (PB9, 9),
+        (PB10, 10),
+        (PB11, 11),
+        (PB12, 12),
+        (PB13, 13),
+        (PB14, 14),
+        (PB15, 15),
+    ]
+);
+
+declare_pins!(
+    C,
+    PinsC,
+    Portc,
+    [
+        (PC0, 0),
+        (PC1, 1),
+        (PC2, 2),
+        (PC3, 3),
+        (PC4, 4),
+        (PC5, 5),
+        (PC6, 6),
+        (PC7, 7),
+        (PC8, 8),
+        (PC9, 9),
+        (PC10, 10),
+        (PC11, 11),
+        (PC12, 12),
+        (PC13, 13),
+        (PC14, 14),
+        (PC15, 15),
+    ]
+);
+
+declare_pins!(
+    D,
+    PinsD,
+    Portd,
+    [
+        (PD0, 0),
+        (PD1, 1),
+        (PD2, 2),
+        (PD3, 3),
+        (PD4, 4),
+        (PD5, 5),
+        (PD6, 6),
+        (PD7, 7),
+        (PD8, 8),
+        (PD9, 9),
+        (PD10, 10),
+        (PD11, 11),
+        (PD12, 12),
+        (PD13, 13),
+        (PD14, 14),
+        (PD15, 15),
+    ]
+);
+
+declare_pins!(
+    E,
+    PinsE,
+    Porte,
+    [
+        (PE0, 0),
+        (PE1, 1),
+        (PE2, 2),
+        (PE3, 3),
+        (PE4, 4),
+        (PE5, 5),
+        (PE6, 6),
+        (PE7, 7),
+        (PE8, 8),
+        (PE9, 9),
+        (PE10, 10),
+        (PE11, 11),
+        (PE12, 12),
+        (PE13, 13),
+        (PE14, 14),
+        (PE15, 15),
+    ]
+);
+
+declare_pins!(
+    F,
+    PinsF,
+    Portf,
+    [
+        (PF0, 0),
+        (PF1, 1),
+        (PF2, 2),
+        (PF3, 3),
+        (PF4, 4),
+        (PF5, 5),
+        (PF6, 6),
+        (PF7, 7),
+        (PF8, 8),
+        (PF9, 9),
+        (PF10, 10),
+        (PF11, 11),
+        (PF12, 12),
+        (PF13, 13),
+        (PF14, 14),
+        (PF15, 15),
+    ]
+);
+
+declare_pins!(
+    G,
+    PinsG,
+    Portg,
+    [
+        (PG0, 0),
+        (PG1, 1),
+        (PG2, 2),
+        (PG3, 3),
+        (PG4, 4),
+        (PG5, 5),
+        (PG6, 6),
+        (PG7, 7),
+    ]
+);

va416xx-hal/src/gpio/reg.rs

@@ -0,0 +1,387 @@
+use crate::FunSel;
+
+use super::{
+    dynpin::{self, DynGroup, DynPinId},
+    DynPinMode, FilterClkSel, FilterType, InterruptEdge, InterruptLevel, IsMaskedError, PinState,
+};
+use va416xx::{ioconfig, porta, Ioconfig, Porta, Portb, Portc, Portd, Porte, Portf, Portg};
+
+/// Type definition to avoid confusion: These register blocks are identical
+type PortRegisterBlock = porta::RegisterBlock;
+
+//==================================================================================================
+//  ModeFields
+//==================================================================================================
+
+/// Collect all fields needed to set the [`PinMode`](super::PinMode)
+#[derive(Default)]
+struct ModeFields {
+    dir: bool,
+    opendrn: bool,
+    pull_en: bool,
+    /// true for pullup, false for pulldown
+    pull_dir: bool,
+    funsel: u8,
+    enb_input: bool,
+}
+
+impl From<DynPinMode> for ModeFields {
+    #[inline]
+    fn from(mode: DynPinMode) -> Self {
+        let mut fields = Self::default();
+        use DynPinMode::*;
+        match mode {
+            Input(config) => {
+                use dynpin::DynInput::*;
+                fields.dir = false;
+                fields.funsel = FunSel::Sel0 as u8;
+                match config {
+                    Floating => (),
+                    PullUp => {
+                        fields.pull_en = true;
+                        fields.pull_dir = true;
+                    }
+                    PullDown => {
+                        fields.pull_en = true;
+                    }
+                }
+            }
+            Output(config) => {
+                use dynpin::DynOutput::*;
+                fields.dir = true;
+                fields.funsel = FunSel::Sel0 as u8;
+                match config {
+                    PushPull => (),
+                    OpenDrain => {
+                        fields.opendrn = true;
+                    }
+                    ReadableOpenDrain => {
+                        fields.enb_input = true;
+                        fields.opendrn = true;
+                    }
+                    ReadablePushPull => {
+                        fields.enb_input = true;
+                    }
+                }
+            }
+            Alternate(config) => {
+                fields.funsel = config as u8;
+            }
+        }
+        fields
+    }
+}
+
+//==============================================================================
+//  RegisterInterface
+//==============================================================================
+
+pub type PortReg = ioconfig::Porta;
+
+/// Provide a safe register interface for pin objects
+///
+/// [`PORT`], like every PAC `struct`, is [`Send`] but not [`Sync`], because it
+/// points to a `RegisterBlock` of `VolatileCell`s. Unfortunately, such an
+/// interface is quite restrictive. Instead, it would be ideal if we could split
+/// the [`PORT`] into independent pins that are both [`Send`] and [`Sync`].
+///
+/// [`PORT`] is a single, zero-sized marker `struct` that provides access to
+/// every [`PORT`] register. Instead, we would like to create zero-sized marker
+/// `struct`s for every pin, where each pin is only allowed to control its own
+/// registers. Furthermore, each pin `struct` should be a singleton, so that
+/// exclusive access to the `struct` also guarantees exclusive access to the
+/// corresponding registers. Finally, the pin `struct`s should not have any
+/// interior mutability. Together, these requirements would allow the pin
+/// `struct`s to be both [`Send`] and [`Sync`].
+///
+/// This trait creates a safe API for accomplishing these goals. Implementers
+/// supply a pin ID through the [`id`] function. The remaining functions provide
+/// a safe API for accessing the registers associated with that pin ID. Any
+/// modification of the registers requires `&mut self`, which destroys interior
+/// mutability.
+///
+/// # Safety
+///
+/// Users should only implement the [`id`] function. No default function
+/// implementations should be overridden. The implementing type must also have
+/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
+/// pin ID is a singleton.
+///
+/// [`id`]: Self::id
+pub(super) unsafe trait RegisterInterface {
+    /// Provide a [`DynPinId`] identifying the set of registers controlled by
+    /// this type.
+    fn id(&self) -> DynPinId;
+
+    const PORTA: *const PortRegisterBlock = Porta::ptr();
+    const PORTB: *const PortRegisterBlock = Portb::ptr();
+    const PORTC: *const PortRegisterBlock = Portc::ptr();
+    const PORTD: *const PortRegisterBlock = Portd::ptr();
+    const PORTE: *const PortRegisterBlock = Porte::ptr();
+    const PORTF: *const PortRegisterBlock = Portf::ptr();
+    const PORTG: *const PortRegisterBlock = Portg::ptr();
+
+    /// Change the pin mode
+    #[inline]
+    fn change_mode(&mut self, mode: DynPinMode) {
+        let ModeFields {
+            dir,
+            funsel,
+            opendrn,
+            pull_dir,
+            pull_en,
+            enb_input,
+        } = mode.into();
+        let (portreg, iocfg) = (self.port_reg(), self.iocfg_port());
+        iocfg.write(|w| {
+            w.opendrn().bit(opendrn);
+            w.pen().bit(pull_en);
+            w.plevel().bit(pull_dir);
+            w.iewo().bit(enb_input);
+            unsafe { w.funsel().bits(funsel) }
+        });
+        let mask = self.mask_32();
+        unsafe {
+            if dir {
+                portreg.dir().modify(|r, w| w.bits(r.bits() | mask));
+                // Clear output
+                portreg.clrout().write(|w| w.bits(mask));
+            } else {
+                portreg.dir().modify(|r, w| w.bits(r.bits() & !mask));
+            }
+        }
+    }
+
+    #[inline]
+    fn port_reg(&self) -> &PortRegisterBlock {
+        match self.id().group {
+            DynGroup::A => unsafe { &(*Self::PORTA) },
+            DynGroup::B => unsafe { &(*Self::PORTB) },
+            DynGroup::C => unsafe { &(*Self::PORTC) },
+            DynGroup::D => unsafe { &(*Self::PORTD) },
+            DynGroup::E => unsafe { &(*Self::PORTE) },
+            DynGroup::F => unsafe { &(*Self::PORTF) },
+            DynGroup::G => unsafe { &(*Self::PORTG) },
+        }
+    }
+
+    fn iocfg_port(&self) -> &PortReg {
+        let ioconfig = unsafe { Ioconfig::ptr().as_ref().unwrap() };
+        match self.id().group {
+            DynGroup::A => ioconfig.porta(self.id().num as usize),
+            DynGroup::B => ioconfig.portb0(self.id().num as usize),
+            DynGroup::C => ioconfig.portc0(self.id().num as usize),
+            DynGroup::D => ioconfig.portd0(self.id().num as usize),
+            DynGroup::E => ioconfig.porte0(self.id().num as usize),
+            DynGroup::F => ioconfig.portf0(self.id().num as usize),
+            DynGroup::G => ioconfig.portg0(self.id().num as usize),
+        }
+    }
+
+    #[inline]
+    fn mask_32(&self) -> u32 {
+        1 << self.id().num
+    }
+
+    #[inline]
+    fn enable_irq(&self) {
+        self.port_reg()
+            .irq_enb()
+            .modify(|r, w| unsafe { w.bits(r.bits() | self.mask_32()) });
+    }
+
+    #[inline]
+    /// Read the logic level of an output pin
+    fn read_pin(&self) -> bool {
+        let portreg = self.port_reg();
+        ((portreg.datainraw().read().bits() >> self.id().num) & 0x01) == 1
+    }
+
+    // Get DATAMASK bit for this particular pin
+    #[inline(always)]
+    fn datamask(&self) -> bool {
+        let portreg = self.port_reg();
+        (portreg.datamask().read().bits() >> self.id().num) == 1
+    }
+
+    /// Read a pin but use the masked version but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline(always)]
+    fn read_pin_masked(&self) -> Result<bool, IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError(()))
+        } else {
+            Ok(((self.port_reg().datain().read().bits() >> self.id().num) & 0x01) == 1)
+        }
+    }
+
+    /// Write the logic level of an output pin
+    #[inline(always)]
+    fn write_pin(&mut self, bit: bool) {
+        // Safety: SETOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe {
+            if bit {
+                self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+            } else {
+                self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+            }
+        }
+    }
+
+    /// Write the logic level of an output pin but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline]
+    fn write_pin_masked(&mut self, bit: bool) -> Result<(), IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError(()))
+        } else {
+            // Safety: SETOUT is a "mask" register, and we only write the bit for
+            // this pin ID
+            unsafe {
+                if bit {
+                    self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+                } else {
+                    self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+                }
+                Ok(())
+            }
+        }
+    }
+
+    /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
+    /// When using edge mode, it is possible to generate interrupts on both edges as well
+    #[inline]
+    fn interrupt_edge(&mut self, edge_type: InterruptEdge) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            match edge_type {
+                InterruptEdge::HighToLow => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+                }
+                InterruptEdge::LowToHigh => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+                InterruptEdge::BothEdges => {
+                    self.port_reg()
+                        .irq_edge()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+            }
+        }
+    }
+
+    /// Configure which edge or level type triggers an interrupt
+    #[inline]
+    fn interrupt_level(&mut self, level: InterruptLevel) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            if level == InterruptLevel::Low {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for input pins
+    #[inline]
+    fn filter_type(&self, filter: FilterType, clksel: FilterClkSel) {
+        self.iocfg_port().modify(|_, w| {
+            // Safety: Only write to register for this Pin ID
+            unsafe {
+                w.flttype().bits(filter as u8);
+                w.fltclk().bits(clksel as u8)
+            }
+        });
+    }
+
+    /// Set DATAMASK bit for this particular pin. 1 is the default
+    /// state of the bit and allows access of the corresponding bit
+    #[inline(always)]
+    fn set_datamask(&self) {
+        let portreg = self.port_reg();
+        unsafe {
+            portreg
+                .datamask()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()))
+        }
+    }
+
+    /// Clear DATAMASK bit for this particular pin. This prevents access
+    /// of the corresponding bit for output and input operations
+    #[inline(always)]
+    fn clear_datamask(&self) {
+        let portreg = self.port_reg();
+        unsafe {
+            portreg
+                .datamask()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()))
+        }
+    }
+
+    /// Only useful for output pins
+    /// See p.52 of the programmers guide for more information.
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    fn pulse_mode(&self, enable: bool, default_state: PinState) {
+        let portreg = self.port_reg();
+        unsafe {
+            if enable {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if default_state == PinState::Low {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for output pins
+    fn delay(&self, delay_1: bool, delay_2: bool) {
+        let portreg = self.port_reg();
+        unsafe {
+            if delay_1 {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if delay_2 {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+        }
+    }
+}

va416xx-hal/src/lib.rs

@@ -0,0 +1,46 @@
+#![no_std]
+
+pub use va416xx;
+pub use va416xx as pac;
+pub mod prelude;
+
+pub mod clock;
+pub mod gpio;
+pub mod time;
+pub mod typelevel;
+
+#[derive(Debug, Eq, Copy, Clone, PartialEq)]
+pub enum FunSel {
+    Sel0 = 0b00,
+    Sel1 = 0b01,
+    Sel2 = 0b10,
+    Sel3 = 0b11,
+}
+
+/// Generic IRQ config which can be used to specify whether the HAL driver will
+/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
+/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
+/// this steps themselves
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+pub struct IrqCfg {
+    /// Interrupt target vector. Should always be set, might be required for disabling IRQs
+    pub irq: pac::Interrupt,
+    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral
+    pub route: bool,
+    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC
+    pub enable: bool,
+}
+
+impl IrqCfg {
+    pub fn new(irq: pac::Interrupt, route: bool, enable: bool) -> Self {
+        IrqCfg { irq, route, enable }
+    }
+}
+
+mod private {
+    /// Super trait used to mark traits with an exhaustive set of
+    /// implementations
+    pub trait Sealed {}
+}
+
+pub(crate) use private::Sealed;

va416xx-hal/src/prelude.rs

@@ -0,0 +1 @@
+

va416xx-hal/src/time.rs

@@ -0,0 +1,156 @@
+//! Time units
+//!
+//! See [`Hertz`], [`KiloHertz`] and [`MegaHertz`] for creating increasingly higher frequencies.
+//!
+//! The [`U32Ext`] trait adds various methods like `.hz()`, `.mhz()`, etc to the `u32` primitive type,
+//! allowing it to be converted into frequencies.
+
+/// Bits per second
+#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+pub struct Bps(pub u32);
+
+/// Hertz
+///
+/// Create a frequency specified in [Hertz](https://en.wikipedia.org/wiki/Hertz).
+///
+/// See also [`KiloHertz`] and [`MegaHertz`] for semantically correct ways of creating higher
+/// frequencies.
+///
+/// # Examples
+///
+/// ## Create an 60 Hz frequency
+///
+/// ```rust
+/// use stm32f1xx_hal::time::Hertz;
+///
+/// let freq = 60.hz();
+/// ```
+#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+pub struct Hertz(pub u32);
+
+/// Kilohertz
+///
+/// Create a frequency specified in kilohertz.
+///
+/// See also [`Hertz`] and [`MegaHertz`] for semantically correct ways of creating lower or higher
+/// frequencies.
+///
+/// # Examples
+///
+/// ## Create a 100 Khz frequency
+///
+/// This example creates a 100 KHz frequency. This could be used to set an I2C data rate or PWM
+/// frequency, etc.
+///
+/// ```rust
+/// use stm32f1xx_hal::time::Hertz;
+///
+/// let freq = 100.khz();
+/// ```
+#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+pub struct KiloHertz(pub u32);
+
+/// Megahertz
+///
+/// Create a frequency specified in megahertz.
+///
+/// See also [`Hertz`] and [`KiloHertz`] for semantically correct ways of creating lower
+/// frequencies.
+///
+/// # Examples
+///
+/// ## Create a an 8 MHz frequency
+///
+/// This example creates an 8 MHz frequency that could be used to configure an SPI peripheral, etc.
+///
+/// ```rust
+/// use stm32f1xx_hal::time::Hertz;
+///
+/// let freq = 8.mhz();
+/// ```
+#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+pub struct MegaHertz(pub u32);
+
+/// Time unit
+#[derive(PartialEq, PartialOrd, Clone, Copy)]
+pub struct MilliSeconds(pub u32);
+
+#[derive(PartialEq, PartialOrd, Clone, Copy)]
+pub struct MicroSeconds(pub u32);
+
+/// Extension trait that adds convenience methods to the `u32` type
+pub trait U32Ext {
+    /// Wrap in `Bps`
+    fn bps(self) -> Bps;
+
+    /// Wrap in `Hertz`
+    fn hz(self) -> Hertz;
+
+    /// Wrap in `KiloHertz`
+    fn khz(self) -> KiloHertz;
+
+    /// Wrap in `MegaHertz`
+    fn mhz(self) -> MegaHertz;
+
+    /// Wrap in `MilliSeconds`
+    fn ms(self) -> MilliSeconds;
+
+    /// Wrap in `MicroSeconds`
+    fn us(self) -> MicroSeconds;
+}
+
+impl U32Ext for u32 {
+    fn bps(self) -> Bps {
+        Bps(self)
+    }
+
+    fn hz(self) -> Hertz {
+        Hertz(self)
+    }
+
+    fn khz(self) -> KiloHertz {
+        KiloHertz(self)
+    }
+
+    fn mhz(self) -> MegaHertz {
+        MegaHertz(self)
+    }
+
+    fn ms(self) -> MilliSeconds {
+        MilliSeconds(self)
+    }
+
+    fn us(self) -> MicroSeconds {
+        MicroSeconds(self)
+    }
+}
+
+impl From<KiloHertz> for Hertz {
+    fn from(val: KiloHertz) -> Self {
+        Self(val.0 * 1_000)
+    }
+}
+
+impl From<MegaHertz> for Hertz {
+    fn from(val: MegaHertz) -> Self {
+        Self(val.0 * 1_000_000)
+    }
+}
+
+impl From<MegaHertz> for KiloHertz {
+    fn from(val: MegaHertz) -> Self {
+        Self(val.0 * 1_000)
+    }
+}
+
+impl From<MilliSeconds> for Hertz {
+    fn from(val: MilliSeconds) -> Self {
+        Self(1_000 / val.0)
+    }
+}
+
+impl From<MicroSeconds> for Hertz {
+    fn from(val: MicroSeconds) -> Self {
+        Self(1_000_000 / val.0)
+    }
+}

va416xx-hal/src/typelevel.rs

@@ -0,0 +1,155 @@
+//! Module supporting type-level programming
+//!
+//! This module is identical to the
+//! [atsamd typelevel](https://docs.rs/atsamd-hal/latest/atsamd_hal/typelevel/index.html).
+
+use core::ops::{Add, Sub};
+
+use typenum::{Add1, Bit, Sub1, UInt, Unsigned, B1, U0};
+
+mod private {
+    /// Super trait used to mark traits with an exhaustive set of
+    /// implementations
+    pub trait Sealed {}
+
+    impl Sealed for u8 {}
+    impl Sealed for i8 {}
+    impl Sealed for u16 {}
+    impl Sealed for i16 {}
+    impl Sealed for u32 {}
+    impl Sealed for i32 {}
+    impl Sealed for f32 {}
+
+    /// Mapping from an instance of a countable type to its successor
+    pub trait Increment {
+        /// Successor type of `Self`
+        type Inc;
+        /// Consume an instance of `Self` and return its successor
+        fn inc(self) -> Self::Inc;
+    }
+
+    /// Mapping from an instance of a countable type to its predecessor
+    pub trait Decrement {
+        /// Predecessor type of `Self`
+        type Dec;
+        /// Consume an instance of `Self` and return its predecessor
+        fn dec(self) -> Self::Dec;
+    }
+}
+
+pub(crate) use private::Decrement as PrivateDecrement;
+pub(crate) use private::Increment as PrivateIncrement;
+pub(crate) use private::Sealed;
+
+/// Type-level version of the [`None`] variant
+#[derive(Default)]
+pub struct NoneT;
+
+impl Sealed for NoneT {}
+
+//==============================================================================
+// Is
+//==============================================================================
+
+/// Marker trait for type identity
+///
+/// This trait is used as part of the [`AnyKind`] trait pattern. It represents
+/// the concept of type identity, because all implementors have
+/// `<Self as Is>::Type == Self`. When used as a trait bound with a specific
+/// type, it guarantees that the corresponding type parameter is exactly the
+/// specific type. Stated differently, it guarantees that `T == Specific` in
+/// the following example.
+///
+/// ```
+/// where T: Is<Type = Specific>
+/// ```
+///
+/// Moreover, the super traits guarantee that any instance of or reference to a
+/// type `T` can be converted into the `Specific` type.
+///
+/// ```
+/// fn example<T>(mut any: T)
+/// where
+///     T: Is<Type = Specific>,
+/// {
+///     let specific_mut: &mut Specific = any.as_mut();
+///     let specific_ref: &Specific = any.as_ref();
+///     let specific: Specific = any.into();
+/// }
+/// ```
+///
+/// [`AnyKind`]: #anykind-trait-pattern
+pub trait Is
+where
+    Self: Sealed,
+    Self: From<IsType<Self>>,
+    Self: Into<IsType<Self>>,
+    Self: AsRef<IsType<Self>>,
+    Self: AsMut<IsType<Self>>,
+{
+    type Type;
+}
+
+/// Type alias for [`Is::Type`]
+pub type IsType<T> = <T as Is>::Type;
+
+impl<T> Is for T
+where
+    T: Sealed + AsRef<T> + AsMut<T>,
+{
+    type Type = T;
+}
+
+//==============================================================================
+// Counting
+//==============================================================================
+
+/// Implement `Sealed` for [`U0`]
+impl Sealed for U0 {}
+
+/// Implement `Sealed` for all type-level, [`Unsigned`] integers *except* [`U0`]
+impl<U: Unsigned, B: Bit> Sealed for UInt<U, B> {}
+
+/// Trait mapping each countable type to its successor
+///
+/// This trait maps each countable type to its corresponding successor type. The
+/// actual implementation of this trait is contained within `PrivateIncrement`.
+/// Access to `PrivateIncrement` is restricted, so that safe HAL APIs can be
+/// built with it.
+pub trait Increment: PrivateIncrement {}
+
+impl<T: PrivateIncrement> Increment for T {}
+
+/// Trait mapping each countable type to its predecessor
+///
+/// This trait maps each countable type to its corresponding predecessor type.
+/// The actual implementation of this trait is contained within
+/// `PrivateDecrement`. Access to `PrivateDecrement` is restricted, so that safe
+/// HAL APIs can be built with it.
+pub trait Decrement: PrivateDecrement {}
+
+impl<T: PrivateDecrement> Decrement for T {}
+
+impl<N> PrivateIncrement for N
+where
+    N: Unsigned + Add<B1>,
+    Add1<N>: Unsigned,
+{
+    type Inc = Add1<N>;
+    #[inline]
+    fn inc(self) -> Self::Inc {
+        Self::Inc::default()
+    }
+}
+
+impl<N> PrivateDecrement for N
+where
+    N: Unsigned + Sub<B1>,
+    Sub1<N>: Unsigned,
+{
+    type Dec = Sub1<N>;
+    #[inline]
+    fn dec(self) -> Self::Dec {
+        Self::Dec::default()
+    }
+}

va416xx/.github/bors.toml

@@ -0,0 +1,2 @@
+status = ["ci"]
+delete_merged_branches = true

va416xx/.github/workflows/changelog.yml

@@ -0,0 +1,20 @@
+on:
+  pull_request_target:
+
+name: Changelog check
+
+jobs:
+  changelog:
+    name: Changelog check
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout sources
+        uses: actions/checkout@v2
+
+      - name: Changelog updated
+        uses: Zomzog/changelog-checker@v1.2.0
+        with:
+          fileName: CHANGELOG.md
+          noChangelogLabel: no changelog
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

va416xx/.github/workflows/ci.yml

@@ -0,0 +1,64 @@
+on: [push]
+
+name: build
+
+jobs:
+  check:
+    name: Check
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          target: thumbv7em-none-eabihf
+          override: true
+      - uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: check
+          args: --target thumbv7em-none-eabihf
+
+  fmt:
+    name: Rustfmt
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - run: rustup component add rustfmt
+      - uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check
+
+  clippy:
+    name: Clippy
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          target: thumbv7em-none-eabihf
+          override: true
+      - run: rustup component add clippy
+      - uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target thumbv7em-none-eabihf -- -D warnings
+
+  ci:
+      if: ${{ success() }}
+      # all new jobs must be added to this list
+      needs: [check, fmt, clippy]
+      runs-on: ubuntu-latest
+      steps:
+        - name: CI succeeded
+          run: exit 0

va416xx/.gitignore

@@ -0,0 +1,2 @@
+/target
+Cargo.lock

va416xx/CHANGELOG.md

@@ -0,0 +1,21 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [unreleased]
+
+## [v0.1.1]
+
+- Clippy issue fixed by regenerating PAC with patched `svd2rust`:
+  https://github.com/rust-embedded/svd2rust/pull/558
+
+## [v0.1.0]
+
+- Clippy currently complains about unsound code which should still work.
+  Related issue: https://github.com/rust-embedded/svd2rust/issues/557
+  Clippy is disabled in CI/CD for now.
+- Initial release

va416xx/Cargo.toml

@@ -0,0 +1,24 @@
+[package]
+name = "va416xx"
+version = "0.1.1"
+authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
+edition = "2021"
+description = "PAC for the Vorago VA416xx family of MCUs"
+homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx"
+repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx"
+license = "Apache-2.0"
+keywords = ["no-std", "arm", "cortex-m", "vorago", "va416xx"]
+categories = ["embedded", "no-std", "hardware-support"]
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+cortex-m = "0.7"
+vcell = "0.1.3"
+
+[dependencies.cortex-m-rt]
+optional = true
+version = ">=0.6.15,<0.8"
+
+[features]
+rt = ["cortex-m-rt/device"]

va416xx/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+   "License" shall mean the terms and conditions for use, reproduction,
+   and distribution as defined by Sections 1 through 9 of this document.
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+   "You" (or "Your") shall mean an individual or Legal Entity
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+   form, that is based on (or derived from) the Work and for which the
+   editorial revisions, annotations, elaborations, or other modifications
+   represent, as a whole, an original work of authorship. For the purposes
+   of this License, Derivative Works shall not include works that remain
+   separable from, or merely link (or bind by name) to the interfaces of,
+   the Work and Derivative Works thereof.
+
+   "Contribution" shall mean any work of authorship, including
+   the original version of the Work and any modifications or additions
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+   on behalf of whom a Contribution has been received by Licensor and
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+2. Grant of Copyright License. Subject to the terms and conditions of
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+   meet the following conditions:
+
+   (a) You must give any other recipients of the Work or
+       Derivative Works a copy of this License; and
+
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+
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+
+5. Submission of Contributions. Unless You explicitly state otherwise,
+   any Contribution intentionally submitted for inclusion in the Work
+   by You to the Licensor shall be under the terms and conditions of
+   this License, without any additional terms or conditions.
+   Notwithstanding the above, nothing herein shall supersede or modify
+   the terms of any separate license agreement you may have executed
+   with Licensor regarding such Contributions.
+
+6. Trademarks. This License does not grant permission to use the trade
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+
+7. Disclaimer of Warranty. Unless required by applicable law or
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+   Contributor provides its Contributions) on an "AS IS" BASIS,
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+
+8. Limitation of Liability. In no event and under no legal theory,
+   whether in tort (including negligence), contract, or otherwise,
+   unless required by applicable law (such as deliberate and grossly
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+limitations under the License.

va416xx/NOTICE

@@ -0,0 +1,3 @@
+Rust Peripheral Access Crate (PAC) crate for the Vorago VA416xx family of MCUs
+
+This software contains code developed at the University of Stuttgart.

va416xx/README.md

@@ -0,0 +1,59 @@
+[![Crates.io](https://img.shields.io/crates/v/va416xx)](https://crates.io/crates/va416xx)
+[![build](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml)
+[![docs.rs](https://img.shields.io/docsrs/va416xx)](https://docs.rs/va416xx)
+
+# PAC for the Vorago VA416xx microcontroller family
+
+This repository contains the Peripheral Access Crate (PAC) for
+Voragos VA416xx series of Cortex-M4 based microcontrollers.
+
+The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
+
+## Usage
+
+To use this crate, add this to your `Cargo.toml`
+
+```toml
+[dependencies.va416xx]
+version = "<MostRecentVersion>"
+features = ["rt"]
+```
+
+The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
+
+For full details on the autgenerated API, you can read the
+[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/).
+
+## Regenerating the PAC
+
+If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes
+or the `svd2rust` version is updated, you can do some using the following these steps:
+
+1. Make sure all necessary tools are installed: [`svd2rust`](https://docs.rs/svd2rust/latest/svd2rust/),
+   [`svdtools`](https://github.com/rust-embedded/svdtools) and [`form`](https://crates.io/crates/form).
+   You can install all tools with `cargo`:
+
+   ```sh
+   cargo install --locked svd2rust svdtools form
+   ```
+
+2. Patch the vendor-provided SVD file `svd/va41xx.svd`. This can be done using `svdtools` in
+   conjunction with the `svd/va416xx-patch.yml` file.
+
+   ```sh
+   svdtools patch svd/va416xx-patch.yml
+   ```
+
+3. Use `svd2rust` to generate the Rust library
+
+   ```sh
+   svd2rust -i svd/va416xx.svd.patched
+   ```
+
+4. Use the `form` tool to split the generated `lib.rs` into individual modules.
+
+    ```sh
+    form -i lib.rs -o src/
+    ```
+
+The `gen-helper.sh` automates steps 2-4.

va416xx/automation/Dockerfile

@@ -0,0 +1,11 @@
+# Run the following commands from root directory to build and run locally
+# docker build -f automation/Dockerfile -t <NAME> .
+# docker run -it <NAME>
+FROM rust:latest
+RUN apt-get update
+RUN apt-get --yes upgrade
+# tzdata is a dependency, won't install otherwise
+ARG DEBIAN_FRONTEND=noninteractive
+
+RUN rustup target add thumbv7em-none-eabihf && \
+	rustup component add rustfmt clippy

va416xx/automation/Jenkinsfile

@@ -0,0 +1,39 @@
+pipeline {
+    agent any
+
+    stages {
+        stage('Clippy') {
+            agent {
+                dockerfile {
+                    dir 'automation'
+                    reuseNode true
+                }
+            }
+            steps {
+                sh 'cargo clippy'
+            }
+        }
+        stage('Rustfmt') {
+            agent {
+                dockerfile {
+                    dir 'automation'
+                    reuseNode true
+                }
+            }
+            steps {
+                sh 'cargo fmt'
+            }
+        }
+        stage('Check') {
+            agent {
+                dockerfile {
+                    dir 'automation'
+                    reuseNode true
+                }
+            }
+            steps {
+                sh 'cargo check --target thumbv7em-none-eabihf'
+            }
+        }
+    }
+}

va416xx/build.rs

@@ -0,0 +1,17 @@
+#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

va416xx/device.x

@@ -0,0 +1,197 @@
+PROVIDE(U0 = DefaultHandler);
+PROVIDE(U1 = DefaultHandler);
+PROVIDE(U2 = DefaultHandler);
+PROVIDE(U3 = DefaultHandler);
+PROVIDE(U4 = DefaultHandler);
+PROVIDE(U5 = DefaultHandler);
+PROVIDE(U6 = DefaultHandler);
+PROVIDE(U7 = DefaultHandler);
+PROVIDE(U8 = DefaultHandler);
+PROVIDE(U9 = DefaultHandler);
+PROVIDE(U10 = DefaultHandler);
+PROVIDE(U11 = DefaultHandler);
+PROVIDE(U12 = DefaultHandler);
+PROVIDE(U13 = DefaultHandler);
+PROVIDE(U14 = DefaultHandler);
+PROVIDE(U15 = DefaultHandler);
+PROVIDE(SPI0_TX = DefaultHandler);
+PROVIDE(SPI0_RX = DefaultHandler);
+PROVIDE(SPI1_TX = DefaultHandler);
+PROVIDE(SPI1_RX = DefaultHandler);
+PROVIDE(SPI2_TX = DefaultHandler);
+PROVIDE(SPI2_RX = DefaultHandler);
+PROVIDE(SPI3_TX = DefaultHandler);
+PROVIDE(SPI3_RX = DefaultHandler);
+PROVIDE(UART0_TX = DefaultHandler);
+PROVIDE(UART0_RX = DefaultHandler);
+PROVIDE(UART1_TX = DefaultHandler);
+PROVIDE(UART1_RX = DefaultHandler);
+PROVIDE(UART2_TX = DefaultHandler);
+PROVIDE(UART2_RX = DefaultHandler);
+PROVIDE(I2C0_MS = DefaultHandler);
+PROVIDE(I2C0_SL = DefaultHandler);
+PROVIDE(I2C1_MS = DefaultHandler);
+PROVIDE(I2C1_SL = DefaultHandler);
+PROVIDE(I2C2_MS = DefaultHandler);
+PROVIDE(I2C2_SL = DefaultHandler);
+PROVIDE(Ethernet = DefaultHandler);
+PROVIDE(U37 = DefaultHandler);
+PROVIDE(SpW = DefaultHandler);
+PROVIDE(U39 = DefaultHandler);
+PROVIDE(DAC0 = DefaultHandler);
+PROVIDE(DAC1 = DefaultHandler);
+PROVIDE(TRNG = DefaultHandler);
+PROVIDE(DMA_ERROR = DefaultHandler);
+PROVIDE(ADC = DefaultHandler);
+PROVIDE(LoCLK = DefaultHandler);
+PROVIDE(LVD = DefaultHandler);
+PROVIDE(WATCHDOG = DefaultHandler);
+PROVIDE(TIM0 = DefaultHandler);
+PROVIDE(TIM1 = DefaultHandler);
+PROVIDE(TIM2 = DefaultHandler);
+PROVIDE(TIM3 = DefaultHandler);
+PROVIDE(TIM4 = DefaultHandler);
+PROVIDE(TIM5 = DefaultHandler);
+PROVIDE(TIM6 = DefaultHandler);
+PROVIDE(TIM7 = DefaultHandler);
+PROVIDE(TIM8 = DefaultHandler);
+PROVIDE(TIM9 = DefaultHandler);
+PROVIDE(TIM10 = DefaultHandler);
+PROVIDE(TIM11 = DefaultHandler);
+PROVIDE(TIM12 = DefaultHandler);
+PROVIDE(TIM13 = DefaultHandler);
+PROVIDE(TIM14 = DefaultHandler);
+PROVIDE(TIM15 = DefaultHandler);
+PROVIDE(TIM16 = DefaultHandler);
+PROVIDE(TIM17 = DefaultHandler);
+PROVIDE(TIM18 = DefaultHandler);
+PROVIDE(TIM19 = DefaultHandler);
+PROVIDE(TIM20 = DefaultHandler);
+PROVIDE(TIM21 = DefaultHandler);
+PROVIDE(TIM22 = DefaultHandler);
+PROVIDE(TIM23 = DefaultHandler);
+PROVIDE(CAN0 = DefaultHandler);
+PROVIDE(U73 = DefaultHandler);
+PROVIDE(CAN1 = DefaultHandler);
+PROVIDE(U75 = DefaultHandler);
+PROVIDE(EDAC_MBE = DefaultHandler);
+PROVIDE(EDAC_SBE = DefaultHandler);
+PROVIDE(PORTA0 = DefaultHandler);
+PROVIDE(PORTA1 = DefaultHandler);
+PROVIDE(PORTA2 = DefaultHandler);
+PROVIDE(PORTA3 = DefaultHandler);
+PROVIDE(PORTA4 = DefaultHandler);
+PROVIDE(PORTA5 = DefaultHandler);
+PROVIDE(PORTA6 = DefaultHandler);
+PROVIDE(PORTA7 = DefaultHandler);
+PROVIDE(PORTA8 = DefaultHandler);
+PROVIDE(PORTA9 = DefaultHandler);
+PROVIDE(PORTA10 = DefaultHandler);
+PROVIDE(PORTA11 = DefaultHandler);
+PROVIDE(PORTA12 = DefaultHandler);
+PROVIDE(PORTA13 = DefaultHandler);
+PROVIDE(PORTA14 = DefaultHandler);
+PROVIDE(PORTA15 = DefaultHandler);
+PROVIDE(PORTB0 = DefaultHandler);
+PROVIDE(PORTB1 = DefaultHandler);
+PROVIDE(PORTB2 = DefaultHandler);
+PROVIDE(PORTB3 = DefaultHandler);
+PROVIDE(PORTB4 = DefaultHandler);
+PROVIDE(PORTB5 = DefaultHandler);
+PROVIDE(PORTB6 = DefaultHandler);
+PROVIDE(PORTB7 = DefaultHandler);
+PROVIDE(PORTB8 = DefaultHandler);
+PROVIDE(PORTB9 = DefaultHandler);
+PROVIDE(PORTB10 = DefaultHandler);
+PROVIDE(PORTB11 = DefaultHandler);
+PROVIDE(PORTB12 = DefaultHandler);
+PROVIDE(PORTB13 = DefaultHandler);
+PROVIDE(PORTB14 = DefaultHandler);
+PROVIDE(PORTB15 = DefaultHandler);
+PROVIDE(PORTC0 = DefaultHandler);
+PROVIDE(PORTC1 = DefaultHandler);
+PROVIDE(PORTC2 = DefaultHandler);
+PROVIDE(PORTC3 = DefaultHandler);
+PROVIDE(PORTC4 = DefaultHandler);
+PROVIDE(PORTC5 = DefaultHandler);
+PROVIDE(PORTC6 = DefaultHandler);
+PROVIDE(PORTC7 = DefaultHandler);
+PROVIDE(PORTC8 = DefaultHandler);
+PROVIDE(PORTC9 = DefaultHandler);
+PROVIDE(PORTC10 = DefaultHandler);
+PROVIDE(PORTC11 = DefaultHandler);
+PROVIDE(PORTC12 = DefaultHandler);
+PROVIDE(PORTC13 = DefaultHandler);
+PROVIDE(PORTC14 = DefaultHandler);
+PROVIDE(PORTC15 = DefaultHandler);
+PROVIDE(PORTD0 = DefaultHandler);
+PROVIDE(PORTD1 = DefaultHandler);
+PROVIDE(PORTD2 = DefaultHandler);
+PROVIDE(PORTD3 = DefaultHandler);
+PROVIDE(PORTD4 = DefaultHandler);
+PROVIDE(PORTD5 = DefaultHandler);
+PROVIDE(PORTD6 = DefaultHandler);
+PROVIDE(PORTD7 = DefaultHandler);
+PROVIDE(PORTD8 = DefaultHandler);
+PROVIDE(PORTD9 = DefaultHandler);
+PROVIDE(PORTD10 = DefaultHandler);
+PROVIDE(PORTD11 = DefaultHandler);
+PROVIDE(PORTD12 = DefaultHandler);
+PROVIDE(PORTD13 = DefaultHandler);
+PROVIDE(PORTD14 = DefaultHandler);
+PROVIDE(PORTD15 = DefaultHandler);
+PROVIDE(PORTE0 = DefaultHandler);
+PROVIDE(PORTE1 = DefaultHandler);
+PROVIDE(PORTE2 = DefaultHandler);
+PROVIDE(PORTE3 = DefaultHandler);
+PROVIDE(PORTE4 = DefaultHandler);
+PROVIDE(PORTE5 = DefaultHandler);
+PROVIDE(PORTE6 = DefaultHandler);
+PROVIDE(PORTE7 = DefaultHandler);
+PROVIDE(PORTE8 = DefaultHandler);
+PROVIDE(PORTE9 = DefaultHandler);
+PROVIDE(PORTE10 = DefaultHandler);
+PROVIDE(PORTE11 = DefaultHandler);
+PROVIDE(PORTE12 = DefaultHandler);
+PROVIDE(PORTE13 = DefaultHandler);
+PROVIDE(PORTE14 = DefaultHandler);
+PROVIDE(PORTE15 = DefaultHandler);
+PROVIDE(PORTF0 = DefaultHandler);
+PROVIDE(PORTF1 = DefaultHandler);
+PROVIDE(PORTF2 = DefaultHandler);
+PROVIDE(PORTF3 = DefaultHandler);
+PROVIDE(PORTF4 = DefaultHandler);
+PROVIDE(PORTF5 = DefaultHandler);
+PROVIDE(PORTF6 = DefaultHandler);
+PROVIDE(PORTF7 = DefaultHandler);
+PROVIDE(PORTF8 = DefaultHandler);
+PROVIDE(PORTF9 = DefaultHandler);
+PROVIDE(PORTF10 = DefaultHandler);
+PROVIDE(PORTF11 = DefaultHandler);
+PROVIDE(PORTF12 = DefaultHandler);
+PROVIDE(PORTF13 = DefaultHandler);
+PROVIDE(PORTF14 = DefaultHandler);
+PROVIDE(PORTF15 = DefaultHandler);
+PROVIDE(DMA_ACTIVE0 = DefaultHandler);
+PROVIDE(DMA_ACTIVE1 = DefaultHandler);
+PROVIDE(DMA_ACTIVE2 = DefaultHandler);
+PROVIDE(DMA_ACTIVE3 = DefaultHandler);
+PROVIDE(DMA_DONE0 = DefaultHandler);
+PROVIDE(DMA_DONE1 = DefaultHandler);
+PROVIDE(DMA_DONE2 = DefaultHandler);
+PROVIDE(DMA_DONE3 = DefaultHandler);
+PROVIDE(I2C0_MS_RX = DefaultHandler);
+PROVIDE(I2C0_MS_TX = DefaultHandler);
+PROVIDE(I2C0_SL_RX = DefaultHandler);
+PROVIDE(I2C0_SL_TX = DefaultHandler);
+PROVIDE(I2C1_MS_RX = DefaultHandler);
+PROVIDE(I2C1_MS_TX = DefaultHandler);
+PROVIDE(I2C1_SL_RX = DefaultHandler);
+PROVIDE(I2C1_SL_TX = DefaultHandler);
+PROVIDE(I2C2_MS_RX = DefaultHandler);
+PROVIDE(I2C2_MS_TX = DefaultHandler);
+PROVIDE(I2C2_SL_RX = DefaultHandler);
+PROVIDE(I2C2_SL_TX = DefaultHandler);
+PROVIDE(FPU = DefaultHandler);
+PROVIDE(TXEV = DefaultHandler);
+

va416xx/gen-helper.sh

@@ -0,0 +1,42 @@
+#!/bin/sh
+
+# Use installed tool by default
+svd2rust_bin="svd2rust"
+# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/
+if [ -f svd2rust ]; then
+	# If the local directory contains svd2rust, use that version instead
+	svd2rust_bin="./svd2rust"
+elif [ -f ../svd2rust ]; then
+	# Keeps the repository clean
+	svd2rust_bin="../svd2rust"
+fi
+if [ -x "$(${svd2rust_bin} --version)" ]; then
+	echo "No svd2rust found locally or installed." \
+		"Install it with cargo install svd2rust"
+	exit
+fi
+
+if ! command -v form &> /dev/null
+then
+    echo "form tool was not found"
+    exit 1
+fi
+
+if ! command -v svdtools &> /dev/null
+then
+    echo "svdtools was not found"
+    exit 1
+fi
+
+svdtools patch svd/va416xx-patch.yml
+${svd2rust_bin} -i svd/va416xx.svd.patched
+
+result=$?
+if [ $result -ne 0 ]; then
+  echo "svd2rust failed with code $result"
+  exit
+fi
+
+rm -rf src
+form -i lib.rs -o src/ && rm lib.rs
+cargo fmt

va416xx/src/adc.rs

@@ -0,0 +1,127 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    ctrl: Ctrl,
+    fifo_data: FifoData,
+    status: Status,
+    irq_enb: IrqEnb,
+    irq_raw: IrqRaw,
+    irq_end: IrqEnd,
+    irq_clr: IrqClr,
+    rxfifoirqtrg: Rxfifoirqtrg,
+    fifo_clr: FifoClr,
+    _reserved9: [u8; 0x0fd8],
+    perid: Perid,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Control Register"]
+    #[inline(always)]
+    pub const fn ctrl(&self) -> &Ctrl {
+        &self.ctrl
+    }
+    #[doc = "0x04 - FIFO data"]
+    #[inline(always)]
+    pub const fn fifo_data(&self) -> &FifoData {
+        &self.fifo_data
+    }
+    #[doc = "0x08 - Status"]
+    #[inline(always)]
+    pub const fn status(&self) -> &Status {
+        &self.status
+    }
+    #[doc = "0x0c - Interrupt Enable"]
+    #[inline(always)]
+    pub const fn irq_enb(&self) -> &IrqEnb {
+        &self.irq_enb
+    }
+    #[doc = "0x10 - Raw Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_raw(&self) -> &IrqRaw {
+        &self.irq_raw
+    }
+    #[doc = "0x14 - Enabled Interrupt Status"]
+    #[inline(always)]
+    pub const fn irq_end(&self) -> &IrqEnd {
+        &self.irq_end
+    }
+    #[doc = "0x18 - Clear Interrupt"]
+    #[inline(always)]
+    pub const fn irq_clr(&self) -> &IrqClr {
+        &self.irq_clr
+    }
+    #[doc = "0x1c - Receive FIFO Interrupt Trigger Value"]
+    #[inline(always)]
+    pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg {
+        &self.rxfifoirqtrg
+    }
+    #[doc = "0x20 - FIFO Clear"]
+    #[inline(always)]
+    pub const fn fifo_clr(&self) -> &FifoClr {
+        &self.fifo_clr
+    }
+    #[doc = "0xffc - Peripheral ID Register"]
+    #[inline(always)]
+    pub const fn perid(&self) -> &Perid {
+        &self.perid
+    }
+}
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+module"]
+#[doc(alias = "CTRL")]
+pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
+#[doc = "Control Register"]
+pub mod ctrl;
+#[doc = "FIFO_DATA (r) register accessor: FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`]
+module"]
+#[doc(alias = "FIFO_DATA")]
+pub type FifoData = crate::Reg<fifo_data::FifoDataSpec>;
+#[doc = "FIFO data"]
+pub mod fifo_data;
+#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+module"]
+#[doc(alias = "STATUS")]
+pub type Status = crate::Reg<status::StatusSpec>;
+#[doc = "Status"]
+pub mod status;
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+module"]
+#[doc(alias = "IRQ_ENB")]
+pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
+#[doc = "Interrupt Enable"]
+pub mod irq_enb;
+#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
+module"]
+#[doc(alias = "IRQ_RAW")]
+pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
+#[doc = "Raw Interrupt Status"]
+pub mod irq_raw;
+#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
+module"]
+#[doc(alias = "IRQ_END")]
+pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
+#[doc = "Enabled Interrupt Status"]
+pub mod irq_end;
+#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`]
+module"]
+#[doc(alias = "IRQ_CLR")]
+pub type IrqClr = crate::Reg<irq_clr::IrqClrSpec>;
+#[doc = "Clear Interrupt"]
+pub mod irq_clr;
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+module"]
+#[doc(alias = "RXFIFOIRQTRG")]
+pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
+#[doc = "Receive FIFO Interrupt Trigger Value"]
+pub mod rxfifoirqtrg;
+#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+module"]
+#[doc(alias = "FIFO_CLR")]
+pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
+#[doc = "FIFO Clear"]
+pub mod fifo_clr;
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+module"]
+#[doc(alias = "PERID")]
+pub type Perid = crate::Reg<perid::PeridSpec>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

va416xx/src/adc/ctrl.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CtrlSpec>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CtrlSpec>;
+#[doc = "Field `CHAN_EN` reader - Enables the channel for data collection"]
+pub type ChanEnR = crate::FieldReader<u16>;
+#[doc = "Field `CHAN_EN` writer - Enables the channel for data collection"]
+pub type ChanEnW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `CHAN_TAG_EN` reader - Enables the channel tag to be saved with the ADC data"]
+pub type ChanTagEnR = crate::BitReader;
+#[doc = "Field `CHAN_TAG_EN` writer - Enables the channel tag to be saved with the ADC data"]
+pub type ChanTagEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWEEP_EN` reader - ADC data acquisition for all enabled channel"]
+pub type SweepEnR = crate::BitReader;
+#[doc = "Field `SWEEP_EN` writer - ADC data acquisition for all enabled channel"]
+pub type SweepEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXT_TRIG_EN` reader - Allows the external trigger to start analog acquisition"]
+pub type ExtTrigEnR = crate::BitReader;
+#[doc = "Field `EXT_TRIG_EN` writer - Allows the external trigger to start analog acquisition"]
+pub type ExtTrigEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MANUAL_TRIG` reader - Starts analog acquisition"]
+pub type ManualTrigR = crate::BitReader;
+#[doc = "Field `MANUAL_TRIG` writer - Starts analog acquisition"]
+pub type ManualTrigW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CONV_CNT` reader - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+pub type ConvCntR = crate::FieldReader;
+#[doc = "Field `CONV_CNT` writer - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+pub type ConvCntW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:15 - Enables the channel for data collection"]
+    #[inline(always)]
+    pub fn chan_en(&self) -> ChanEnR {
+        ChanEnR::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"]
+    #[inline(always)]
+    pub fn chan_tag_en(&self) -> ChanTagEnR {
+        ChanTagEnR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - ADC data acquisition for all enabled channel"]
+    #[inline(always)]
+    pub fn sweep_en(&self) -> SweepEnR {
+        SweepEnR::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"]
+    #[inline(always)]
+    pub fn ext_trig_en(&self) -> ExtTrigEnR {
+        ExtTrigEnR::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Starts analog acquisition"]
+    #[inline(always)]
+    pub fn manual_trig(&self) -> ManualTrigR {
+        ManualTrigR::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+    #[inline(always)]
+    pub fn conv_cnt(&self) -> ConvCntR {
+        ConvCntR::new(((self.bits >> 20) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Enables the channel for data collection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn chan_en(&mut self) -> ChanEnW<CtrlSpec> {
+        ChanEnW::new(self, 0)
+    }
+    #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"]
+    #[inline(always)]
+    #[must_use]
+    pub fn chan_tag_en(&mut self) -> ChanTagEnW<CtrlSpec> {
+        ChanTagEnW::new(self, 16)
+    }
+    #[doc = "Bit 17 - ADC data acquisition for all enabled channel"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sweep_en(&mut self) -> SweepEnW<CtrlSpec> {
+        SweepEnW::new(self, 17)
+    }
+    #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ext_trig_en(&mut self) -> ExtTrigEnW<CtrlSpec> {
+        ExtTrigEnW::new(self, 18)
+    }
+    #[doc = "Bit 19 - Starts analog acquisition"]
+    #[inline(always)]
+    #[must_use]
+    pub fn manual_trig(&mut self) -> ManualTrigW<CtrlSpec> {
+        ManualTrigW::new(self, 19)
+    }
+    #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn conv_cnt(&mut self) -> ConvCntW<CtrlSpec> {
+        ConvCntW::new(self, 20)
+    }
+}
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlSpec;
+impl crate::RegisterSpec for CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/fifo_clr.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `FIFO_CLR` reader"]
+pub type R = crate::R<FifoClrSpec>;
+#[doc = "Register `FIFO_CLR` writer"]
+pub type W = crate::W<FifoClrSpec>;
+#[doc = "Field `FIFO_CLR` writer - Clears the ADC FIFO. Always reads 0"]
+pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clears the ADC FIFO. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_clr(&mut self) -> FifoClrW<FifoClrSpec> {
+        FifoClrW::new(self, 0)
+    }
+}
+#[doc = "FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoClrSpec;
+impl crate::RegisterSpec for FifoClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fifo_clr::R`](R) reader structure"]
+impl crate::Readable for FifoClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
+impl crate::Writable for FifoClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIFO_CLR to value 0"]
+impl crate::Resettable for FifoClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/fifo_data.rs

@@ -0,0 +1,29 @@
+#[doc = "Register `FIFO_DATA` reader"]
+pub type R = crate::R<FifoDataSpec>;
+#[doc = "Field `ADC_DATA` reader - ADC acquisition data from the FIFO"]
+pub type AdcDataR = crate::FieldReader<u16>;
+#[doc = "Field `CHAN_TAG` reader - If enabled, this will include the number of the channel corresponding to the measurement"]
+pub type ChanTagR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:11 - ADC acquisition data from the FIFO"]
+    #[inline(always)]
+    pub fn adc_data(&self) -> AdcDataR {
+        AdcDataR::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 12:15 - If enabled, this will include the number of the channel corresponding to the measurement"]
+    #[inline(always)]
+    pub fn chan_tag(&self) -> ChanTagR {
+        ChanTagR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+#[doc = "FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoDataSpec;
+impl crate::RegisterSpec for FifoDataSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fifo_data::R`](R) reader structure"]
+impl crate::Readable for FifoDataSpec {}
+#[doc = "`reset()` method sets FIFO_DATA to value 0"]
+impl crate::Resettable for FifoDataSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_clr.rs

@@ -0,0 +1,51 @@
+#[doc = "Register `IRQ_CLR` writer"]
+pub type W = crate::W<IrqClrSpec>;
+#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"]
+pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"]
+pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC_DONE` writer - Clears the ADC done interrupt status. Always reads 0"]
+pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"]
+pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqClrSpec> {
+        FifoOflowW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqClrSpec> {
+        FifoUflowW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn adc_done(&mut self) -> AdcDoneW<IrqClrSpec> {
+        AdcDoneW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn trig_error(&mut self) -> TrigErrorW<IrqClrSpec> {
+        TrigErrorW::new(self, 3)
+    }
+}
+#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqClrSpec;
+impl crate::RegisterSpec for IrqClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`irq_clr::W`](W) writer structure"]
+impl crate::Writable for IrqClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_CLR to value 0"]
+impl crate::Resettable for IrqClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_enb.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"]
+pub type FifoEmptyR = crate::BitReader;
+#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"]
+pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"]
+pub type FifoFullR = crate::BitReader;
+#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"]
+pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"]
+pub type FifoOflowR = crate::BitReader;
+#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"]
+pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"]
+pub type FifoUflowR = crate::BitReader;
+#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"]
+pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"]
+pub type AdcDoneR = crate::BitReader;
+#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"]
+pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"]
+pub type TrigErrorR = crate::BitReader;
+#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"]
+pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigR = crate::BitReader;
+#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FifoEmptyR {
+        FifoEmptyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enables the interrupt for FIFO full"]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FifoFullR {
+        FifoFullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
+    #[inline(always)]
+    pub fn fifo_oflow(&self) -> FifoOflowR {
+        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
+    #[inline(always)]
+    pub fn fifo_uflow(&self) -> FifoUflowR {
+        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
+    #[inline(always)]
+    pub fn adc_done(&self) -> AdcDoneR {
+        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Enables the interrupt for a trigger error"]
+    #[inline(always)]
+    pub fn trig_error(&self) -> TrigErrorR {
+        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
+        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_empty(&mut self) -> FifoEmptyW<IrqEnbSpec> {
+        FifoEmptyW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Enables the interrupt for FIFO full"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_full(&mut self) -> FifoFullW<IrqEnbSpec> {
+        FifoFullW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqEnbSpec> {
+        FifoOflowW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqEnbSpec> {
+        FifoUflowW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
+    #[inline(always)]
+    #[must_use]
+    pub fn adc_done(&mut self) -> AdcDoneW<IrqEnbSpec> {
+        AdcDoneW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Enables the interrupt for a trigger error"]
+    #[inline(always)]
+    #[must_use]
+    pub fn trig_error(&mut self) -> TrigErrorW<IrqEnbSpec> {
+        TrigErrorW::new(self, 5)
+    }
+    #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<IrqEnbSpec> {
+        FifoDepthTrigW::new(self, 6)
+    }
+}
+#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_end.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_END` reader"]
+pub type R = crate::R<IrqEndSpec>;
+#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"]
+pub type FifoEmptyR = crate::BitReader;
+#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"]
+pub type FifoFullR = crate::BitReader;
+#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"]
+pub type FifoOflowR = crate::BitReader;
+#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"]
+pub type FifoUflowR = crate::BitReader;
+#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done and the interrupt is enabled"]
+pub type AdcDoneR = crate::BitReader;
+#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"]
+pub type TrigErrorR = crate::BitReader;
+#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FifoEmptyR {
+        FifoEmptyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FifoFullR {
+        FifoFullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_oflow(&self) -> FifoOflowR {
+        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_uflow(&self) -> FifoUflowR {
+        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Indicates that a ADC conversion is done and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn adc_done(&self) -> AdcDoneR {
+        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn trig_error(&self) -> TrigErrorR {
+        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
+        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEndSpec;
+impl crate::RegisterSpec for IrqEndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
+impl crate::Readable for IrqEndSpec {}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IrqEndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_raw.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub type R = crate::R<IrqRawSpec>;
+#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"]
+pub type FifoEmptyR = crate::BitReader;
+#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"]
+pub type FifoFullR = crate::BitReader;
+#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"]
+pub type FifoOflowR = crate::BitReader;
+#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for ADC update is received"]
+pub type FifoUflowR = crate::BitReader;
+#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done"]
+pub type AdcDoneR = crate::BitReader;
+#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"]
+pub type TrigErrorR = crate::BitReader;
+#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Indicates the FIFO is empty"]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FifoEmptyR {
+        FifoEmptyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Indicates the FIFO is full"]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FifoFullR {
+        FifoFullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"]
+    #[inline(always)]
+    pub fn fifo_oflow(&self) -> FifoOflowR {
+        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for ADC update is received"]
+    #[inline(always)]
+    pub fn fifo_uflow(&self) -> FifoUflowR {
+        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Indicates that a ADC conversion is done"]
+    #[inline(always)]
+    pub fn adc_done(&self) -> AdcDoneR {
+        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"]
+    #[inline(always)]
+    pub fn trig_error(&self) -> TrigErrorR {
+        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
+        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqRawSpec;
+impl crate::RegisterSpec for IrqRawSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
+impl crate::Readable for IrqRawSpec {}
+#[doc = "`reset()` method sets IRQ_RAW to value 0x01"]
+impl crate::Resettable for IrqRawSpec {
+    const RESET_VALUE: u32 = 0x01;
+}

va416xx/src/adc/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0019_07e9"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0019_07e9;
+}

va416xx/src/adc/rxfifoirqtrg.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `RXFIFOIRQTRG` reader"]
+pub type R = crate::R<RxfifoirqtrgSpec>;
+#[doc = "Register `RXFIFOIRQTRG` writer"]
+pub type W = crate::W<RxfifoirqtrgSpec>;
+#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+pub type LevelR = crate::FieldReader;
+#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+    #[inline(always)]
+    pub fn level(&self) -> LevelR {
+        LevelR::new((self.bits & 0x1f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn level(&mut self) -> LevelW<RxfifoirqtrgSpec> {
+        LevelW::new(self, 0)
+    }
+}
+#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxfifoirqtrgSpec;
+impl crate::RegisterSpec for RxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for RxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for RxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0x10"]
+impl crate::Resettable for RxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0x10;
+}

va416xx/src/adc/status.rs

@@ -0,0 +1,29 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<StatusSpec>;
+#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"]
+pub type FifoEntryCntR = crate::FieldReader;
+#[doc = "Field `ADC_BUSY` reader - Indicates an ADC data acquisition is in process"]
+pub type AdcBusyR = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"]
+    #[inline(always)]
+    pub fn fifo_entry_cnt(&self) -> FifoEntryCntR {
+        FifoEntryCntR::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bit 7 - Indicates an ADC data acquisition is in process"]
+    #[inline(always)]
+    pub fn adc_busy(&self) -> AdcBusyR {
+        AdcBusyR::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StatusSpec;
+impl crate::RegisterSpec for StatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for StatusSpec {}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for StatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/bmskb.rs

@@ -0,0 +1,105 @@
+#[doc = "Register `BMSKB` reader"]
+pub type R = crate::R<BmskbSpec>;
+#[doc = "Register `BMSKB` writer"]
+pub type W = crate::W<BmskbSpec>;
+#[doc = "Field `BM0` reader - BM\\[17:15\\]
+- Unused in standard, ID\\[17:15\\]
+in extended"]
+pub type Bm0R = crate::FieldReader;
+#[doc = "Field `BM0` writer - BM\\[17:15\\]
+- Unused in standard, ID\\[17:15\\]
+in extended"]
+pub type Bm0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `IDE` reader - Identifier Extension Bit"]
+pub type IdeR = crate::BitReader;
+#[doc = "Field `IDE` writer - Identifier Extension Bit"]
+pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"]
+pub type RtrR = crate::BitReader;
+#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"]
+pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BM1` reader - BM\\[28:18\\]
+- ID\\[10:0\\]
+in standard, ID\\[28:18\\]
+in extended"]
+pub type Bm1R = crate::FieldReader<u16>;
+#[doc = "Field `BM1` writer - BM\\[28:18\\]
+- ID\\[10:0\\]
+in standard, ID\\[28:18\\]
+in extended"]
+pub type Bm1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+impl R {
+    #[doc = "Bits 0:2 - BM\\[17:15\\]
+- Unused in standard, ID\\[17:15\\]
+in extended"]
+    #[inline(always)]
+    pub fn bm0(&self) -> Bm0R {
+        Bm0R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - Identifier Extension Bit"]
+    #[inline(always)]
+    pub fn ide(&self) -> IdeR {
+        IdeR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"]
+    #[inline(always)]
+    pub fn rtr(&self) -> RtrR {
+        RtrR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:15 - BM\\[28:18\\]
+- ID\\[10:0\\]
+in standard, ID\\[28:18\\]
+in extended"]
+    #[inline(always)]
+    pub fn bm1(&self) -> Bm1R {
+        Bm1R::new(((self.bits >> 5) & 0x07ff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - BM\\[17:15\\]
+- Unused in standard, ID\\[17:15\\]
+in extended"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bm0(&mut self) -> Bm0W<BmskbSpec> {
+        Bm0W::new(self, 0)
+    }
+    #[doc = "Bit 3 - Identifier Extension Bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ide(&mut self) -> IdeW<BmskbSpec> {
+        IdeW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rtr(&mut self) -> RtrW<BmskbSpec> {
+        RtrW::new(self, 4)
+    }
+    #[doc = "Bits 5:15 - BM\\[28:18\\]
+- ID\\[10:0\\]
+in standard, ID\\[28:18\\]
+in extended"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bm1(&mut self) -> Bm1W<BmskbSpec> {
+        Bm1W::new(self, 5)
+    }
+}
+#[doc = "CAN Basic Mask Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmskb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BmskbSpec;
+impl crate::RegisterSpec for BmskbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bmskb::R`](R) reader structure"]
+impl crate::Readable for BmskbSpec {}
+#[doc = "`write(|w| ..)` method takes [`bmskb::W`](W) writer structure"]
+impl crate::Writable for BmskbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BMSKB to value 0"]
+impl crate::Resettable for BmskbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/bmskx.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `BMSKX` reader"]
+pub type R = crate::R<BmskxSpec>;
+#[doc = "Register `BMSKX` writer"]
+pub type W = crate::W<BmskxSpec>;
+#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"]
+pub type XrtrR = crate::BitReader;
+#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"]
+pub type XrtrW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BM` reader - BM\\[14:0\\]
+used when an extended frame is received. ID\\[14:0\\]
+in extended, unused standard"]
+pub type BmR = crate::FieldReader<u16>;
+#[doc = "Field `BM` writer - BM\\[14:0\\]
+used when an extended frame is received. ID\\[14:0\\]
+in extended, unused standard"]
+pub type BmW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+impl R {
+    #[doc = "Bit 0 - Extended Remote transmission Request Bit"]
+    #[inline(always)]
+    pub fn xrtr(&self) -> XrtrR {
+        XrtrR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:15 - BM\\[14:0\\]
+used when an extended frame is received. ID\\[14:0\\]
+in extended, unused standard"]
+    #[inline(always)]
+    pub fn bm(&self) -> BmR {
+        BmR::new(((self.bits >> 1) & 0x7fff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Extended Remote transmission Request Bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn xrtr(&mut self) -> XrtrW<BmskxSpec> {
+        XrtrW::new(self, 0)
+    }
+    #[doc = "Bits 1:15 - BM\\[14:0\\]
+used when an extended frame is received. ID\\[14:0\\]
+in extended, unused standard"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bm(&mut self) -> BmW<BmskxSpec> {
+        BmW::new(self, 1)
+    }
+}
+#[doc = "CAN Basic Mask Extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmskx::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmskx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BmskxSpec;
+impl crate::RegisterSpec for BmskxSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bmskx::R`](R) reader structure"]
+impl crate::Readable for BmskxSpec {}
+#[doc = "`write(|w| ..)` method takes [`bmskx::W`](W) writer structure"]
+impl crate::Writable for BmskxSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BMSKX to value 0"]
+impl crate::Resettable for BmskxSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/canec.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CANEC` reader"]
+pub type R = crate::R<CanecSpec>;
+#[doc = "Register `CANEC` writer"]
+pub type W = crate::W<CanecSpec>;
+#[doc = "Field `TEC` reader - Transmit Error Counter"]
+pub type TecR = crate::FieldReader;
+#[doc = "Field `TEC` writer - Transmit Error Counter"]
+pub type TecW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `REC` reader - Receive Error Counter"]
+pub type RecR = crate::FieldReader;
+#[doc = "Field `REC` writer - Receive Error Counter"]
+pub type RecW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Transmit Error Counter"]
+    #[inline(always)]
+    pub fn tec(&self) -> TecR {
+        TecR::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Receive Error Counter"]
+    #[inline(always)]
+    pub fn rec(&self) -> RecR {
+        RecR::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Transmit Error Counter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tec(&mut self) -> TecW<CanecSpec> {
+        TecW::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Receive Error Counter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rec(&mut self) -> RecW<CanecSpec> {
+        RecW::new(self, 8)
+    }
+}
+#[doc = "CAN Error Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`canec::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`canec::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CanecSpec;
+impl crate::RegisterSpec for CanecSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`canec::R`](R) reader structure"]
+impl crate::Readable for CanecSpec {}
+#[doc = "`write(|w| ..)` method takes [`canec::W`](W) writer structure"]
+impl crate::Writable for CanecSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CANEC to value 0"]
+impl crate::Resettable for CanecSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cediag.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `CEDIAG` reader"]
+pub type R = crate::R<CediagSpec>;
+#[doc = "Register `CEDIAG` writer"]
+pub type W = crate::W<CediagSpec>;
+#[doc = "Field `EFID` reader - Error Field Identifier"]
+pub type EfidR = crate::FieldReader;
+#[doc = "Field `EFID` writer - Error Field Identifier"]
+pub type EfidW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `EBID` reader - Error Bit Identifier"]
+pub type EbidR = crate::FieldReader;
+#[doc = "Field `EBID` writer - Error Bit Identifier"]
+pub type EbidW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `TXE` reader - Transmit Error"]
+pub type TxeR = crate::BitReader;
+#[doc = "Field `TXE` writer - Transmit Error"]
+pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `STUFF` reader - Stuff Error"]
+pub type StuffR = crate::BitReader;
+#[doc = "Field `STUFF` writer - Stuff Error"]
+pub type StuffW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRC` reader - CRC"]
+pub type CrcR = crate::BitReader;
+#[doc = "Field `CRC` writer - CRC"]
+pub type CrcW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MON` reader - Monitor"]
+pub type MonR = crate::BitReader;
+#[doc = "Field `MON` writer - Monitor"]
+pub type MonW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DRIVE` reader - Drive"]
+pub type DriveR = crate::BitReader;
+#[doc = "Field `DRIVE` writer - Drive"]
+pub type DriveW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:3 - Error Field Identifier"]
+    #[inline(always)]
+    pub fn efid(&self) -> EfidR {
+        EfidR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:9 - Error Bit Identifier"]
+    #[inline(always)]
+    pub fn ebid(&self) -> EbidR {
+        EbidR::new(((self.bits >> 4) & 0x3f) as u8)
+    }
+    #[doc = "Bit 10 - Transmit Error"]
+    #[inline(always)]
+    pub fn txe(&self) -> TxeR {
+        TxeR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Stuff Error"]
+    #[inline(always)]
+    pub fn stuff(&self) -> StuffR {
+        StuffR::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - CRC"]
+    #[inline(always)]
+    pub fn crc(&self) -> CrcR {
+        CrcR::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Monitor"]
+    #[inline(always)]
+    pub fn mon(&self) -> MonR {
+        MonR::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - Drive"]
+    #[inline(always)]
+    pub fn drive(&self) -> DriveR {
+        DriveR::new(((self.bits >> 14) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Error Field Identifier"]
+    #[inline(always)]
+    #[must_use]
+    pub fn efid(&mut self) -> EfidW<CediagSpec> {
+        EfidW::new(self, 0)
+    }
+    #[doc = "Bits 4:9 - Error Bit Identifier"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ebid(&mut self) -> EbidW<CediagSpec> {
+        EbidW::new(self, 4)
+    }
+    #[doc = "Bit 10 - Transmit Error"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txe(&mut self) -> TxeW<CediagSpec> {
+        TxeW::new(self, 10)
+    }
+    #[doc = "Bit 11 - Stuff Error"]
+    #[inline(always)]
+    #[must_use]
+    pub fn stuff(&mut self) -> StuffW<CediagSpec> {
+        StuffW::new(self, 11)
+    }
+    #[doc = "Bit 12 - CRC"]
+    #[inline(always)]
+    #[must_use]
+    pub fn crc(&mut self) -> CrcW<CediagSpec> {
+        CrcW::new(self, 12)
+    }
+    #[doc = "Bit 13 - Monitor"]
+    #[inline(always)]
+    #[must_use]
+    pub fn mon(&mut self) -> MonW<CediagSpec> {
+        MonW::new(self, 13)
+    }
+    #[doc = "Bit 14 - Drive"]
+    #[inline(always)]
+    #[must_use]
+    pub fn drive(&mut self) -> DriveW<CediagSpec> {
+        DriveW::new(self, 14)
+    }
+}
+#[doc = "CAN Error Diagnostic Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cediag::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cediag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CediagSpec;
+impl crate::RegisterSpec for CediagSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cediag::R`](R) reader structure"]
+impl crate::Readable for CediagSpec {}
+#[doc = "`write(|w| ..)` method takes [`cediag::W`](W) writer structure"]
+impl crate::Writable for CediagSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CEDIAG to value 0"]
+impl crate::Resettable for CediagSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cgcr.rs

@@ -0,0 +1,205 @@
+#[doc = "Register `CGCR` reader"]
+pub type R = crate::R<CgcrSpec>;
+#[doc = "Register `CGCR` writer"]
+pub type W = crate::W<CgcrSpec>;
+#[doc = "Field `CANEN` reader - CAN Enable"]
+pub type CanenR = crate::BitReader;
+#[doc = "Field `CANEN` writer - CAN Enable"]
+pub type CanenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRX` reader - RW,Control Receive"]
+pub type CrxR = crate::BitReader;
+#[doc = "Field `CRX` writer - RW,Control Receive"]
+pub type CrxW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CTX` reader - RW,Control Transmit"]
+pub type CtxR = crate::BitReader;
+#[doc = "Field `CTX` writer - RW,Control Transmit"]
+pub type CtxW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BUFFLOCK` reader - Buffer Lock"]
+pub type BufflockR = crate::BitReader;
+#[doc = "Field `BUFFLOCK` writer - Buffer Lock"]
+pub type BufflockW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TSTPEN` reader - Time Sync Enable"]
+pub type TstpenR = crate::BitReader;
+#[doc = "Field `TSTPEN` writer - Time Sync Enable"]
+pub type TstpenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DDIR` reader - Data Direction"]
+pub type DdirR = crate::BitReader;
+#[doc = "Field `DDIR` writer - Data Direction"]
+pub type DdirW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LO` reader - Listen Only"]
+pub type LoR = crate::BitReader;
+#[doc = "Field `LO` writer - Listen Only"]
+pub type LoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IGNACK` reader - Ignore Acknowledge"]
+pub type IgnackR = crate::BitReader;
+#[doc = "Field `IGNACK` writer - Ignore Acknowledge"]
+pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LOOPBACK` reader - Loopback"]
+pub type LoopbackR = crate::BitReader;
+#[doc = "Field `LOOPBACK` writer - Loopback"]
+pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INTERNAL` reader - Internal"]
+pub type InternalR = crate::BitReader;
+#[doc = "Field `INTERNAL` writer - Internal"]
+pub type InternalW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DIAGEN` reader - Diagnostic Enable"]
+pub type DiagenR = crate::BitReader;
+#[doc = "Field `DIAGEN` writer - Diagnostic Enable"]
+pub type DiagenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EIT` reader - Error Interrupt Type"]
+pub type EitR = crate::BitReader;
+#[doc = "Field `EIT` writer - Error Interrupt Type"]
+pub type EitW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - CAN Enable"]
+    #[inline(always)]
+    pub fn canen(&self) -> CanenR {
+        CanenR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW,Control Receive"]
+    #[inline(always)]
+    pub fn crx(&self) -> CrxR {
+        CrxR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW,Control Transmit"]
+    #[inline(always)]
+    pub fn ctx(&self) -> CtxR {
+        CtxR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Buffer Lock"]
+    #[inline(always)]
+    pub fn bufflock(&self) -> BufflockR {
+        BufflockR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Time Sync Enable"]
+    #[inline(always)]
+    pub fn tstpen(&self) -> TstpenR {
+        TstpenR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Data Direction"]
+    #[inline(always)]
+    pub fn ddir(&self) -> DdirR {
+        DdirR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Listen Only"]
+    #[inline(always)]
+    pub fn lo(&self) -> LoR {
+        LoR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Ignore Acknowledge"]
+    #[inline(always)]
+    pub fn ignack(&self) -> IgnackR {
+        IgnackR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Loopback"]
+    #[inline(always)]
+    pub fn loopback(&self) -> LoopbackR {
+        LoopbackR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Internal"]
+    #[inline(always)]
+    pub fn internal(&self) -> InternalR {
+        InternalR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Diagnostic Enable"]
+    #[inline(always)]
+    pub fn diagen(&self) -> DiagenR {
+        DiagenR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Error Interrupt Type"]
+    #[inline(always)]
+    pub fn eit(&self) -> EitR {
+        EitR::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - CAN Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn canen(&mut self) -> CanenW<CgcrSpec> {
+        CanenW::new(self, 0)
+    }
+    #[doc = "Bit 1 - RW,Control Receive"]
+    #[inline(always)]
+    #[must_use]
+    pub fn crx(&mut self) -> CrxW<CgcrSpec> {
+        CrxW::new(self, 1)
+    }
+    #[doc = "Bit 2 - RW,Control Transmit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ctx(&mut self) -> CtxW<CgcrSpec> {
+        CtxW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Buffer Lock"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bufflock(&mut self) -> BufflockW<CgcrSpec> {
+        BufflockW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Time Sync Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tstpen(&mut self) -> TstpenW<CgcrSpec> {
+        TstpenW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Data Direction"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ddir(&mut self) -> DdirW<CgcrSpec> {
+        DdirW::new(self, 5)
+    }
+    #[doc = "Bit 6 - Listen Only"]
+    #[inline(always)]
+    #[must_use]
+    pub fn lo(&mut self) -> LoW<CgcrSpec> {
+        LoW::new(self, 6)
+    }
+    #[doc = "Bit 7 - Ignore Acknowledge"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ignack(&mut self) -> IgnackW<CgcrSpec> {
+        IgnackW::new(self, 7)
+    }
+    #[doc = "Bit 8 - Loopback"]
+    #[inline(always)]
+    #[must_use]
+    pub fn loopback(&mut self) -> LoopbackW<CgcrSpec> {
+        LoopbackW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Internal"]
+    #[inline(always)]
+    #[must_use]
+    pub fn internal(&mut self) -> InternalW<CgcrSpec> {
+        InternalW::new(self, 9)
+    }
+    #[doc = "Bit 10 - Diagnostic Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn diagen(&mut self) -> DiagenW<CgcrSpec> {
+        DiagenW::new(self, 10)
+    }
+    #[doc = "Bit 11 - Error Interrupt Type"]
+    #[inline(always)]
+    #[must_use]
+    pub fn eit(&mut self) -> EitW<CgcrSpec> {
+        EitW::new(self, 11)
+    }
+}
+#[doc = "CAN Global Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CgcrSpec;
+impl crate::RegisterSpec for CgcrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cgcr::R`](R) reader structure"]
+impl crate::Readable for CgcrSpec {}
+#[doc = "`write(|w| ..)` method takes [`cgcr::W`](W) writer structure"]
+impl crate::Writable for CgcrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CGCR to value 0"]
+impl crate::Resettable for CgcrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cicen.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CICEN` reader"]
+pub type R = crate::R<CicenSpec>;
+#[doc = "Register `CICEN` writer"]
+pub type W = crate::W<CicenSpec>;
+#[doc = "Field `ICEN` reader - Buffer Interrupt Code Enable\\[14:0\\]"]
+pub type IcenR = crate::FieldReader<u16>;
+#[doc = "Field `ICEN` writer - Buffer Interrupt Code Enable\\[14:0\\]"]
+pub type IcenW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `EICEN` reader - Error Interrupt Code Enable"]
+pub type EicenR = crate::BitReader;
+#[doc = "Field `EICEN` writer - Error Interrupt Code Enable"]
+pub type EicenW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"]
+    #[inline(always)]
+    pub fn icen(&self) -> IcenR {
+        IcenR::new((self.bits & 0x7fff) as u16)
+    }
+    #[doc = "Bit 15 - Error Interrupt Code Enable"]
+    #[inline(always)]
+    pub fn eicen(&self) -> EicenR {
+        EicenR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn icen(&mut self) -> IcenW<CicenSpec> {
+        IcenW::new(self, 0)
+    }
+    #[doc = "Bit 15 - Error Interrupt Code Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn eicen(&mut self) -> EicenW<CicenSpec> {
+        EicenW::new(self, 15)
+    }
+}
+#[doc = "CAN Interrupt Code Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cicen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cicen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CicenSpec;
+impl crate::RegisterSpec for CicenSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cicen::R`](R) reader structure"]
+impl crate::Readable for CicenSpec {}
+#[doc = "`write(|w| ..)` method takes [`cicen::W`](W) writer structure"]
+impl crate::Writable for CicenSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CICEN to value 0"]
+impl crate::Resettable for CicenSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/ciclr.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CICLR` reader"]
+pub type R = crate::R<CiclrSpec>;
+#[doc = "Register `CICLR` writer"]
+pub type W = crate::W<CiclrSpec>;
+#[doc = "Field `ICLR` reader - Buffer Interrupt Clear\\[14:0\\]"]
+pub type IclrR = crate::FieldReader<u16>;
+#[doc = "Field `ICLR` writer - Buffer Interrupt Clear\\[14:0\\]"]
+pub type IclrW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `EICLR` reader - Error Interrupt Clear"]
+pub type EiclrR = crate::BitReader;
+#[doc = "Field `EICLR` writer - Error Interrupt Clear"]
+pub type EiclrW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"]
+    #[inline(always)]
+    pub fn iclr(&self) -> IclrR {
+        IclrR::new((self.bits & 0x7fff) as u16)
+    }
+    #[doc = "Bit 15 - Error Interrupt Clear"]
+    #[inline(always)]
+    pub fn eiclr(&self) -> EiclrR {
+        EiclrR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn iclr(&mut self) -> IclrW<CiclrSpec> {
+        IclrW::new(self, 0)
+    }
+    #[doc = "Bit 15 - Error Interrupt Clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn eiclr(&mut self) -> EiclrW<CiclrSpec> {
+        EiclrW::new(self, 15)
+    }
+}
+#[doc = "CAN Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ciclr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ciclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CiclrSpec;
+impl crate::RegisterSpec for CiclrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ciclr::R`](R) reader structure"]
+impl crate::Readable for CiclrSpec {}
+#[doc = "`write(|w| ..)` method takes [`ciclr::W`](W) writer structure"]
+impl crate::Writable for CiclrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CICLR to value 0"]
+impl crate::Resettable for CiclrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cien.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CIEN` reader"]
+pub type R = crate::R<CienSpec>;
+#[doc = "Register `CIEN` writer"]
+pub type W = crate::W<CienSpec>;
+#[doc = "Field `IEN` reader - Buffer Interrupt Enable\\[14:0\\]"]
+pub type IenR = crate::FieldReader<u16>;
+#[doc = "Field `IEN` writer - Buffer Interrupt Enable\\[14:0\\]"]
+pub type IenW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `EIEN` reader - Error Interrupt Enable"]
+pub type EienR = crate::BitReader;
+#[doc = "Field `EIEN` writer - Error Interrupt Enable"]
+pub type EienW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"]
+    #[inline(always)]
+    pub fn ien(&self) -> IenR {
+        IenR::new((self.bits & 0x7fff) as u16)
+    }
+    #[doc = "Bit 15 - Error Interrupt Enable"]
+    #[inline(always)]
+    pub fn eien(&self) -> EienR {
+        EienR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ien(&mut self) -> IenW<CienSpec> {
+        IenW::new(self, 0)
+    }
+    #[doc = "Bit 15 - Error Interrupt Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn eien(&mut self) -> EienW<CienSpec> {
+        EienW::new(self, 15)
+    }
+}
+#[doc = "CAN Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cien::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cien::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CienSpec;
+impl crate::RegisterSpec for CienSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cien::R`](R) reader structure"]
+impl crate::Readable for CienSpec {}
+#[doc = "`write(|w| ..)` method takes [`cien::W`](W) writer structure"]
+impl crate::Writable for CienSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CIEN to value 0"]
+impl crate::Resettable for CienSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cipnd.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CIPND` reader"]
+pub type R = crate::R<CipndSpec>;
+#[doc = "Register `CIPND` writer"]
+pub type W = crate::W<CipndSpec>;
+#[doc = "Field `IPND` reader - Buffer Interrupt Pending\\[14:0\\]"]
+pub type IpndR = crate::FieldReader<u16>;
+#[doc = "Field `IPND` writer - Buffer Interrupt Pending\\[14:0\\]"]
+pub type IpndW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `EIPND` reader - Error Interrupt Pending"]
+pub type EipndR = crate::BitReader;
+#[doc = "Field `EIPND` writer - Error Interrupt Pending"]
+pub type EipndW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"]
+    #[inline(always)]
+    pub fn ipnd(&self) -> IpndR {
+        IpndR::new((self.bits & 0x7fff) as u16)
+    }
+    #[doc = "Bit 15 - Error Interrupt Pending"]
+    #[inline(always)]
+    pub fn eipnd(&self) -> EipndR {
+        EipndR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ipnd(&mut self) -> IpndW<CipndSpec> {
+        IpndW::new(self, 0)
+    }
+    #[doc = "Bit 15 - Error Interrupt Pending"]
+    #[inline(always)]
+    #[must_use]
+    pub fn eipnd(&mut self) -> EipndW<CipndSpec> {
+        EipndW::new(self, 15)
+    }
+}
+#[doc = "CAN Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cipnd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cipnd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CipndSpec;
+impl crate::RegisterSpec for CipndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cipnd::R`](R) reader structure"]
+impl crate::Readable for CipndSpec {}
+#[doc = "`write(|w| ..)` method takes [`cipnd::W`](W) writer structure"]
+impl crate::Writable for CipndSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CIPND to value 0"]
+impl crate::Resettable for CipndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb0.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB0` reader"]
+pub type R = crate::R<CnstatCmb0Spec>;
+#[doc = "Register `CNSTAT_CMB0` writer"]
+pub type W = crate::W<CnstatCmb0Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb0Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb0Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb0Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb0Spec;
+impl crate::RegisterSpec for CnstatCmb0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb0::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb0Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb0::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB0 to value 0"]
+impl crate::Resettable for CnstatCmb0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb1.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB1` reader"]
+pub type R = crate::R<CnstatCmb1Spec>;
+#[doc = "Register `CNSTAT_CMB1` writer"]
+pub type W = crate::W<CnstatCmb1Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb1Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb1Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb1Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb1Spec;
+impl crate::RegisterSpec for CnstatCmb1Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb1::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb1Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb1::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb1Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB1 to value 0"]
+impl crate::Resettable for CnstatCmb1Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb10.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB10` reader"]
+pub type R = crate::R<CnstatCmb10Spec>;
+#[doc = "Register `CNSTAT_CMB10` writer"]
+pub type W = crate::W<CnstatCmb10Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb10Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb10Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb10Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb10::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb10Spec;
+impl crate::RegisterSpec for CnstatCmb10Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb10::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb10Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb10::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb10Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB10 to value 0"]
+impl crate::Resettable for CnstatCmb10Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb11.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB11` reader"]
+pub type R = crate::R<CnstatCmb11Spec>;
+#[doc = "Register `CNSTAT_CMB11` writer"]
+pub type W = crate::W<CnstatCmb11Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb11Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb11Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb11Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb11::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb11Spec;
+impl crate::RegisterSpec for CnstatCmb11Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb11::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb11Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb11::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb11Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB11 to value 0"]
+impl crate::Resettable for CnstatCmb11Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb12.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB12` reader"]
+pub type R = crate::R<CnstatCmb12Spec>;
+#[doc = "Register `CNSTAT_CMB12` writer"]
+pub type W = crate::W<CnstatCmb12Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb12Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb12Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb12Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb12::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb12Spec;
+impl crate::RegisterSpec for CnstatCmb12Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb12::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb12Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb12::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb12Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB12 to value 0"]
+impl crate::Resettable for CnstatCmb12Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb13.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB13` reader"]
+pub type R = crate::R<CnstatCmb13Spec>;
+#[doc = "Register `CNSTAT_CMB13` writer"]
+pub type W = crate::W<CnstatCmb13Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb13Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb13Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb13Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb13::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb13Spec;
+impl crate::RegisterSpec for CnstatCmb13Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb13::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb13Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb13::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb13Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB13 to value 0"]
+impl crate::Resettable for CnstatCmb13Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb14.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB14` reader"]
+pub type R = crate::R<CnstatCmb14Spec>;
+#[doc = "Register `CNSTAT_CMB14` writer"]
+pub type W = crate::W<CnstatCmb14Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb14Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb14Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb14Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb14::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb14Spec;
+impl crate::RegisterSpec for CnstatCmb14Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb14::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb14Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb14::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb14Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB14 to value 0"]
+impl crate::Resettable for CnstatCmb14Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb2.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB2` reader"]
+pub type R = crate::R<CnstatCmb2Spec>;
+#[doc = "Register `CNSTAT_CMB2` writer"]
+pub type W = crate::W<CnstatCmb2Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb2Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb2Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb2Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb2Spec;
+impl crate::RegisterSpec for CnstatCmb2Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb2::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb2Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb2::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb2Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB2 to value 0"]
+impl crate::Resettable for CnstatCmb2Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb3.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB3` reader"]
+pub type R = crate::R<CnstatCmb3Spec>;
+#[doc = "Register `CNSTAT_CMB3` writer"]
+pub type W = crate::W<CnstatCmb3Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb3Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb3Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb3Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb3Spec;
+impl crate::RegisterSpec for CnstatCmb3Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb3::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb3Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb3::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb3Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB3 to value 0"]
+impl crate::Resettable for CnstatCmb3Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb4.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB4` reader"]
+pub type R = crate::R<CnstatCmb4Spec>;
+#[doc = "Register `CNSTAT_CMB4` writer"]
+pub type W = crate::W<CnstatCmb4Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb4Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb4Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb4Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb4Spec;
+impl crate::RegisterSpec for CnstatCmb4Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb4::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb4Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb4::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb4Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB4 to value 0"]
+impl crate::Resettable for CnstatCmb4Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb5.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB5` reader"]
+pub type R = crate::R<CnstatCmb5Spec>;
+#[doc = "Register `CNSTAT_CMB5` writer"]
+pub type W = crate::W<CnstatCmb5Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb5Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb5Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb5Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb5Spec;
+impl crate::RegisterSpec for CnstatCmb5Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb5::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb5Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb5::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb5Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB5 to value 0"]
+impl crate::Resettable for CnstatCmb5Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb6.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB6` reader"]
+pub type R = crate::R<CnstatCmb6Spec>;
+#[doc = "Register `CNSTAT_CMB6` writer"]
+pub type W = crate::W<CnstatCmb6Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb6Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb6Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb6Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb6Spec;
+impl crate::RegisterSpec for CnstatCmb6Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb6::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb6Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb6::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb6Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB6 to value 0"]
+impl crate::Resettable for CnstatCmb6Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb7.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB7` reader"]
+pub type R = crate::R<CnstatCmb7Spec>;
+#[doc = "Register `CNSTAT_CMB7` writer"]
+pub type W = crate::W<CnstatCmb7Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb7Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb7Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb7Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb7Spec;
+impl crate::RegisterSpec for CnstatCmb7Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb7::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb7Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb7::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb7Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB7 to value 0"]
+impl crate::Resettable for CnstatCmb7Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb8.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB8` reader"]
+pub type R = crate::R<CnstatCmb8Spec>;
+#[doc = "Register `CNSTAT_CMB8` writer"]
+pub type W = crate::W<CnstatCmb8Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb8Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb8Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb8Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb8::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb8Spec;
+impl crate::RegisterSpec for CnstatCmb8Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb8::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb8Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb8::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb8Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB8 to value 0"]
+impl crate::Resettable for CnstatCmb8Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_cmb9.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_CMB9` reader"]
+pub type R = crate::R<CnstatCmb9Spec>;
+#[doc = "Register `CNSTAT_CMB9` writer"]
+pub type W = crate::W<CnstatCmb9Spec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatCmb9Spec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatCmb9Spec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatCmb9Spec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb9::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatCmb9Spec;
+impl crate::RegisterSpec for CnstatCmb9Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_cmb9::R`](R) reader structure"]
+impl crate::Readable for CnstatCmb9Spec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_cmb9::W`](W) writer structure"]
+impl crate::Writable for CnstatCmb9Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_CMB9 to value 0"]
+impl crate::Resettable for CnstatCmb9Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cnstat_hcmb.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CNSTAT_HCMB` reader"]
+pub type R = crate::R<CnstatHcmbSpec>;
+#[doc = "Register `CNSTAT_HCMB` writer"]
+pub type W = crate::W<CnstatHcmbSpec>;
+#[doc = "Field `ST` reader - Buffer Status"]
+pub type StR = crate::FieldReader;
+#[doc = "Field `ST` writer - Buffer Status"]
+pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `PRI` reader - Transmit Priority Code"]
+pub type PriR = crate::FieldReader;
+#[doc = "Field `PRI` writer - Transmit Priority Code"]
+pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DLC` reader - Data Length Code"]
+pub type DlcR = crate::FieldReader;
+#[doc = "Field `DLC` writer - Data Length Code"]
+pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    pub fn st(&self) -> StR {
+        StR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    pub fn pri(&self) -> PriR {
+        PriR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    pub fn dlc(&self) -> DlcR {
+        DlcR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Buffer Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn st(&mut self) -> StW<CnstatHcmbSpec> {
+        StW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Transmit Priority Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pri(&mut self) -> PriW<CnstatHcmbSpec> {
+        PriW::new(self, 4)
+    }
+    #[doc = "Bits 12:15 - Data Length Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn dlc(&mut self) -> DlcW<CnstatHcmbSpec> {
+        DlcW::new(self, 12)
+    }
+}
+#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_hcmb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CnstatHcmbSpec;
+impl crate::RegisterSpec for CnstatHcmbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cnstat_hcmb::R`](R) reader structure"]
+impl crate::Readable for CnstatHcmbSpec {}
+#[doc = "`write(|w| ..)` method takes [`cnstat_hcmb::W`](W) writer structure"]
+impl crate::Writable for CnstatHcmbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CNSTAT_HCMB to value 0"]
+impl crate::Resettable for CnstatHcmbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/cstpnd.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `CSTPND` reader"]
+pub type R = crate::R<CstpndSpec>;
+#[doc = "Register `CSTPND` writer"]
+pub type W = crate::W<CstpndSpec>;
+#[doc = "Field `IST` reader - Interrupt Source portion of Interrupt Code"]
+pub type IstR = crate::FieldReader;
+#[doc = "Field `IST` writer - Interrupt Source portion of Interrupt Code"]
+pub type IstW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `IRQ` reader - Interrupt Request portion of Interrupt Code"]
+pub type IrqR = crate::BitReader;
+#[doc = "Field `IRQ` writer - Interrupt Request portion of Interrupt Code"]
+pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NS` reader - CAN Node Status"]
+pub type NsR = crate::FieldReader;
+#[doc = "Field `NS` writer - CAN Node Status"]
+pub type NsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"]
+    #[inline(always)]
+    pub fn ist(&self) -> IstR {
+        IstR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"]
+    #[inline(always)]
+    pub fn irq(&self) -> IrqR {
+        IrqR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:7 - CAN Node Status"]
+    #[inline(always)]
+    pub fn ns(&self) -> NsR {
+        NsR::new(((self.bits >> 5) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ist(&mut self) -> IstW<CstpndSpec> {
+        IstW::new(self, 0)
+    }
+    #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq(&mut self) -> IrqW<CstpndSpec> {
+        IrqW::new(self, 4)
+    }
+    #[doc = "Bits 5:7 - CAN Node Status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ns(&mut self) -> NsW<CstpndSpec> {
+        NsW::new(self, 5)
+    }
+}
+#[doc = "CAN Status Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cstpnd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cstpnd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CstpndSpec;
+impl crate::RegisterSpec for CstpndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cstpnd::R`](R) reader structure"]
+impl crate::Readable for CstpndSpec {}
+#[doc = "`write(|w| ..)` method takes [`cstpnd::W`](W) writer structure"]
+impl crate::Writable for CstpndSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CSTPND to value 0"]
+impl crate::Resettable for CstpndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/ctim.rs

@@ -0,0 +1,85 @@
+#[doc = "Register `CTIM` reader"]
+pub type R = crate::R<CtimSpec>;
+#[doc = "Register `CTIM` writer"]
+pub type W = crate::W<CtimSpec>;
+#[doc = "Field `TSEG2` reader - Time Segment 2"]
+pub type Tseg2R = crate::FieldReader;
+#[doc = "Field `TSEG2` writer - Time Segment 2"]
+pub type Tseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TSEG1` reader - Time Segment 1"]
+pub type Tseg1R = crate::FieldReader;
+#[doc = "Field `TSEG1` writer - Time Segment 1"]
+pub type Tseg1W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `SJW` reader - Synchronization Jump Width"]
+pub type SjwR = crate::FieldReader;
+#[doc = "Field `SJW` writer - Synchronization Jump Width"]
+pub type SjwW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `PSC` reader - Prescaler Configuration"]
+pub type PscR = crate::FieldReader;
+#[doc = "Field `PSC` writer - Prescaler Configuration"]
+pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:2 - Time Segment 2"]
+    #[inline(always)]
+    pub fn tseg2(&self) -> Tseg2R {
+        Tseg2R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:6 - Time Segment 1"]
+    #[inline(always)]
+    pub fn tseg1(&self) -> Tseg1R {
+        Tseg1R::new(((self.bits >> 3) & 0x0f) as u8)
+    }
+    #[doc = "Bits 7:8 - Synchronization Jump Width"]
+    #[inline(always)]
+    pub fn sjw(&self) -> SjwR {
+        SjwR::new(((self.bits >> 7) & 3) as u8)
+    }
+    #[doc = "Bits 9:15 - Prescaler Configuration"]
+    #[inline(always)]
+    pub fn psc(&self) -> PscR {
+        PscR::new(((self.bits >> 9) & 0x7f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Time Segment 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tseg2(&mut self) -> Tseg2W<CtimSpec> {
+        Tseg2W::new(self, 0)
+    }
+    #[doc = "Bits 3:6 - Time Segment 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn tseg1(&mut self) -> Tseg1W<CtimSpec> {
+        Tseg1W::new(self, 3)
+    }
+    #[doc = "Bits 7:8 - Synchronization Jump Width"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sjw(&mut self) -> SjwW<CtimSpec> {
+        SjwW::new(self, 7)
+    }
+    #[doc = "Bits 9:15 - Prescaler Configuration"]
+    #[inline(always)]
+    #[must_use]
+    pub fn psc(&mut self) -> PscW<CtimSpec> {
+        PscW::new(self, 9)
+    }
+}
+#[doc = "CAN Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtimSpec;
+impl crate::RegisterSpec for CtimSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctim::R`](R) reader structure"]
+impl crate::Readable for CtimSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctim::W`](W) writer structure"]
+impl crate::Writable for CtimSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTIM to value 0"]
+impl crate::Resettable for CtimSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/ctmr.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `CTMR` reader"]
+pub type R = crate::R<CtmrSpec>;
+#[doc = "Register `CTMR` writer"]
+pub type W = crate::W<CtmrSpec>;
+#[doc = "Field `CTMR` reader - Time Stamp Counter"]
+pub type CtmrR = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - Time Stamp Counter"]
+    #[inline(always)]
+    pub fn ctmr(&self) -> CtmrR {
+        CtmrR::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {}
+#[doc = "CAN Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctmr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtmrSpec;
+impl crate::RegisterSpec for CtmrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctmr::R`](R) reader structure"]
+impl crate::Readable for CtmrSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctmr::W`](W) writer structure"]
+impl crate::Writable for CtmrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTMR to value 0"]
+impl crate::Resettable for CtmrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb0.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB0` reader"]
+pub type R = crate::R<Data0Cmb0Spec>;
+#[doc = "Register `DATA0_CMB0` writer"]
+pub type W = crate::W<Data0Cmb0Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb0Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb0Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb0Spec;
+impl crate::RegisterSpec for Data0Cmb0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb0::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb0Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb0::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB0 to value 0"]
+impl crate::Resettable for Data0Cmb0Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb1.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB1` reader"]
+pub type R = crate::R<Data0Cmb1Spec>;
+#[doc = "Register `DATA0_CMB1` writer"]
+pub type W = crate::W<Data0Cmb1Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb1Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb1Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb1Spec;
+impl crate::RegisterSpec for Data0Cmb1Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb1::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb1Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb1::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb1Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB1 to value 0"]
+impl crate::Resettable for Data0Cmb1Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb10.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB10` reader"]
+pub type R = crate::R<Data0Cmb10Spec>;
+#[doc = "Register `DATA0_CMB10` writer"]
+pub type W = crate::W<Data0Cmb10Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb10Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb10Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb10::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb10Spec;
+impl crate::RegisterSpec for Data0Cmb10Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb10::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb10Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb10::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb10Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB10 to value 0"]
+impl crate::Resettable for Data0Cmb10Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb11.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB11` reader"]
+pub type R = crate::R<Data0Cmb11Spec>;
+#[doc = "Register `DATA0_CMB11` writer"]
+pub type W = crate::W<Data0Cmb11Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb11Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb11Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb11::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb11Spec;
+impl crate::RegisterSpec for Data0Cmb11Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb11::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb11Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb11::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb11Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB11 to value 0"]
+impl crate::Resettable for Data0Cmb11Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb12.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB12` reader"]
+pub type R = crate::R<Data0Cmb12Spec>;
+#[doc = "Register `DATA0_CMB12` writer"]
+pub type W = crate::W<Data0Cmb12Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb12Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb12Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb12::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb12Spec;
+impl crate::RegisterSpec for Data0Cmb12Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb12::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb12Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb12::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb12Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB12 to value 0"]
+impl crate::Resettable for Data0Cmb12Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb13.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB13` reader"]
+pub type R = crate::R<Data0Cmb13Spec>;
+#[doc = "Register `DATA0_CMB13` writer"]
+pub type W = crate::W<Data0Cmb13Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb13Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb13Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb13::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb13Spec;
+impl crate::RegisterSpec for Data0Cmb13Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb13::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb13Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb13::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb13Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB13 to value 0"]
+impl crate::Resettable for Data0Cmb13Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/can0/data0_cmb14.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `DATA0_CMB14` reader"]
+pub type R = crate::R<Data0Cmb14Spec>;
+#[doc = "Register `DATA0_CMB14` writer"]
+pub type W = crate::W<Data0Cmb14Spec>;
+#[doc = "Field `BYTE2` reader - Data Byte 2"]
+pub type Byte2R = crate::FieldReader;
+#[doc = "Field `BYTE2` writer - Data Byte 2"]
+pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `BYTE1` reader - Data Byte 1"]
+pub type Byte1R = crate::FieldReader;
+#[doc = "Field `BYTE1` writer - Data Byte 1"]
+pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> Byte2R {
+        Byte2R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> Byte1R {
+        Byte1R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data Byte 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte2(&mut self) -> Byte2W<Data0Cmb14Spec> {
+        Byte2W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Data Byte 1"]
+    #[inline(always)]
+    #[must_use]
+    pub fn byte1(&mut self) -> Byte1W<Data0Cmb14Spec> {
+        Byte1W::new(self, 8)
+    }
+}
+#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb14::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Data0Cmb14Spec;
+impl crate::RegisterSpec for Data0Cmb14Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data0_cmb14::R`](R) reader structure"]
+impl crate::Readable for Data0Cmb14Spec {}
+#[doc = "`write(|w| ..)` method takes [`data0_cmb14::W`](W) writer structure"]
+impl crate::Writable for Data0Cmb14Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA0_CMB14 to value 0"]
+impl crate::Resettable for Data0Cmb14Spec {
+    const RESET_VALUE: u32 = 0;
+}