init commit
This commit is contained in:
220
va416xx/src/clkgen/ctrl0.rs
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220
va416xx/src/clkgen/ctrl0.rs
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@ -0,0 +1,220 @@
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#[doc = "Register `CTRL0` reader"]
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pub type R = crate::R<Ctrl0Spec>;
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#[doc = "Register `CTRL0` writer"]
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pub type W = crate::W<Ctrl0Spec>;
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#[doc = "Field `REF_CLK_SEL` reader - PLL Reference Clock Select"]
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pub type RefClkSelR = crate::FieldReader;
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#[doc = "Field `REF_CLK_SEL` writer - PLL Reference Clock Select"]
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pub type RefClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `CLKSEL_SYS` reader - Input clock select to PLL"]
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pub type ClkselSysR = crate::FieldReader;
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#[doc = "Field `CLKSEL_SYS` writer - Input clock select to PLL"]
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pub type ClkselSysW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `PLL_INTFB` reader - PLL Symbol; select internal feedback path when high rather than FCLK"]
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pub type PllIntfbR = crate::BitReader;
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#[doc = "Field `PLL_INTFB` writer - PLL Symbol; select internal feedback path when high rather than FCLK"]
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pub type PllIntfbW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `PLL_PWDN` reader - PLL Symbol; power down when high"]
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pub type PllPwdnR = crate::BitReader;
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#[doc = "Field `PLL_PWDN` writer - PLL Symbol; power down when high"]
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pub type PllPwdnW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `PLL_BYPASS` reader - PLL Symbol; reference-to-output bypass when high"]
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pub type PllBypassR = crate::BitReader;
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#[doc = "Field `PLL_BYPASS` writer - PLL Symbol; reference-to-output bypass when high"]
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pub type PllBypassW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `PLL_TEST` reader - PLL Symbol; Reference-to-counters-to-output bypass when high"]
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pub type PllTestR = crate::BitReader;
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#[doc = "Field `PLL_TEST` writer - PLL Symbol; Reference-to-counters-to-output bypass when high"]
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pub type PllTestW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `PLL_BWADJ` reader - PLL Symbol; selects the values 1-64 for the bandwidth divider"]
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pub type PllBwadjR = crate::FieldReader;
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#[doc = "Field `PLL_BWADJ` writer - PLL Symbol; selects the values 1-64 for the bandwidth divider"]
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pub type PllBwadjW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
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#[doc = "Field `PLL_CLKOD` reader - PLL Symbol; selects the values 1-16 for the post VCO divider"]
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pub type PllClkodR = crate::FieldReader;
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#[doc = "Field `PLL_CLKOD` writer - PLL Symbol; selects the values 1-16 for the post VCO divider"]
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pub type PllClkodW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
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#[doc = "Field `PLL_CLKF` reader - PLL Symbol; selects the values 1-64 for the multiplication factor"]
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pub type PllClkfR = crate::FieldReader;
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#[doc = "Field `PLL_CLKF` writer - PLL Symbol; selects the values 1-64 for the multiplication factor"]
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pub type PllClkfW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
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#[doc = "Field `PLL_CLKR` reader - PLL Symbol; selects the values 1-16 for the reference divider"]
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pub type PllClkrR = crate::FieldReader;
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#[doc = "Field `PLL_CLKR` writer - PLL Symbol; selects the values 1-16 for the reference divider"]
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pub type PllClkrW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
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#[doc = "Field `CLK_DIV_SEL` reader - Selects the PLL out divider to divide by 1/2/4/8"]
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pub type ClkDivSelR = crate::FieldReader;
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#[doc = "Field `CLK_DIV_SEL` writer - Selects the PLL out divider to divide by 1/2/4/8"]
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pub type ClkDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `PLL_RESET` reader - Writing this bit to 1 puts the PLL into reset"]
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pub type PllResetR = crate::BitReader;
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#[doc = "Field `PLL_RESET` writer - Writing this bit to 1 puts the PLL into reset"]
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pub type PllResetW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `SYS_CLK_LOST_DET_EN` reader - Enable the circuit that detects loss of SYS_CLK"]
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pub type SysClkLostDetEnR = crate::BitReader;
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#[doc = "Field `SYS_CLK_LOST_DET_EN` writer - Enable the circuit that detects loss of SYS_CLK"]
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pub type SysClkLostDetEnW<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bits 0:1 - PLL Reference Clock Select"]
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#[inline(always)]
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pub fn ref_clk_sel(&self) -> RefClkSelR {
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RefClkSelR::new((self.bits & 3) as u8)
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}
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#[doc = "Bits 2:3 - Input clock select to PLL"]
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#[inline(always)]
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pub fn clksel_sys(&self) -> ClkselSysR {
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ClkselSysR::new(((self.bits >> 2) & 3) as u8)
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}
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#[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"]
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#[inline(always)]
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pub fn pll_intfb(&self) -> PllIntfbR {
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PllIntfbR::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 5 - PLL Symbol; power down when high"]
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#[inline(always)]
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pub fn pll_pwdn(&self) -> PllPwdnR {
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PllPwdnR::new(((self.bits >> 5) & 1) != 0)
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}
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#[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"]
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#[inline(always)]
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pub fn pll_bypass(&self) -> PllBypassR {
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PllBypassR::new(((self.bits >> 6) & 1) != 0)
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}
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#[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"]
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#[inline(always)]
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pub fn pll_test(&self) -> PllTestR {
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PllTestR::new(((self.bits >> 7) & 1) != 0)
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}
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#[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"]
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#[inline(always)]
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pub fn pll_bwadj(&self) -> PllBwadjR {
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PllBwadjR::new(((self.bits >> 8) & 0x3f) as u8)
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}
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#[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"]
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#[inline(always)]
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pub fn pll_clkod(&self) -> PllClkodR {
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PllClkodR::new(((self.bits >> 14) & 0x0f) as u8)
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}
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#[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"]
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#[inline(always)]
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pub fn pll_clkf(&self) -> PllClkfR {
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PllClkfR::new(((self.bits >> 18) & 0x3f) as u8)
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}
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#[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"]
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#[inline(always)]
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pub fn pll_clkr(&self) -> PllClkrR {
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PllClkrR::new(((self.bits >> 24) & 0x0f) as u8)
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}
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#[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"]
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#[inline(always)]
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pub fn clk_div_sel(&self) -> ClkDivSelR {
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ClkDivSelR::new(((self.bits >> 28) & 3) as u8)
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}
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#[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"]
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#[inline(always)]
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pub fn pll_reset(&self) -> PllResetR {
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PllResetR::new(((self.bits >> 30) & 1) != 0)
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}
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#[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"]
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#[inline(always)]
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pub fn sys_clk_lost_det_en(&self) -> SysClkLostDetEnR {
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SysClkLostDetEnR::new(((self.bits >> 31) & 1) != 0)
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}
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}
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impl W {
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#[doc = "Bits 0:1 - PLL Reference Clock Select"]
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#[inline(always)]
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#[must_use]
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pub fn ref_clk_sel(&mut self) -> RefClkSelW<Ctrl0Spec> {
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RefClkSelW::new(self, 0)
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}
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#[doc = "Bits 2:3 - Input clock select to PLL"]
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#[inline(always)]
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#[must_use]
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pub fn clksel_sys(&mut self) -> ClkselSysW<Ctrl0Spec> {
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ClkselSysW::new(self, 2)
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}
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#[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"]
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#[inline(always)]
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#[must_use]
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pub fn pll_intfb(&mut self) -> PllIntfbW<Ctrl0Spec> {
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PllIntfbW::new(self, 4)
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}
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#[doc = "Bit 5 - PLL Symbol; power down when high"]
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#[inline(always)]
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#[must_use]
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pub fn pll_pwdn(&mut self) -> PllPwdnW<Ctrl0Spec> {
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PllPwdnW::new(self, 5)
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}
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#[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"]
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#[inline(always)]
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#[must_use]
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pub fn pll_bypass(&mut self) -> PllBypassW<Ctrl0Spec> {
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PllBypassW::new(self, 6)
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}
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#[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"]
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#[inline(always)]
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#[must_use]
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pub fn pll_test(&mut self) -> PllTestW<Ctrl0Spec> {
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PllTestW::new(self, 7)
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}
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#[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"]
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#[inline(always)]
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#[must_use]
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pub fn pll_bwadj(&mut self) -> PllBwadjW<Ctrl0Spec> {
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PllBwadjW::new(self, 8)
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}
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#[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"]
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#[inline(always)]
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#[must_use]
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pub fn pll_clkod(&mut self) -> PllClkodW<Ctrl0Spec> {
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PllClkodW::new(self, 14)
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}
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#[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"]
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#[inline(always)]
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#[must_use]
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pub fn pll_clkf(&mut self) -> PllClkfW<Ctrl0Spec> {
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PllClkfW::new(self, 18)
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}
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#[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"]
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#[inline(always)]
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#[must_use]
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pub fn pll_clkr(&mut self) -> PllClkrW<Ctrl0Spec> {
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PllClkrW::new(self, 24)
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}
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#[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"]
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#[inline(always)]
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#[must_use]
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pub fn clk_div_sel(&mut self) -> ClkDivSelW<Ctrl0Spec> {
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ClkDivSelW::new(self, 28)
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}
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#[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"]
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#[inline(always)]
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#[must_use]
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pub fn pll_reset(&mut self) -> PllResetW<Ctrl0Spec> {
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PllResetW::new(self, 30)
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}
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#[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"]
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#[inline(always)]
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#[must_use]
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pub fn sys_clk_lost_det_en(&mut self) -> SysClkLostDetEnW<Ctrl0Spec> {
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SysClkLostDetEnW::new(self, 31)
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}
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}
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#[doc = "Clock Generation Module Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Ctrl0Spec;
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impl crate::RegisterSpec for Ctrl0Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"]
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impl crate::Readable for Ctrl0Spec {}
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#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
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impl crate::Writable for Ctrl0Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CTRL0 to value 0x30"]
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impl crate::Resettable for Ctrl0Spec {
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const RESET_VALUE: u32 = 0x30;
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}
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115
va416xx/src/clkgen/ctrl1.rs
Normal file
115
va416xx/src/clkgen/ctrl1.rs
Normal file
@ -0,0 +1,115 @@
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#[doc = "Register `CTRL1` reader"]
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pub type R = crate::R<Ctrl1Spec>;
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#[doc = "Register `CTRL1` writer"]
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pub type W = crate::W<Ctrl1Spec>;
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#[doc = "Field `SYS_CLK_LOST_DET_REARM` reader - Resets/Rearms the SYS_CLK lost detection feature"]
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pub type SysClkLostDetRearmR = crate::BitReader;
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#[doc = "Field `SYS_CLK_LOST_DET_REARM` writer - Resets/Rearms the SYS_CLK lost detection feature"]
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pub type SysClkLostDetRearmW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `PLL_LCK_DET_REARM` reader - Resets/Rearms the PLL lock detect circuit"]
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pub type PllLckDetRearmR = crate::BitReader;
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#[doc = "Field `PLL_LCK_DET_REARM` writer - Resets/Rearms the PLL lock detect circuit"]
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pub type PllLckDetRearmW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `PLL_LOST_LOCK_DET_EN` reader - Enables the PLL lock lost detection circuit"]
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pub type PllLostLockDetEnR = crate::BitReader;
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#[doc = "Field `PLL_LOST_LOCK_DET_EN` writer - Enables the PLL lock lost detection circuit"]
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pub type PllLostLockDetEnW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `XTAL_EN` reader - Enables the crystal oscillator"]
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pub type XtalEnR = crate::BitReader;
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#[doc = "Field `XTAL_EN` writer - Enables the crystal oscillator"]
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pub type XtalEnW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `XTAL_N_EN` reader - Enables XTAL_N output"]
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pub type XtalNEnR = crate::BitReader;
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#[doc = "Field `XTAL_N_EN` writer - Enables XTAL_N output"]
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pub type XtalNEnW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `ADC_CLK_DIV_SEL` reader - Clock divider select for ADC"]
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pub type AdcClkDivSelR = crate::FieldReader;
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#[doc = "Field `ADC_CLK_DIV_SEL` writer - Clock divider select for ADC"]
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pub type AdcClkDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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impl R {
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#[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"]
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#[inline(always)]
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pub fn sys_clk_lost_det_rearm(&self) -> SysClkLostDetRearmR {
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SysClkLostDetRearmR::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"]
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#[inline(always)]
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pub fn pll_lck_det_rearm(&self) -> PllLckDetRearmR {
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PllLckDetRearmR::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - Enables the PLL lock lost detection circuit"]
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#[inline(always)]
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pub fn pll_lost_lock_det_en(&self) -> PllLostLockDetEnR {
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PllLostLockDetEnR::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - Enables the crystal oscillator"]
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#[inline(always)]
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pub fn xtal_en(&self) -> XtalEnR {
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XtalEnR::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - Enables XTAL_N output"]
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#[inline(always)]
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pub fn xtal_n_en(&self) -> XtalNEnR {
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XtalNEnR::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bits 5:6 - Clock divider select for ADC"]
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#[inline(always)]
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pub fn adc_clk_div_sel(&self) -> AdcClkDivSelR {
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AdcClkDivSelR::new(((self.bits >> 5) & 3) as u8)
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}
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}
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impl W {
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#[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"]
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#[inline(always)]
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#[must_use]
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pub fn sys_clk_lost_det_rearm(&mut self) -> SysClkLostDetRearmW<Ctrl1Spec> {
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SysClkLostDetRearmW::new(self, 0)
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}
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#[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"]
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#[inline(always)]
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#[must_use]
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pub fn pll_lck_det_rearm(&mut self) -> PllLckDetRearmW<Ctrl1Spec> {
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PllLckDetRearmW::new(self, 1)
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}
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#[doc = "Bit 2 - Enables the PLL lock lost detection circuit"]
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#[inline(always)]
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#[must_use]
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pub fn pll_lost_lock_det_en(&mut self) -> PllLostLockDetEnW<Ctrl1Spec> {
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PllLostLockDetEnW::new(self, 2)
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}
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#[doc = "Bit 3 - Enables the crystal oscillator"]
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#[inline(always)]
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#[must_use]
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pub fn xtal_en(&mut self) -> XtalEnW<Ctrl1Spec> {
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XtalEnW::new(self, 3)
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}
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#[doc = "Bit 4 - Enables XTAL_N output"]
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#[inline(always)]
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#[must_use]
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pub fn xtal_n_en(&mut self) -> XtalNEnW<Ctrl1Spec> {
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XtalNEnW::new(self, 4)
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}
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#[doc = "Bits 5:6 - Clock divider select for ADC"]
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#[inline(always)]
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#[must_use]
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pub fn adc_clk_div_sel(&mut self) -> AdcClkDivSelW<Ctrl1Spec> {
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AdcClkDivSelW::new(self, 5)
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}
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}
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#[doc = "Clock Generation Module Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Ctrl1Spec;
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impl crate::RegisterSpec for Ctrl1Spec {
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type Ux = u32;
|
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}
|
||||
#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
|
||||
impl crate::Readable for Ctrl1Spec {}
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#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
|
||||
impl crate::Writable for Ctrl1Spec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CTRL1 to value 0"]
|
||||
impl crate::Resettable for Ctrl1Spec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
43
va416xx/src/clkgen/stat.rs
Normal file
43
va416xx/src/clkgen/stat.rs
Normal file
@ -0,0 +1,43 @@
|
||||
#[doc = "Register `STAT` reader"]
|
||||
pub type R = crate::R<StatSpec>;
|
||||
#[doc = "Field `FBSLIP` reader - Feedback cycle slip output (CLKOUT frequency low)"]
|
||||
pub type FbslipR = crate::BitReader;
|
||||
#[doc = "Field `RFSLIP` reader - Reference cycle slip output (CLKOUT frequency high)"]
|
||||
pub type RfslipR = crate::BitReader;
|
||||
#[doc = "Field `LOCKLOST` reader - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"]
|
||||
pub type LocklostR = crate::BitReader;
|
||||
#[doc = "Field `SYSCLKLOST` reader - Set when SYS_CLK has dropped to less than 1MHz"]
|
||||
pub type SysclklostR = crate::BitReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Feedback cycle slip output (CLKOUT frequency low)"]
|
||||
#[inline(always)]
|
||||
pub fn fbslip(&self) -> FbslipR {
|
||||
FbslipR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Reference cycle slip output (CLKOUT frequency high)"]
|
||||
#[inline(always)]
|
||||
pub fn rfslip(&self) -> RfslipR {
|
||||
RfslipR::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"]
|
||||
#[inline(always)]
|
||||
pub fn locklost(&self) -> LocklostR {
|
||||
LocklostR::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Set when SYS_CLK has dropped to less than 1MHz"]
|
||||
#[inline(always)]
|
||||
pub fn sysclklost(&self) -> SysclklostR {
|
||||
SysclklostR::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Clock Generation Module Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct StatSpec;
|
||||
impl crate::RegisterSpec for StatSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`stat::R`](R) reader structure"]
|
||||
impl crate::Readable for StatSpec {}
|
||||
#[doc = "`reset()` method sets STAT to value 0"]
|
||||
impl crate::Resettable for StatSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Reference in New Issue
Block a user