88 lines
3.6 KiB
Markdown
88 lines
3.6 KiB
Markdown
Change Log
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=======
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All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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# [unreleased]
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# [v0.4.0] 2025-02-14
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## Changed
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- GPIO API: Interrupt, pulse and filter and `set_datamask` and `clear_datamask` APIs are now
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methods which mutable modify the pin instead of consuming and returning it.
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- Simplified PWM module implementation.
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- All error types now implement `core::error::Error` by using the `thiserror::Error` derive.
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- `InvalidPinTypeError` now wraps the pin mode.
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- I2C `TimingCfg` constructor now returns explicit error instead of generic Error.
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Removed the timing configuration error type from the generic I2C error enumeration.
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- `PinsA` and `PinsB` constructor do not expect an optional `pac::Ioconfig` argument anymore.
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- `IrqCfg` renamed to `InterruptConfig`, kept alias for old name.
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- All library provided interrupt handlers now start with common prefix `on_interrupt_*`
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- `RxWithIrq` renamed to `RxWithInterrupt`
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- `Rx::into_rx_with_irq` does not expect any arguments any more.
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- `filter_type` renamed to `configure_filter_type`.
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- `level_irq` renamed to `configure_level_interrupt`.
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- `edge_irq` renamed to `configure_edge_interrupt`.
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- UART interrupt management is now handled by the main constructor instead of later stages to
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statically ensure one interrupt vector for the UART peripheral. `Uart::new` expects an
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optional `InterruptConfig` argument.
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- `enable_interrupt` and `disable_interrupt` renamed to `enable_nvic_interrupt` and
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`disable_nvic_interrupt` to distinguish them from peripheral interrupts more clearly.
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- `port_mux` renamed to `port_function_select`
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- Renamed `IrqUartErrors` to `UartErrors`.
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# [v0.3.0] 2024-30-09
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## Changed
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- Improve and fix SPI abstractions. Add new low level interface. The primary SPI constructor now
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only expects a configuration structure and the transfer configuration needs to be applied in a
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separate step.
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- Added an additional way to read the UART RX with IRQs. The module documentation provides
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more information.
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- Made the UART with IRQ API more flexible for future additions.
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- Improved UART API result and error handling, added low level API to read from and write
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to the FIFO directly
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## Fixed
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- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly.
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- Fixes for SPI example
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- Fixes for RTIC example
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# [v0.2.0] 2024-09-18
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- Documentation improvements
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- Improved UART typing support: Validity of passed pins is now checked properly
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## Changed
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- Added `va41620`, `va41630`, `va41628` and `va41629` device features. A device now has to be
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selected for HAL compilation to work properly
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- Adaptions for the UART IRQ feature which are now only implemented for the RX part of the UART.
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## Fixed
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- Small fixes and improvements for ADC drivers
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- Fixes for the SPI implementation where the clock divider values were not calculated
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correctly
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- Fixes for UART IRQ handler implementation
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- Add new IRQ router initialization method `irq_router::enable_and_init_irq_router`. This method
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also sets the initial values of some registers to 0 where the datasheet and the actual reset
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value are inconsistent, which can lead to weird bugs like IRQs not being triggered properly.
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## Added
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- Added basic DMA driver
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- Added basic EDAC module
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- Added bootloader and flashloader example application
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- Added NVM module which exposes a simple API to write to the NVM memory used for the boot process
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# [v0.1.0] 2024-07-01
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- Initial release with basic HAL drivers
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