12271 lines
430 KiB
XML
12271 lines
430 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
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<vendor>VORAGO TECHNOLOGIES</vendor>
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<vendorID>SST</vendorID>
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<name>va416xx</name>
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<series>M4</series>
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<version>1.3</version>
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<description>ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz</description>
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<licenseText>VORAGO Technologies \n
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\n
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----------------------------------------------------------------------------\n
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Copyright (c) 2013-2020 VORAGO Technologies\n
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\n
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BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n
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AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n
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\n
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THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
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OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
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VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n
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FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n</licenseText>
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<cpu>
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<name>CM4</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<headerSystemFilename>system_va416xx</headerSystemFilename>
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<headerDefinitionsPrefix>VOR_</headerDefinitionsPrefix>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>CLKGEN</name>
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<version>1.0</version>
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<description>Clock Generation Peripheral</description>
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<baseAddress>0x40006000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x100</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>LoCLK</name>
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<value>45</value>
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</interrupt>
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<registers>
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<register>
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<name>CTRL0</name>
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<description>Clock Generation Module Control Register 0</description>
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<addressOffset>0x0</addressOffset>
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<resetValue>0x00000030</resetValue>
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<fields>
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<field>
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<name>SYS_CLK_LOST_DET_EN</name>
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<description>Enable the circuit that detects loss of SYS_CLK</description>
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<bitRange>[31:31]</bitRange>
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</field>
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<field>
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<name>PLL_RESET</name>
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<description>Writing this bit to 1 puts the PLL into reset</description>
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<bitRange>[30:30]</bitRange>
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</field>
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<field>
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<name>CLK_DIV_SEL</name>
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<description>Selects the PLL out divider to divide by 1/2/4/8</description>
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<bitRange>[29:28]</bitRange>
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</field>
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<field>
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<name>PLL_CLKR</name>
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<description>PLL Symbol; selects the values 1-16 for the reference divider</description>
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<bitRange>[27:24]</bitRange>
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</field>
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<field>
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<name>PLL_CLKF</name>
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<description>PLL Symbol; selects the values 1-64 for the multiplication factor</description>
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<bitRange>[23:18]</bitRange>
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</field>
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<field>
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<name>PLL_CLKOD</name>
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<description>PLL Symbol; selects the values 1-16 for the post VCO divider</description>
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<bitRange>[17:14]</bitRange>
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</field>
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<field>
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<name>PLL_BWADJ</name>
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<description>PLL Symbol; selects the values 1-64 for the bandwidth divider</description>
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<bitRange>[13:8]</bitRange>
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</field>
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<field>
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<name>PLL_TEST</name>
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<description>PLL Symbol; Reference-to-counters-to-output bypass when high</description>
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<bitRange>[7:7]</bitRange>
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</field>
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<field>
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<name>PLL_BYPASS</name>
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<description>PLL Symbol; reference-to-output bypass when high</description>
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<bitRange>[6:6]</bitRange>
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</field>
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<field>
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<name>PLL_PWDN</name>
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<description>PLL Symbol; power down when high</description>
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<bitRange>[5:5]</bitRange>
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</field>
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<field>
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<name>PLL_INTFB</name>
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<description>PLL Symbol; select internal feedback path when high rather than FCLK</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>CLKSEL_SYS</name>
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<description>Input clock select to PLL</description>
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<bitRange>[3:2]</bitRange>
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</field>
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<field>
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<name>REF_CLK_SEL</name>
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<description>PLL Reference Clock Select</description>
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<bitRange>[1:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>STAT</name>
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<description>Clock Generation Module Status Register</description>
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<addressOffset>0x4</addressOffset>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>SYSCLKLOST</name>
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<description>Set when SYS_CLK has dropped to less than 1MHz</description>
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<bitRange>[3:3]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>LOCKLOST</name>
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<description>LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles</description>
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<bitRange>[2:2]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>RFSLIP</name>
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<description>Reference cycle slip output (CLKOUT frequency high)</description>
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<bitRange>[1:1]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>FBSLIP</name>
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<description>Feedback cycle slip output (CLKOUT frequency low)</description>
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<bitRange>[0:0]</bitRange>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>CTRL1</name>
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<description>Clock Generation Module Control Register 1</description>
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<addressOffset>0x8</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ADC_CLK_DIV_SEL</name>
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<description>Clock divider select for ADC</description>
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<bitRange>[6:5]</bitRange>
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</field>
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<field>
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<name>XTAL_N_EN</name>
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<description>Enables XTAL_N output</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>XTAL_EN</name>
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<description>Enables the crystal oscillator</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>PLL_LOST_LOCK_DET_EN</name>
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<description>Enables the PLL lock lost detection circuit</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>PLL_LCK_DET_REARM</name>
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<description>Resets/Rearms the PLL lock detect circuit</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>SYS_CLK_LOST_DET_REARM</name>
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<description>Resets/Rearms the SYS_CLK lost detection feature</description>
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<bitRange>[0:0]</bitRange>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>SYSCONFIG</name>
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<version>1.0</version>
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<description>System Configuration Peripheral</description>
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<baseAddress>0x40010000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x1000</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>LVD</name>
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<value>46</value>
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</interrupt>
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<interrupt>
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<name>EDAC_MBE</name>
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<value>76</value>
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</interrupt>
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<interrupt>
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<name>EDAC_SBE</name>
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<value>77</value>
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</interrupt>
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<registers>
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<register>
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<name>RST_STAT</name>
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<description>System Reset Status</description>
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<addressOffset>0x0</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>POR</name>
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<description>Power On Reset Status</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>EXTRST</name>
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<description>External Reset Status</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>SYSRSTREQ</name>
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<description>SYSRESETREQ Reset Status</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>LOOKUP</name>
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<description>LOOKUP Reset Status</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>WATCHDOG</name>
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<description>WATCHDOG Reset Status</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>MEMERR</name>
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<description>Memory Error Reset Status</description>
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<bitRange>[5:5]</bitRange>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register derivedFrom="RST_STAT">
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<name>RST_CNTL_ROM</name>
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<description>ROM Reset Control</description>
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<addressOffset>0x4</addressOffset>
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<resetValue>0x0000003F</resetValue>
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</register>
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<register derivedFrom="RST_STAT">
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<name>RST_CNTL_RAM0</name>
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<description>RAM Reset Control</description>
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<addressOffset>0x8</addressOffset>
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<resetValue>0x0000003F</resetValue>
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</register>
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<register derivedFrom="RST_STAT">
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<name>RST_CNTL_RAM1</name>
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<description>RAM Reset Control</description>
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<addressOffset>0xC</addressOffset>
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<resetValue>0x0000003F</resetValue>
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</register>
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<register>
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<name>ROM_PROT</name>
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<description>ROM Protection Configuration</description>
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<addressOffset>0x10</addressOffset>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>WREN</name>
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<description>ROM Write Enable Bit</description>
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<bitRange>[0:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>ROM_SCRUB</name>
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<description>ROM Scrub Period Configuration</description>
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<addressOffset>0x14</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>VALUE</name>
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<description>Counter divide value</description>
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<bitRange>[23:0]</bitRange>
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</field>
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<field>
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<name>RESET</name>
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<description>Reset Counter</description>
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<bitRange>[31:31]</bitRange>
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<access>write-only</access>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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</field>
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</fields>
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</register>
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<register derivedFrom="ROM_SCRUB">
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<name>RAM0_SCRUB</name>
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<description>RAM0 Scrub Period Configuration</description>
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<addressOffset>0x18</addressOffset>
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</register>
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<register derivedFrom="ROM_SCRUB">
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<name>RAM1_SCRUB</name>
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<description>RAM1 Scrub Period Configuration</description>
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<addressOffset>0x1C</addressOffset>
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</register>
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<register>
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<name>IRQ_ENB</name>
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<description>Enable EDAC Error Interrupt Register</description>
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<addressOffset>0x20</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ROMMBE</name>
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<description>ROM Multi Bit Interrupt</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>ROMSBE</name>
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<description>ROM Single Bit Interrupt</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>RAM0MBE</name>
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<description>RAM0 Multi Bit Interrupt</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>RAM0SBE</name>
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<description>RAM0 Single Bit Interrupt</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>RAM1MBE</name>
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<description>RAM1 Multi Bit Interrupt</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>RAM1SBE</name>
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<description>RAM1 Single Bit Interrupt</description>
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<bitRange>[5:5]</bitRange>
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</field>
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</fields>
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</register>
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<register derivedFrom="IRQ_ENB">
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<name>IRQ_RAW</name>
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<description>Raw EDAC Error Interrupt Status</description>
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<addressOffset>0x24</addressOffset>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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</register>
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<register derivedFrom="IRQ_ENB">
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<name>IRQ_END</name>
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<description>Enabled EDAC Error Interrupt Status</description>
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<addressOffset>0x28</addressOffset>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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</register>
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<register derivedFrom="IRQ_ENB">
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<name>IRQ_CLR</name>
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<description>Clear EDAC Error Interrupt Status</description>
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<addressOffset>0x2C</addressOffset>
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<access>write-only</access>
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<resetValue>0x00000000</resetValue>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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</register>
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<register>
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<name>RAM0_SBE</name>
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<description>Count of RAM0 EDAC Single Bit Errors</description>
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<addressOffset>0x30</addressOffset>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>COUNT</name>
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<description>RAM0 EDAC Single Bit Errors</description>
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<bitRange>[15:0]</bitRange>
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</field>
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</fields>
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</register>
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<register derivedFrom="RAM0_SBE">
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<name>RAM1_SBE</name>
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<description>Count of RAM1 EDAC Single Bit Errors</description>
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<addressOffset>0x34</addressOffset>
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</register>
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<register>
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<name>RAM0_MBE</name>
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<description>Count of RAM0 EDAC Multi Bit Errors</description>
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<addressOffset>0x38</addressOffset>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>COUNT</name>
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<description>RAM0 Multi Bit Errors</description>
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<bitRange>[15:0]</bitRange>
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</field>
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</fields>
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</register>
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<register derivedFrom="RAM0_MBE">
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<name>RAM1_MBE</name>
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<description>Count of RAM1 EDAC Multi Bit Errors</description>
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<addressOffset>0x3C</addressOffset>
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</register>
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<register derivedFrom="RAM0_SBE">
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<name>ROM_SBE</name>
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<description>Count of ROM EDAC Single Bit Errors</description>
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<addressOffset>0x40</addressOffset>
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</register>
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<register derivedFrom="RAM0_MBE">
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<name>ROM_MBE</name>
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<description>Count of ROM EDAC Multi Bit Errors</description>
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<addressOffset>0x44</addressOffset>
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</register>
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|
<register>
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|
<name>ROM_RETRIES</name>
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|
<description>ROM BOOT Retry count</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<access>read-only</access>
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|
<resetValue>0x00000000</resetValue>
|
|
<fields>
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|
<field>
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|
<name>COUNT</name>
|
|
<description>Count of ROM block Retries</description>
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|
<bitRange>[7:0]</bitRange>
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|
</field>
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|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REFRESH_CONFIG_H</name>
|
|
<description>Register Refresh Rate for TMR registers</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVCOUNT</name>
|
|
<description>Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles</description>
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|
<bitRange>[7:0]</bitRange>
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|
</field>
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|
<field>
|
|
<name>TESTMODE</name>
|
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<description>Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly.</description>
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<bitRange>[31:30]</bitRange>
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</field>
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|
</fields>
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|
</register>
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|
<register>
|
|
<name>TIM_RESET</name>
|
|
<description>TIM Reset Control</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIM_RESET</name>
|
|
<description>Reset of a given TIMER</description>
|
|
<bitRange>[23:0]</bitRange>
|
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</field>
|
|
</fields>
|
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</register>
|
|
<register>
|
|
<name>TIM_CLK_ENABLE</name>
|
|
<description>TIM Enable Control</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMERS</name>
|
|
<description>Clock enable of a given TIMER</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Peripheral Reset Control</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<resetValue>0x7F7BEFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPI0</name>
|
|
<description>Resetn of SPI0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPI1</name>
|
|
<description>Resetn of SPI1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPI2</name>
|
|
<description>Resetn of SPI2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPI3</name>
|
|
<description>Resetn of SPI3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0</name>
|
|
<description>Resetn of UART0</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1</name>
|
|
<description>Resetn of UART1</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART2</name>
|
|
<description>Resetn of UART2</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C0</name>
|
|
<description>Resetn of I2C0</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C1</name>
|
|
<description>Resetn of I2C1</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C2</name>
|
|
<description>Resetn of I2C2</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN0</name>
|
|
<description>Resetn of CAN0</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN1</name>
|
|
<description>Resetn of CAN1</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRNG</name>
|
|
<description>Resetn of TRNG</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>Resetn of ADC</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC</name>
|
|
<description>Resetn of DAC</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>Resetn of DMA</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EBI</name>
|
|
<description>Resetn of EBI</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH</name>
|
|
<description>Resetn of Ethernet</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPW</name>
|
|
<description>Resetn of SpaceWire</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKGEN</name>
|
|
<description>RESETn of PLL in Clock Generation Module</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Resetn of IRQ Router</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IOCONFIG</name>
|
|
<description>Resetn of IO CONFIG</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UTILITY</name>
|
|
<description>Resetn of UTILITY peripheral</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WDOG</name>
|
|
<description>Resetn of WDOG</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTA</name>
|
|
<description>Resetn of PORTA</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTB</name>
|
|
<description>Resetn of PORTB</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTC</name>
|
|
<description>Resetn of PORTC</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTD</name>
|
|
<description>Resetn of PORTD</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTE</name>
|
|
<description>Resetn of PORTE</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTF</name>
|
|
<description>Resetn of PORTF</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORTG</name>
|
|
<description>Resetn of PORTG</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="PERIPHERAL_RESET">
|
|
<name>PERIPHERAL_CLK_ENABLE</name>
|
|
<description>Peripheral Enable Control</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<resetValue>0x00880000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SPW_M4_CTRL</name>
|
|
<description>SPW M4 control register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00030000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LREN</name>
|
|
<description>Lockup reset enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPW_PAD_EN</name>
|
|
<description>SPW pad enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REG_WR_KEY</name>
|
|
<description>Fuse-analog register writes enabled when key = 0xfeed</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMU_CTRL</name>
|
|
<description>PMU Control Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LVL_SLCT</name>
|
|
<description>Select the POK detect level</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKEUP_CNT</name>
|
|
<description>Wakeup Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTSTRT</name>
|
|
<description>Launch SLP mode in analog block</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WKUP_CNT</name>
|
|
<description>Used to set a time to wake up the processor after the device has been put in a low power state</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EBI_CFG0</name>
|
|
<description>EBI Config Register 0</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRLOW0</name>
|
|
<description>Lower bound address for CEN0</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDRHIGH0</name>
|
|
<description>Upper bound address for CEN0</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CFGREADCYCLE</name>
|
|
<description>Number of cycles for a read - N plus 1</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CFGWRITECYCLE</name>
|
|
<description>Number of cycles for a write - N plus 1</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CFGTURNAROUNDCYCLE</name>
|
|
<description>Number of cycles for turnaround - N plus 1</description>
|
|
<bitRange>[24:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CFGSIZE</name>
|
|
<description>8 bit (0) or 16 bit (1) port size</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="EBI_CFG0">
|
|
<name>EBI_CFG1</name>
|
|
<description>EBI Config Register 1</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="EBI_CFG0">
|
|
<name>EBI_CFG2</name>
|
|
<description>EBI Config Register 2</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="EBI_CFG0">
|
|
<name>EBI_CFG3</name>
|
|
<description>EBI Config Register 3</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ANALOG_CNTL</name>
|
|
<description>Analog Control Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMOSC</name>
|
|
<description>Test Mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMPOKDIS</name>
|
|
<description>Test Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TM_ADCMUX_N</name>
|
|
<description>Test Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TM_ADCMUX_P</name>
|
|
<description>Test Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMRATIO</name>
|
|
<description>Test Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMATOMUX</name>
|
|
<description>Test Mode</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_STEST</name>
|
|
<description>Number of clocks for sample time</description>
|
|
<bitRange>[12:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RCLK_POS_EN</name>
|
|
<description>Enable normal test clock</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RCLK_NEG_EN</name>
|
|
<description>Enable inverted test clock</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APB2CLK_POS_EN</name>
|
|
<description>Enable normal APB2CLK for test output</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APB2CLK_NEG_EN</name>
|
|
<description>Enable inverted APB2CLK for test output</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TM_ANALOG_PD_EN</name>
|
|
<description>Enables pull down on analog pads</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JMP2BOOT</name>
|
|
<description>Enables a skip of all delay counters and eFuse read</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SKIPBOOT</name>
|
|
<description>Enables a skip of all delay counters, eFuse read, and boot</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_CLKDIV10</name>
|
|
<description>Initial SpW Clock Divider Value</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000009</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SW_CLKDIV10</name>
|
|
<description>Defines the initial value for the SpW clock, defaults to divide by ten</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REFRESH_CONFIG_L</name>
|
|
<description>Register Refresh Rate for TMR registers</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVCOUNT</name>
|
|
<description>Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC0_CAL</name>
|
|
<description>DAC0 Calibration Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_CAL</name>
|
|
<description>DAC0 Calibration bits</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC1_CAL</name>
|
|
<description>DAC1 Calibration Register</description>
|
|
<addressOffset>0xFD4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC1_CAL</name>
|
|
<description>DAC1 Calibration bits</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC_CAL</name>
|
|
<description>ADC Calibration Register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_CAL</name>
|
|
<description>ADC Calibration bits</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BG_CAL</name>
|
|
<description>Bandgap Calibration Register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BG_CAL</name>
|
|
<description>Bandgap Calibration bits</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DREG_CAL</name>
|
|
<description>Digital LDO Regulator Calibration Register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DREG_CAL</name>
|
|
<description>Digital LDO Regulator Calibration bits</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AREG_CAL</name>
|
|
<description>Analog LDO Regulator Calibration Register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AREG_CAL</name>
|
|
<description>Analog LDO Regulator Calibration bits</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HBO_CAL</name>
|
|
<description>Heart Beat OSC Calibration Register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSC_CAL</name>
|
|
<description>1MHz OSC Calibration bit</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HBO_CAL</name>
|
|
<description>Heart Beat OSC Calibration bits</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EF_CONFIG</name>
|
|
<description>EFuse Config Register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0A800C40</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ROM_SPEED</name>
|
|
<description>Specifies the speed of ROM_SCK</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_SIZE</name>
|
|
<description>Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_NOCHECK</name>
|
|
<description>When set to 1, the ROM check is skipped</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_DELAY</name>
|
|
<description>Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_READ</name>
|
|
<description>SPI ROM read instruction code</description>
|
|
<bitRange>[17:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_LATENCY</name>
|
|
<description>Number of bits of latency from Address until data from the SPI ROM</description>
|
|
<bitRange>[22:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_ADDRESS</name>
|
|
<description>ROM Address Mode</description>
|
|
<bitRange>[24:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_DLYCAP</name>
|
|
<description>ROM SPI Delayed capture</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_STATUS</name>
|
|
<description>The first data byte from the SPI ROM following an address is taken as a status byte</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RM</name>
|
|
<description>This bit controls the internal RAM read timing and must be maintained at this value</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WM</name>
|
|
<description>This bit controls the internal RAM write timing and must be maintained at this value</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EF_ID0</name>
|
|
<description>EFuse ID0 Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>EF_ID1</name>
|
|
<description>EFuse ID1 Register</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PROCID</name>
|
|
<description>Processor ID Register</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x040057E3</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x028007E9</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MANUFACTURER_ID</name>
|
|
<description>MANUFACTURER_ID</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_ID</name>
|
|
<description>PERIPHERAL_ID</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_VER</name>
|
|
<description>PERIPHERAL_VER</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<version>1.0</version>
|
|
<description>DMA Controller Block</description>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA_ERROR</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_ACTIVE0</name>
|
|
<value>174</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_ACTIVE1</name>
|
|
<value>175</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_ACTIVE2</name>
|
|
<value>176</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_ACTIVE3</name>
|
|
<value>177</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_DONE0</name>
|
|
<value>178</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_DONE1</name>
|
|
<value>179</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_DONE2</name>
|
|
<value>180</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_DONE3</name>
|
|
<value>181</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>DMA Status</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEST_STATUS</name>
|
|
<description>Test Status Logic Included</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHNLS_MINUS1</name>
|
|
<description>Number of Available Channels Minus 1</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Current State of the control state machine</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_ENABLE</name>
|
|
<description>Enable status of the controller</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>DMA Configuration</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_PROT_CTRL</name>
|
|
<description>HPROT[3:0]</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_ENABLE</name>
|
|
<description>PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_BASE_PTR</name>
|
|
<description>Base Pointer for DMA Control Registers</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL_BASE_PTR</name>
|
|
<description>Base Pointer for DMA Control Registers</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALT_CTRL_BASE_PTR</name>
|
|
<description>DMA Channel alternate control data base pointer</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALT_CTRL_BASE_PTR</name>
|
|
<description>Base Pointer for Alternate DMA Control Register</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAITONREQ_STATUS</name>
|
|
<description>DMA channel wait on request status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA wait on request</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA wait on request</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA wait on request</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA wait on request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_SW_REQUEST</name>
|
|
<description>DMA channel software request</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel SW request</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel SW request</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel SW request</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel SW request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_USEBURST_SET</name>
|
|
<description>DMA channel useburst set</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel use burst set</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel use burst set</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel use burst set</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel use burst set</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_USEBURST_CLR</name>
|
|
<description>DMA channel useburst clear</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel use burst clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel use burst clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel use burst clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel use burst clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_REQ_MASK_SET</name>
|
|
<description>DMA channel request mask set</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel Request Mask set</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel Request Mask set</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel Request Mask set</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel Request Mask set</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_REQ_MASK_CLR</name>
|
|
<description>DMA channel request mask clear</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel Request Mask clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel Request Mask clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel Request Mask clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel Request Mask clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_ENABLE_SET</name>
|
|
<description>DMA channel enable set</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel Enable set</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel Enable set</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel Enable set</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel Enable set</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_ENABLE_CLR</name>
|
|
<description>DMA channel enable clear</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel Enable clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel Enable clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel Enable clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel Enable clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_PRI_ALT_SET</name>
|
|
<description>DMA channel primary alternate set</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel PRI_ALT set</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel PRI_ALT set</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel PRI_ALT set</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel PRI_ALT set</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_PRI_ALT_CLR</name>
|
|
<description>DMA channel primary alternate clear</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel PRI_ALT clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel PRI_ALT clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel PRI_ALT clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel PRI_ALT clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_PRIORITY_SET</name>
|
|
<description>DMA channel priority set</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel PRIORITY set</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel PRIORITY set</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel PRIORITY set</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel PRIORITY set</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNL_PRIORITY_CLR</name>
|
|
<description>DMA channel priority clear</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel PRIORITY clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel PRIORITY clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel PRIORITY clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel PRIORITY clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR_CLR</name>
|
|
<description>DMA bus error clear</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR_CLR</name>
|
|
<description>Error Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEGRATION_CFG</name>
|
|
<description>DMA integration configuration</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INT_TEST_EN</name>
|
|
<description>Error Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STALL_STATUS</name>
|
|
<description>DMA stall status</description>
|
|
<addressOffset>0xE08</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STALL_STATUS</name>
|
|
<description>DMA is stalled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REQ_STATUS</name>
|
|
<description>DMA Configuration</description>
|
|
<addressOffset>0xE10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA Request Status for this CH</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA Request Status for this CH</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA Request Status for this CH</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA Request Status for this CH</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_SREQ_STATUS</name>
|
|
<description>DMA single request status</description>
|
|
<addressOffset>0xE18</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA SRequest Status for this CH</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA SRequest Status for this CH</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA SRequest Status for this CH</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA SRequest Status for this CH</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_DONE_SET</name>
|
|
<description>DMA done set</description>
|
|
<addressOffset>0xE20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA Done Set for this CH</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA Done Set for this CH</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA Done Set for this CH</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA Done Set for this CH</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_DONE_CLR</name>
|
|
<description>DMA done clear</description>
|
|
<addressOffset>0xE24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA Done clear for this CH</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA Done clear for this CH</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA Done clear for this CH</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA Done clear for this CH</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ACTIVE_SET</name>
|
|
<description>DMA active set</description>
|
|
<addressOffset>0xE28</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA Active Set</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA Active Set</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA Active Set</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA Active Set</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_ACTIVE_CLR</name>
|
|
<description>DMA active clear</description>
|
|
<addressOffset>0xE2C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>DMA Active clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>DMA Active clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>DMA Active clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>DMA Active clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR_SET</name>
|
|
<description>DMA bus error set</description>
|
|
<addressOffset>0xE48</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ERR_SET</name>
|
|
<description>Set Error</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPH_ID_4</name>
|
|
<description>DMA Peripheral ID 4</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<resetValue>0x00000004</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLOCK_COUNT</name>
|
|
<description>The Number of 4k Address Blocks Required</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JEP106_C_CODE</name>
|
|
<description>JEP106</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPH_ID_0</name>
|
|
<description>DMA Peripheral ID 0</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<resetValue>0x00000030</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PART_NUMBER_0</name>
|
|
<description>Part Number</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPH_ID_1</name>
|
|
<description>DMA Peripheral ID 1</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JEP106_ID_3_0</name>
|
|
<description>Indentity Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PART_NUMBER_1</name>
|
|
<description>Part Number 1</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPH_ID_2</name>
|
|
<description>DMA Peripheral ID 2</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<resetValue>0x000000BC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JEDEC_USED</name>
|
|
<description>JEDEC</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JEP106_ID_6_4</name>
|
|
<description>JEP106</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPH_ID_3</name>
|
|
<description>DMA Peripheral ID 3</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MOD_NUMBER</name>
|
|
<description>Controller Modifications</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRIMECELL_ID_0</name>
|
|
<description>DMA PrimeCell ID 0</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRIMECELL_ID_0</name>
|
|
<description>PrimeCell Identification</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRIMECELL_ID_1</name>
|
|
<description>DMA PrimeCell ID 1</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<resetValue>0x000000F0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRIMECELL_ID_1</name>
|
|
<description>PrimeCell Identification</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRIMECELL_ID_2</name>
|
|
<description>DMA PrimeCell ID 2</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRIMECELL_ID_2</name>
|
|
<description>PrimeCell Identification</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRIMECELL_ID_3</name>
|
|
<description>DMA PrimeCell ID 3</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRIMECELL_ID_3</name>
|
|
<description>PrimeCell Identification</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOCONFIG</name>
|
|
<version>1.0</version>
|
|
<description>IO Pin Configuration Peripheral</description>
|
|
<baseAddress>0x40011000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>PORTA[%s]</name>
|
|
<description>PORTA Pin Configuration Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTTYPE</name>
|
|
<description>Input Filter Selectoin</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>Synchronize to system clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIRECT</name>
|
|
<description>Direct input, no synchronization</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER1</name>
|
|
<description>Require 2 samples to have the same value</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER2</name>
|
|
<description>Require 3 samples to have the same value</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER3</name>
|
|
<description>Require 4 samples to have the same value</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER4</name>
|
|
<description>Require 5 samples to have the same value</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTCLK</name>
|
|
<description>Input Filter Clock Selection</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVINP</name>
|
|
<description>Input Invert Selection</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEWO</name>
|
|
<description>Input Enable While Output enabled</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OPENDRN</name>
|
|
<description>Output Open Drain Mode</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVOUT</name>
|
|
<description>Output Invert Selection</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PLEVEL</name>
|
|
<description>Internal Pull up/down level</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>Enable Internal Pull up/down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWOA</name>
|
|
<description>Enable Pull when output active</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUNSEL</name>
|
|
<description>Pin Function Selection</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IODIS</name>
|
|
<description>IO Pin Disable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="PORTA[%s]">
|
|
<name>PORTB[%s]</name>
|
|
<description>PORTB Pin Configuration Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="PORTA[%s]">
|
|
<name>PORTC[%s]</name>
|
|
<description>PORTC Pin Configuration Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="PORTA[%s]">
|
|
<name>PORTD[%s]</name>
|
|
<description>PORTD Pin Configuration Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="PORTA[%s]">
|
|
<name>PORTE[%s]</name>
|
|
<description>PORTE Pin Configuration Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="PORTA[%s]">
|
|
<name>PORTF[%s]</name>
|
|
<description>PORTF Pin Configuration Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="PORTA[%s]">
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>PORTG[%s]</name>
|
|
<description>PORTG Pin Configuration Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV0</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV1</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV2</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV3</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV4</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV5</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV6</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV7</name>
|
|
<description>Clock divide value. 0 will disable the clock</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x028207E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UTILITY</name>
|
|
<version>1.0</version>
|
|
<description>Utility Peripheral</description>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SYND_DATA</name>
|
|
<description>Data Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SYND_SYND</name>
|
|
<description>Syndrome Data Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYND_SYND</name>
|
|
<description>Provides bits 11:0 for syndrome, 2x6-bit</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYND_ENC_32_44</name>
|
|
<description>EDAC Encode</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYND_ENC_31_16</name>
|
|
<description>Computed syndrome value for bits 31-16</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYND_ENC_7_0</name>
|
|
<description>Computed syndrome value for bits 15-0</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYND_CHECK_32_44_DATA</name>
|
|
<description>EDAC Decode Data</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SYND_CHECK_32_44_SYND</name>
|
|
<description>EDAC Decode Syndrome</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBE</name>
|
|
<description>Multiple bit error detect status</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Single bit error detect status</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYND_CHECK_32_44_SYND</name>
|
|
<description>Correct syndrome value</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROM_TRAP_ADDRESS</name>
|
|
<description>ROM EDAC Trap Address</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Trap mode</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address bits for trap match</description>
|
|
<bitRange>[30:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROM_TRAP_SYND</name>
|
|
<description>ROM EDAC Trap Syndrome</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>R0M_SYND_31_16</name>
|
|
<description>6-bit syndrome value for bits 31-16</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_SYND_7_0</name>
|
|
<description>6-bit syndrome value for bits 15-0</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM_TRAP_ADDR0</name>
|
|
<description>RAM0 EDAC Trap Address</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Trap mode</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address bits for trap match</description>
|
|
<bitRange>[30:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM_TRAP_SYND0</name>
|
|
<description>RAM0 EDAC Trap Syndrome</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RAM_SYND_31_16</name>
|
|
<description>6-bit syndrome value for bits 31-16</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAM_SYND_7_0</name>
|
|
<description>6-bit syndrome value for bits 15-0</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM_TRAP_ADDR1</name>
|
|
<description>RAM1 EDAC Trap Address</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Trap mode</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address bits for trap match</description>
|
|
<bitRange>[30:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM_TRAP_SYND1</name>
|
|
<description>RAM1 EDAC Trap Syndrome</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RAM_SYND_31_16</name>
|
|
<description>6-bit syndrome value for bits 31-16</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAM_SYND_7_0</name>
|
|
<description>6-bit syndrome value for bits 15-0</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYND_ENC_32_52</name>
|
|
<description>EDAC Encode</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYND_ENC_32_52</name>
|
|
<description>Computed syndrome value for bits 15-0</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYND_CHECK_32_52_DATA</name>
|
|
<description>EDAC Decode Data</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SYND_CHECK_32_52_SYND</name>
|
|
<description>EDAC Decode Syndrome</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBE</name>
|
|
<description>Multiple bit error detect status</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Single bit error detect status</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYND_CHECK_32_52_SYND</name>
|
|
<description>Corrected syndrome value</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x028407E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTA</name>
|
|
<version>1.0</version>
|
|
<description>GPIO Peripheral</description>
|
|
<groupName>GPIO</groupName>
|
|
<headerStructName>GPIO</headerStructName>
|
|
<baseAddress>0x40012000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTA0</name>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA1</name>
|
|
<value>79</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA2</name>
|
|
<value>80</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA3</name>
|
|
<value>81</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA4</name>
|
|
<value>82</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA5</name>
|
|
<value>83</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA6</name>
|
|
<value>84</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA7</name>
|
|
<value>85</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA8</name>
|
|
<value>86</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA9</name>
|
|
<value>87</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA10</name>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA11</name>
|
|
<value>89</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA12</name>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA13</name>
|
|
<value>91</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA14</name>
|
|
<value>92</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTA15</name>
|
|
<value>93</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB0</name>
|
|
<value>94</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB1</name>
|
|
<value>95</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB2</name>
|
|
<value>96</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB3</name>
|
|
<value>97</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB4</name>
|
|
<value>98</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB5</name>
|
|
<value>99</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB6</name>
|
|
<value>100</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB7</name>
|
|
<value>101</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB8</name>
|
|
<value>102</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB9</name>
|
|
<value>103</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB10</name>
|
|
<value>104</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB11</name>
|
|
<value>105</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB12</name>
|
|
<value>106</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB13</name>
|
|
<value>107</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB14</name>
|
|
<value>108</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTB15</name>
|
|
<value>109</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC0</name>
|
|
<value>110</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC1</name>
|
|
<value>111</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC2</name>
|
|
<value>112</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC3</name>
|
|
<value>113</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC4</name>
|
|
<value>114</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC5</name>
|
|
<value>115</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC6</name>
|
|
<value>116</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC7</name>
|
|
<value>117</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC8</name>
|
|
<value>118</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC9</name>
|
|
<value>119</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC10</name>
|
|
<value>120</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC11</name>
|
|
<value>121</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC12</name>
|
|
<value>122</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC13</name>
|
|
<value>123</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC14</name>
|
|
<value>124</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTC15</name>
|
|
<value>125</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD0</name>
|
|
<value>126</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD1</name>
|
|
<value>127</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD2</name>
|
|
<value>128</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD3</name>
|
|
<value>129</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD4</name>
|
|
<value>130</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD5</name>
|
|
<value>131</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD6</name>
|
|
<value>132</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD7</name>
|
|
<value>133</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD8</name>
|
|
<value>134</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD9</name>
|
|
<value>135</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD10</name>
|
|
<value>136</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD11</name>
|
|
<value>137</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD12</name>
|
|
<value>138</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD13</name>
|
|
<value>139</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD14</name>
|
|
<value>140</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTD15</name>
|
|
<value>141</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE0</name>
|
|
<value>142</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE1</name>
|
|
<value>143</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE2</name>
|
|
<value>144</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE3</name>
|
|
<value>145</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE4</name>
|
|
<value>146</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE5</name>
|
|
<value>147</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE6</name>
|
|
<value>148</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE7</name>
|
|
<value>149</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE8</name>
|
|
<value>150</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE9</name>
|
|
<value>151</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE10</name>
|
|
<value>152</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE11</name>
|
|
<value>153</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE12</name>
|
|
<value>154</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE13</name>
|
|
<value>155</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE14</name>
|
|
<value>156</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTE15</name>
|
|
<value>157</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF0</name>
|
|
<value>158</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF1</name>
|
|
<value>159</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF2</name>
|
|
<value>160</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF3</name>
|
|
<value>161</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF4</name>
|
|
<value>162</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF5</name>
|
|
<value>163</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF6</name>
|
|
<value>164</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF7</name>
|
|
<value>165</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF8</name>
|
|
<value>166</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF9</name>
|
|
<value>167</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF10</name>
|
|
<value>168</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF11</name>
|
|
<value>169</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF12</name>
|
|
<value>170</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF13</name>
|
|
<value>171</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF14</name>
|
|
<value>172</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PORTF15</name>
|
|
<value>173</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DATAIN</name>
|
|
<description>Data In Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<name>DATAINBYTE[%s]</name>
|
|
<description>Data In Register by Byte</description>
|
|
<alternateRegister>DATAIN</alternateRegister>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAIN">
|
|
<name>DATAINRAW</name>
|
|
<description>Data In Raw Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAINBYTE[%s]">
|
|
<name>DATAINRAWBYTE[%s]</name>
|
|
<description>Data In Raw Register by Byte</description>
|
|
<alternateRegister>DATAINRAW</alternateRegister>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DATAOUT</name>
|
|
<description>Data Out Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<name>DATAOUTBYTE[%s]</name>
|
|
<description>Data Out Register by Byte</description>
|
|
<alternateRegister>DATAOUT</alternateRegister>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUT">
|
|
<name>DATAOUTRAW</name>
|
|
<description>Data Out Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUTBYTE[%s]">
|
|
<name>DATAOUTRAWBYTE[%s]</name>
|
|
<description>Data Out Register by Byte</description>
|
|
<alternateRegister>DATAOUTRAW</alternateRegister>
|
|
<addressOffset>0xC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUT">
|
|
<name>SETOUT</name>
|
|
<description>Set Out Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUTBYTE[%s]">
|
|
<name>SETOUTBYTE[%s]</name>
|
|
<description>Set Out Register by Byte</description>
|
|
<alternateRegister>SETOUT</alternateRegister>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUT">
|
|
<name>CLROUT</name>
|
|
<description>Clear Out Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUTBYTE[%s]">
|
|
<name>CLROUTBYTE[%s]</name>
|
|
<description>Clear Out Register by Byte</description>
|
|
<alternateRegister>CLROUT</alternateRegister>
|
|
<addressOffset>0x14</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUT">
|
|
<name>TOGOUT</name>
|
|
<description>Toggle Out Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAOUTBYTE[%s]">
|
|
<name>TOGOUTBYTE[%s]</name>
|
|
<description>Toggle Out Register by Byte</description>
|
|
<alternateRegister>TOGOUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DATAMASK</name>
|
|
<description>Data mask Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<name>DATAMASKBYTE[%s]</name>
|
|
<description>Data Out Register by Byte</description>
|
|
<alternateRegister>DATAMASK</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x8</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASK">
|
|
<name>DIR</name>
|
|
<description>Direction Register (1:Output, 0:Input)</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASKBYTE[%s]">
|
|
<name>DIRBYTE[%s]</name>
|
|
<description>Direction Register by Byte</description>
|
|
<alternateRegister>DIR</alternateRegister>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASK">
|
|
<name>PULSE</name>
|
|
<description>Pulse Mode Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASKBYTE[%s]">
|
|
<name>PULSEBYTE[%s]</name>
|
|
<description>Pulse Mode Register by Byte</description>
|
|
<alternateRegister>PULSE</alternateRegister>
|
|
<addressOffset>0x24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASK">
|
|
<name>PULSEBASE</name>
|
|
<description>Pulse Base Value Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASKBYTE[%s]">
|
|
<name>PULSEBASEBYTE[%s]</name>
|
|
<description>Pulse Base Mode Register by Byte</description>
|
|
<alternateRegister>PULSEBASE</alternateRegister>
|
|
<addressOffset>0x28</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASK">
|
|
<name>DELAY1</name>
|
|
<description>Delay1 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASKBYTE[%s]">
|
|
<name>DELAY1BYTE[%s]</name>
|
|
<description>Delay1 Register by Byte</description>
|
|
<alternateRegister>DELAY1</alternateRegister>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASK">
|
|
<name>DELAY2</name>
|
|
<description>Delay2 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="DATAMASKBYTE[%s]">
|
|
<name>DELAY2BYTE[%s]</name>
|
|
<description>Delay2 Register by Byte</description>
|
|
<alternateRegister>DELAY2</alternateRegister>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_SEN</name>
|
|
<description>Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_EDGE</name>
|
|
<description>Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_EVT</name>
|
|
<description>Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_ENB</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_RAW</name>
|
|
<description>Raw Interrupt Status</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_END</name>
|
|
<description>Masked Interrupt Status</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>EDGE_STATUS</name>
|
|
<description>Edge Status Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x021007E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORTA">
|
|
<name>PORTB</name>
|
|
<baseAddress>0x40012400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORTA">
|
|
<name>PORTC</name>
|
|
<baseAddress>0x40012800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORTA">
|
|
<name>PORTD</name>
|
|
<baseAddress>0x40012C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORTA">
|
|
<name>PORTE</name>
|
|
<baseAddress>0x40013000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORTA">
|
|
<name>PORTF</name>
|
|
<baseAddress>0x40013400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORTA">
|
|
<name>PORTG</name>
|
|
<baseAddress>0x40013800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM0</name>
|
|
<version>1.0</version>
|
|
<description>Timer/Counter Peripheral</description>
|
|
<groupName>Timer_Counter</groupName>
|
|
<headerStructName>TIM</headerStructName>
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM0</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM1</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM2</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM3</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM4</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM5</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM6</name>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM7</name>
|
|
<value>55</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM8</name>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM9</name>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM10</name>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM11</name>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM12</name>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM13</name>
|
|
<value>61</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM14</name>
|
|
<value>62</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM15</name>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM16</name>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM17</name>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM18</name>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM19</name>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM20</name>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM21</name>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM22</name>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM23</name>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Counter Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Counter Active</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTO_DISABLE</name>
|
|
<description>Auto Disables the counter (set ENABLE to 0) when the count reaches 0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO_DEACTIVATE</name>
|
|
<description>Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ENB</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATUS_SEL</name>
|
|
<description>Counter Status Selection</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DONE</name>
|
|
<description>Single cycle pulse when the counter reaches 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Returns the counter ACTIVE bit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMA</name>
|
|
<description>Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMB</name>
|
|
<description>Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Returns the counter ENABLED bit</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMA_ACTIVE</name>
|
|
<description>Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATUS_INV</name>
|
|
<description>Invert the Output Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REQ_STOP</name>
|
|
<description>Stop Request</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RST_VALUE</name>
|
|
<description>The value that counter start from after reaching 0.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>CNT_VALUE</name>
|
|
<description>The current value of the counter</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE</name>
|
|
<description>Alternate access to the Counter ENABLE bit in the CTRL Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Counter Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSD_CTRL</name>
|
|
<description>The Cascade Control Register. Controls the counter external enable signals</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CSDEN0</name>
|
|
<description>Cascade 0 Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDINV0</name>
|
|
<description>Cascade 0 Invert</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDEN1</name>
|
|
<description>Cascade 1 Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDINV1</name>
|
|
<description>Cascade 1 Invert</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCASOP</name>
|
|
<description>Dual Cascade Operation (0:AND, 1:OR)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDTRG0</name>
|
|
<description>Cascade 0 Enabled as Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDTRG1</name>
|
|
<description>Cascade 1 Enabled as Trigger</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDEN2</name>
|
|
<description>Cascade 2 Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDINV2</name>
|
|
<description>Cascade 2 Invert</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CSDTRG2</name>
|
|
<description>Cascade 2 Trigger mode</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CASCADE0</name>
|
|
<description>Cascade Enable Selection</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CASSEL</name>
|
|
<description>Cascade Selection</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="CASCADE0">
|
|
<name>CASCADE1</name>
|
|
<description>Cascade Enable Selection</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
</register>
|
|
<register derivedFrom="CASCADE0">
|
|
<name>CASCADE2</name>
|
|
<description>Cascade Enable Selection</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PWM_VALUE</name>
|
|
<description>The Pulse Width Modulation Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PWMA_VALUE</name>
|
|
<description>The Pulse Width Modulation ValueA</description>
|
|
<alternateRegister>PWM_VALUE</alternateRegister>
|
|
<addressOffset>0x20</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PWMB_VALUE</name>
|
|
<description>The Pulse Width Modulation ValueB</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x021107E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM1</name>
|
|
<baseAddress>0x40018400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM2</name>
|
|
<baseAddress>0x40018800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM3</name>
|
|
<baseAddress>0x40018C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM4</name>
|
|
<baseAddress>0x40019000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM5</name>
|
|
<baseAddress>0x40019400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM6</name>
|
|
<baseAddress>0x40019800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM7</name>
|
|
<baseAddress>0x40019C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM8</name>
|
|
<baseAddress>0x4001A000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM9</name>
|
|
<baseAddress>0x4001A400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM10</name>
|
|
<baseAddress>0x4001A800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM11</name>
|
|
<baseAddress>0x4001AC00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM12</name>
|
|
<baseAddress>0x4001B000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM13</name>
|
|
<baseAddress>0x4001B400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM14</name>
|
|
<baseAddress>0x4001B800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM15</name>
|
|
<baseAddress>0x4001BC00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM16</name>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM17</name>
|
|
<baseAddress>0x40028400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM18</name>
|
|
<baseAddress>0x40028800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM19</name>
|
|
<baseAddress>0x40028C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM20</name>
|
|
<baseAddress>0x40029000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM21</name>
|
|
<baseAddress>0x40029400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM22</name>
|
|
<baseAddress>0x40029800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM0">
|
|
<name>TIM23</name>
|
|
<baseAddress>0x40029C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<version>1.0</version>
|
|
<description>UART Peripheral</description>
|
|
<groupName>UART</groupName>
|
|
<headerStructName>UART</headerStructName>
|
|
<baseAddress>0x40024000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0_TX</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART0_RX</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART1_TX</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART1_RX</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART2_TX</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>UART2_RX</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data In/Out Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE</name>
|
|
<description>Enable Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXENABLE</name>
|
|
<description>Rx Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXENABLE</name>
|
|
<description>Tx Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAREN</name>
|
|
<description>Parity Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PAREVEN</name>
|
|
<description>Parity Even/Odd(1/0)</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARSTK</name>
|
|
<description>Parity Sticky</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STOPBITS</name>
|
|
<description>Stop Bits 1/2(0/1)</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WORDSIZE</name>
|
|
<description>Word Size in Bits 5/6/7/8(00/01/10/11)</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBACK</name>
|
|
<description>Loopback Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBACKBLK</name>
|
|
<description>Loopback Block</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCTS</name>
|
|
<description>Enable Auto CTS mode</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEFRTS</name>
|
|
<description>Default RTSn value</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTORTS</name>
|
|
<description>Enable Auto RTS mode</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BAUD8</name>
|
|
<description>Enable BAUD8 mode</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKSCALE</name>
|
|
<description>Clock Scale Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRAC</name>
|
|
<description>Fractional Divide (64ths)</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Integer Divide</description>
|
|
<bitRange>[23:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Reset Baud Counter</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXSTATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDAVL</name>
|
|
<description>Read Data Available</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDNFULL</name>
|
|
<description>Read Fifo NOT Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXBUSY</name>
|
|
<description>RX Busy Receiving</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXTO</name>
|
|
<description>RX Receive Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOVR</name>
|
|
<description>Read Fifo Overflow</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFRM</name>
|
|
<description>RX Framing Error</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXPAR</name>
|
|
<description>RX Parity Error</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>RX Break Error</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXBUSYBRK</name>
|
|
<description>RX Busy Receiving Break</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXADDR9</name>
|
|
<description>Address Match for 9 bit mode</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSN</name>
|
|
<description>RX RTSn Output Value</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXSTATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRRDY</name>
|
|
<description>Write Fifo NOT Full</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WRBUSY</name>
|
|
<description>Write Fifo Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXBUSY</name>
|
|
<description>TX Busy Transmitting</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WRLOST</name>
|
|
<description>Write Data Lost (Fifo Overflow)</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSN</name>
|
|
<description>TX CTSn Input Value</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_CLR</name>
|
|
<description>Clear FIFO Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Clear Rx FIFO</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Clear Tx FIFO</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBREAK</name>
|
|
<description>Break Transmit Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ADDR9</name>
|
|
<description>Address9 Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ADDR9MASK</name>
|
|
<description>Address9 Mask Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_ENB</name>
|
|
<description>IRQ Enable Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_RX</name>
|
|
<description>RX Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_RX_STATUS</name>
|
|
<description>RX Status Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_RX_TO</name>
|
|
<description>RX Timeout Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TX</name>
|
|
<description>TX Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TX_STATUS</name>
|
|
<description>TX Status Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TX_EMPTY</name>
|
|
<description>TX Empty Interrupt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TX_CTS</name>
|
|
<description>TX CTS Change Interrupt</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_RAW</name>
|
|
<description>IRQ Raw Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_END</name>
|
|
<description>IRQ Enabled Status Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_CLR</name>
|
|
<description>IRQ Clear Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOIRQTRG</name>
|
|
<description>Rx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFOIRQTRG</name>
|
|
<description>Tx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFORTSTRG</name>
|
|
<description>Rx FIFO RTS Trigger Level</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>Internal STATE of UART Controller</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x021207E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART1</name>
|
|
<baseAddress>0x40025000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART2</name>
|
|
<baseAddress>0x40017000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<version>1.0</version>
|
|
<description>SPI Peripheral</description>
|
|
<groupName>SPI</groupName>
|
|
<headerStructName>SPI</headerStructName>
|
|
<baseAddress>0x40015000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0_TX</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI0_RX</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI1_TX</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI1_RX</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI2_TX</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI2_RX</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI3_TX</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPI3_RX</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL0</name>
|
|
<description>Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Data Size(0x3=>4, 0xf=>16)</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPO</name>
|
|
<description>SPI Clock Polarity</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPH</name>
|
|
<description>SPI Clock Phase</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCRDV</name>
|
|
<description>Serial Clock Rate divide+1 value</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL1</name>
|
|
<description>Control Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>Loop Back</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave (0:Master, 1:Slave)</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOD</name>
|
|
<description>Slave output Disable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SS</name>
|
|
<description>Slave Select</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BLOCKMODE</name>
|
|
<description>Block Mode Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BMSTART</name>
|
|
<description>Block Mode Start Status Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BMSTALL</name>
|
|
<description>Block Mode Stall Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MDLYCAP</name>
|
|
<description>Master Delayed Capture Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MTXPAUSE</name>
|
|
<description>Master Tx Pause Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data Input/Output</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TNF</name>
|
|
<description>Transmit FIFO not full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RNE</name>
|
|
<description>Receive FIFO not empty</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO Full</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAFIRST</name>
|
|
<description>Pending Data is first Byte in BLOCKMODE</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGGER</name>
|
|
<description>RX FIFO Above Trigger Level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIGGER</name>
|
|
<description>TX FIFO Below Trigger Level</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKPRESCALE</name>
|
|
<description>Clock Pre Scale divide value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_ENB</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RORIM</name>
|
|
<description>RX Overrun</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>RX Timeout</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>RX Fifo is at least half full</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>TX Fifo is at least half empty</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_RAW</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_END</name>
|
|
<description>Enabled Interrupt Status Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_CLR</name>
|
|
<description>Clear Interrupt Status Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>write-only</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOIRQTRG</name>
|
|
<description>Rx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFOIRQTRG</name>
|
|
<description>Tx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_CLR</name>
|
|
<description>Clear FIFO Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Clear Rx FIFO</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Clear Tx FIFO</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>Internal STATE of SPI Controller</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x021307E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI1</name>
|
|
<baseAddress>0x40015400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI2</name>
|
|
<baseAddress>0x40015800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI3</name>
|
|
<baseAddress>0x40015C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<version>1.0</version>
|
|
<description>I2C Peripheral</description>
|
|
<groupName>I2C</groupName>
|
|
<headerStructName>I2C</headerStructName>
|
|
<baseAddress>0x40016000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0_MS</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C0_SL</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_MS</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_SL</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_MS</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_SL</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C0_MS_RX</name>
|
|
<value>182</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C0_MS_TX</name>
|
|
<value>183</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C0_SL_RX</name>
|
|
<value>184</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C0_SL_TX</name>
|
|
<value>185</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_MS_RX</name>
|
|
<value>186</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_MS_TX</name>
|
|
<value>187</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_SL_RX</name>
|
|
<value>188</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_SL_TX</name>
|
|
<value>189</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_MS_RX</name>
|
|
<value>190</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_MS_TX</name>
|
|
<value>191</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_SL_RX</name>
|
|
<value>192</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_SL_TX</name>
|
|
<value>193</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLKENABLED</name>
|
|
<description>I2C CLK Enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLED</name>
|
|
<description>I2C Activated</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>I2C Active</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMD</name>
|
|
<description>TX FIFIO Empty Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFFMD</name>
|
|
<description>RX FIFO Full Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ALGFILTER</name>
|
|
<description>Enable Input Analog Glitch Filter</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DLGFILTER</name>
|
|
<description>Enable Input Digital Glitch Filter</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBACK</name>
|
|
<description>Enable LoopBack Mode</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMCONFIGENB</name>
|
|
<description>Enable Timing Config Register</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKSCALE</name>
|
|
<description>Clock Scale divide value</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Enable FastMode</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FASTMODE</name>
|
|
<description>Enable FastMode</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WORDS</name>
|
|
<description>Word Count value</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>ADDRESS</name>
|
|
<description>I2C Address value</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data Input/Output</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>I2C Controller Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2CIDLE</name>
|
|
<description>I2C bus is idle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>I2C controller is Idle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAITING</name>
|
|
<description>Controller is Waiting</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STALLED</name>
|
|
<description>Controller is Stalled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>I2C Arbitration was lost</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NACKADDR</name>
|
|
<description>I2C Address was not Acknowledged</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NACKDATA</name>
|
|
<description>I2C Data was not Acknowledged</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNEMPTY</name>
|
|
<description>RX FIFO is Not Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO is Full</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGGER</name>
|
|
<description>RX FIFO Above Trigger Level</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TX FIFO is Empty</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXNFULL</name>
|
|
<description>TX FIFO is Full</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIGGER</name>
|
|
<description>TX FIFO Below Trigger Level</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAW_SDA</name>
|
|
<description>I2C Raw SDA value</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAW_SCL</name>
|
|
<description>I2C Raw SCL value</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>Internal STATE of I2C Master Controller</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>TXCOUNT</name>
|
|
<description>TX Count Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT</name>
|
|
<description>RX Count Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_ENB</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2CIDLE</name>
|
|
<description>I2C Bus is Idle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Controller is Idle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAITING</name>
|
|
<description>Controller is Waiting</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STALLED</name>
|
|
<description>Controller is Stalled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>I2C Arbitration was lost</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NACKADDR</name>
|
|
<description>I2C Address was not Acknowledged</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NACKDATA</name>
|
|
<description>I2C Data was not Acknowledged</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKLOTO</name>
|
|
<description>I2C Clock Low Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXOVERFLOW</name>
|
|
<description>TX FIFO Overflowed</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOVERFLOW</name>
|
|
<description>TX FIFO Overflowed</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXREADY</name>
|
|
<description>TX FIFO Ready</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXREADY</name>
|
|
<description>RX FIFO Ready</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TX FIFO Empty</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO Full</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_RAW</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_END</name>
|
|
<description>Enabled Interrupt Status Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register derivedFrom="IRQ_ENB">
|
|
<name>IRQ_CLR</name>
|
|
<description>Clear Interrupt Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<access>write-only</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOIRQTRG</name>
|
|
<description>Rx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFOIRQTRG</name>
|
|
<description>Tx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_CLR</name>
|
|
<description>Clear FIFO Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Clear Rx FIFO</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Clear Tx FIFO</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMCONFIG</name>
|
|
<description>Timing Config Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>CLKTOLIMIT</name>
|
|
<description>Clock Low Timeout Limit Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>S0_CTRL</name>
|
|
<description>Slave Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLKENABLED</name>
|
|
<description>I2C Enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLED</name>
|
|
<description>I2C Activated</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>I2C Active</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMD</name>
|
|
<description>TX FIFIO Empty Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFFMD</name>
|
|
<description>RX FIFO Full Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_MAXWORDS</name>
|
|
<description>Slave MaxWords Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAXWORD</name>
|
|
<description>Max Word Count</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the max word count</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_ADDRESS</name>
|
|
<description>Slave I2C Address Value</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>A10MODE</name>
|
|
<description>Enable 10b address mode</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address value</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RW</name>
|
|
<description>Read/Write value</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_ADDRESSMASK</name>
|
|
<description>Slave I2C Address Mask value</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Address mask value</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RWMASK</name>
|
|
<description>Read/Write mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_DATA</name>
|
|
<description>Slave Data Input/Output</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>I2C data value</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_LASTADDRESS</name>
|
|
<description>Slave I2C Last Address value</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address value</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRECTION</name>
|
|
<description>Transaction direction 0=master send, 1=master receive</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_STATUS</name>
|
|
<description>Slave I2C Controller Status Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMPLETED</name>
|
|
<description>Controller Complted a Transaction</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Controller is Idle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAITING</name>
|
|
<description>Controller is Waiting</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSTALLED</name>
|
|
<description>Controller is Tx Stalled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSTALLED</name>
|
|
<description>Controller is Rx Stalled</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESSMATCH</name>
|
|
<description>I2C Address Match</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NACKDATA</name>
|
|
<description>I2C Data was not Acknowledged</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAFIRST</name>
|
|
<description>Pending Data is first Byte following Address</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNEMPTY</name>
|
|
<description>RX FIFO is Not Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO is Full</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGGER</name>
|
|
<description>RX FIFO Above Trigger Level</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TX FIFO is Empty</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXNFULL</name>
|
|
<description>TX FIFO is Full</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIGGER</name>
|
|
<description>TX FIFO Below Trigger Level</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAW_BUSY</name>
|
|
<description>I2C Raw Busy value</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAW_SDA</name>
|
|
<description>I2C Raw SDA value</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAW_SCL</name>
|
|
<description>I2C Raw SCL value</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_STATE</name>
|
|
<description>Internal STATE of I2C Slave Controller</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>S0_TXCOUNT</name>
|
|
<description>Slave TX Count Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Count value</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_RXCOUNT</name>
|
|
<description>Slave RX Count Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Count value</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_IRQ_ENB</name>
|
|
<description>Slave Interrupt Enable Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMPLETED</name>
|
|
<description>Controller Complted a Transaction</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Controller is Idle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAITING</name>
|
|
<description>Controller is Waiting</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSTALLED</name>
|
|
<description>Controller is Tx Stalled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSTALLED</name>
|
|
<description>Controller is Rx Stalled</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESSMATCH</name>
|
|
<description>I2C Address Match</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NACKDATA</name>
|
|
<description>I2C Data was not Acknowledged</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAFIRST</name>
|
|
<description>Pending Data is first Byte following Address</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_START</name>
|
|
<description>I2C Start Condition</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_STOP</name>
|
|
<description>I2C Stop Condition</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERFLOW</name>
|
|
<description>TX FIFO Underflowed</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOVERFLOW</name>
|
|
<description>TX FIFO Overflowed</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXREADY</name>
|
|
<description>TX FIFO Ready</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXREADY</name>
|
|
<description>RX FIFO Ready</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPTY</name>
|
|
<description>TX FIFO Empty</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO Full</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="S0_IRQ_ENB">
|
|
<name>S0_IRQ_RAW</name>
|
|
<description>Slave Raw Interrupt Status Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register derivedFrom="S0_IRQ_ENB">
|
|
<name>S0_IRQ_END</name>
|
|
<description>Slave Enabled Interrupt Status Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register derivedFrom="S0_IRQ_ENB">
|
|
<name>S0_IRQ_CLR</name>
|
|
<description>Slave Clear Interrupt Status Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<access>write-only</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</register>
|
|
<register>
|
|
<name>S0_RXFIFOIRQTRG</name>
|
|
<description>Slave Rx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Half full level for the Rx FIFO</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_TXFIFOIRQTRG</name>
|
|
<description>Slave Tx FIFO IRQ Trigger Level</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Half full level for the Rx FIFO</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_FIFO_CLR</name>
|
|
<description>Slave Clear FIFO Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Clear Rx FIFO</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Clear Tx FIFO</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_ADDRESSB</name>
|
|
<description>Slave I2C Address B Value</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RW</name>
|
|
<description>Read write value</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address value</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESSBEN</name>
|
|
<description>Enable Address B</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S0_ADDRESSMASKB</name>
|
|
<description>Slave I2C Address B Mask value</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<resetValue>0x000007FE</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RWMASK</name>
|
|
<description>Read write mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Address mask value</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x021407E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C1</name>
|
|
<baseAddress>0x40016400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C2</name>
|
|
<baseAddress>0x40016800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAN0</name>
|
|
<version>1.0</version>
|
|
<description>CAN Peripheral</description>
|
|
<groupName>CAN</groupName>
|
|
<headerStructName>CAN</headerStructName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CAN0</name>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN1</name>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CNSTAT_CMB0</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB0</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB0</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB0</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB0</name>
|
|
<description>CAN Frame Data Word 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB0</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB0</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB0</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB1</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB1</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB1</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB1</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB1</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB1</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB1</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB1</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB2</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB2</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB2</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB2</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB2</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB2</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB2</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB2</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB3</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB3</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB3</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB3</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB3</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB3</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB3</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB3</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB4</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB4</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB4</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB4</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB4</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB4</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB4</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB4</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB5</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB5</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB5</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB5</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB5</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB5</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB5</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB5</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB6</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB6</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB6</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB6</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB6</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB6</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB6</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB6</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB7</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB7</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB7</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB7</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB7</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB7</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB7</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB7</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB8</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB8</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB8</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB8</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB8</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB8</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB8</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB8</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB9</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB9</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB9</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB9</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB9</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB9</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB9</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB9</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB10</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB10</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB10</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB10</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB10</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB10</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB10</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB10</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB11</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB11</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB11</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB11</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB11</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB11</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB11</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB11</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB12</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB12</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB12</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB12</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB12</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB12</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB12</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB12</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB13</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB13</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB13</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB13</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB13</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB13</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB13</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB13</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_CMB14</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_CMB14</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_CMB14</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_CMB14</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_CMB14</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_CMB14</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_CMB14</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_CMB14</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNSTAT_HCMB</name>
|
|
<description>Buffer Status / Control Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI</name>
|
|
<description>Transmit Priority Code</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Buffer Status</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTP_HCMB</name>
|
|
<description>CAN Frame Timestamp</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Timestamp</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA3_HCMB</name>
|
|
<description>CAN Frame Data Word 3</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE7</name>
|
|
<description>Data Byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE8</name>
|
|
<description>Data Byte 8</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA2_HCMB</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE5</name>
|
|
<description>Data Byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE6</name>
|
|
<description>Data Byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA1_HCMB</name>
|
|
<description>CAN Frame Data Word 2</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE3</name>
|
|
<description>Data Byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE4</name>
|
|
<description>Data Byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA0_HCMB</name>
|
|
<description>CAN Frame Data Word 0</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE1</name>
|
|
<description>Data Byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BYTE2</name>
|
|
<description>Data Byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID0_HCMB</name>
|
|
<description>CAN Frame Identifier Word 0</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID1_HCMB</name>
|
|
<description>CAN Frame Identifier Word 1</description>
|
|
<addressOffset>0x1FC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Half of CAN Frame ID. Format Varies for Standard or Extended Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CGCR</name>
|
|
<description>CAN Global Configuration Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EIT</name>
|
|
<description>Error Interrupt Type</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIAGEN</name>
|
|
<description>Diagnostic Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERNAL</name>
|
|
<description>Internal</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBACK</name>
|
|
<description>Loopback</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>Ignore Acknowledge</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LO</name>
|
|
<description>Listen Only</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DDIR</name>
|
|
<description>Data Direction</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSTPEN</name>
|
|
<description>Time Sync Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUFFLOCK</name>
|
|
<description>Buffer Lock</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CTX</name>
|
|
<description>RW,Control Transmit</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRX</name>
|
|
<description>RW,Control Receive</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CANEN</name>
|
|
<description>CAN Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIM</name>
|
|
<description>CAN Timing Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler Configuration</description>
|
|
<bitRange>[15:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>Synchronization Jump Width</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEG1</name>
|
|
<description>Time Segment 1</description>
|
|
<bitRange>[6:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEG2</name>
|
|
<description>Time Segment 2</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GMSKX</name>
|
|
<description>CAN Global Mask Extension</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GM</name>
|
|
<description>GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard</description>
|
|
<bitRange>[15:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>XRTR</name>
|
|
<description>Extended Remote transmission Request Bit</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GMSKB</name>
|
|
<description>CAN Global Mask Base</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GM1</name>
|
|
<description>GM[28:18] - ID[10:0] in standard, ID[28:18] in extended</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTR</name>
|
|
<description>Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDE</name>
|
|
<description>Identifier Extension Bit</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GM0</name>
|
|
<description>GM[17:15] - Unused in standard, ID[17:15] in extended</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMSKX</name>
|
|
<description>CAN Basic Mask Extension</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BM</name>
|
|
<description>BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard</description>
|
|
<bitRange>[15:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>XRTR</name>
|
|
<description>Extended Remote transmission Request Bit</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMSKB</name>
|
|
<description>CAN Basic Mask Base</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BM1</name>
|
|
<description>BM[28:18] - ID[10:0] in standard, ID[28:18] in extended</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTR</name>
|
|
<description>Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDE</name>
|
|
<description>Identifier Extension Bit</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BM0</name>
|
|
<description>BM[17:15] - Unused in standard, ID[17:15] in extended</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIEN</name>
|
|
<description>CAN Interrupt Enable Register</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EIEN</name>
|
|
<description>Error Interrupt Enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN</name>
|
|
<description>Buffer Interrupt Enable[14:0]</description>
|
|
<bitRange>[14:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIPND</name>
|
|
<description>CAN Interrupt Pending Register</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EIPND</name>
|
|
<description>Error Interrupt Pending</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IPND</name>
|
|
<description>Buffer Interrupt Pending[14:0]</description>
|
|
<bitRange>[14:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CICLR</name>
|
|
<description>CAN Interrupt Clear Register</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EICLR</name>
|
|
<description>Error Interrupt Clear</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICLR</name>
|
|
<description>Buffer Interrupt Clear[14:0]</description>
|
|
<bitRange>[14:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CICEN</name>
|
|
<description>CAN Interrupt Code Enable Register</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EICEN</name>
|
|
<description>Error Interrupt Code Enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICEN</name>
|
|
<description>Buffer Interrupt Code Enable[14:0]</description>
|
|
<bitRange>[14:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSTPND</name>
|
|
<description>CAN Status Pending Register</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NS</name>
|
|
<description>CAN Node Status</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Interrupt Request portion of Interrupt Code</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IST</name>
|
|
<description>Interrupt Source portion of Interrupt Code</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANEC</name>
|
|
<description>CAN Error Counter Register</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Receive Error Counter</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TEC</name>
|
|
<description>Transmit Error Counter</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CEDIAG</name>
|
|
<description>CAN Error Diagnostic Register</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVE</name>
|
|
<description>Drive</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MON</name>
|
|
<description>Monitor</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>CRC</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STUFF</name>
|
|
<description>Stuff Error</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmit Error</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EBID</name>
|
|
<description>Error Bit Identifier</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EFID</name>
|
|
<description>Error Field Identifier</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTMR</name>
|
|
<description>CAN Timer Register</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTMR</name>
|
|
<description>Time Stamp Counter</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="CAN0">
|
|
<name>CAN1</name>
|
|
<baseAddress>0x40014400</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<version>1.0</version>
|
|
<description>Analog to Digital Converter Peripheral</description>
|
|
<groupName>ADC</groupName>
|
|
<headerStructName>ADC</headerStructName>
|
|
<baseAddress>0x40022000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CONV_CNT</name>
|
|
<description>Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MANUAL_TRIG</name>
|
|
<description>Starts analog acquisition</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EXT_TRIG_EN</name>
|
|
<description>Allows the external trigger to start analog acquisition</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SWEEP_EN</name>
|
|
<description>ADC data acquisition for all enabled channel</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHAN_TAG_EN</name>
|
|
<description>Enables the channel tag to be saved with the ADC data</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHAN_EN</name>
|
|
<description>Enables the channel for data collection</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_DATA</name>
|
|
<description>FIFO data</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHAN_TAG</name>
|
|
<description>If enabled, this will include the number of the channel corresponding to the measurement</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DATA</name>
|
|
<description>ADC acquisition data from the FIFO</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_BUSY</name>
|
|
<description>Indicates an ADC data acquisition is in process</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_ENTRY_CNT</name>
|
|
<description>Indicates the number of entries in the FIFO</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_ENB</name>
|
|
<description>Interrupt Enable</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DEPTH_TRIG</name>
|
|
<description>Enables the interrupt for the FIFO entry count meets or exceeds the trigger level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Enables the interrupt for a trigger error</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DONE</name>
|
|
<description>Enables the interrupt for an ADC data acquisition completion</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Enables the interrupt for a FIFO underflow</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Enables the interrupt for a FIFO overflow</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>Enables the interrupt for FIFO full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>Enables the interrupt for FIFO empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_RAW</name>
|
|
<description>Raw Interrupt Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DEPTH_TRIG</name>
|
|
<description>Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DONE</name>
|
|
<description>Indicates that a ADC conversion is done</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Indicates data was unavailable when a new trigger for ADC update is received</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Indicates a FIFO overflow occurred (FIFO was full when new data was written)</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>Indicates the FIFO is full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>Indicates the FIFO is empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_END</name>
|
|
<description>Enabled Interrupt Status</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DEPTH_TRIG</name>
|
|
<description>Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DONE</name>
|
|
<description>Indicates that a ADC conversion is done and the interrupt is enabled</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Indicates a FIFO underflow occurred and the interrupt is enabled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Indicates a FIFO overflow occurred and the interrupt is enabled</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>Indicates the FIFO is full and the interrupt is enabled</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>Indicates the FIFO is empty and the interrupt is enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_CLR</name>
|
|
<description>Clear Interrupt</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Clears the trigger error interrupt status. Always reads 0</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DONE</name>
|
|
<description>Clears the ADC done interrupt status. Always reads 0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Clears the FIFO underflow interrupt status. Always reads 0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Clears the FIFO overflow interrupt status. Always reads 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOIRQTRG</name>
|
|
<description>Receive FIFO Interrupt Trigger Value</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_CLR</name>
|
|
<description>FIFO Clear</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_CLR</name>
|
|
<description>Clears the ADC FIFO. Always reads 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x001907E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC0</name>
|
|
<version>1.0</version>
|
|
<description>Digital to Analog Converter Peripheral</description>
|
|
<groupName>DAC</groupName>
|
|
<headerStructName>DAC</headerStructName>
|
|
<baseAddress>0x40023000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x800</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC0</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DAC1</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL0</name>
|
|
<description>Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MAN_TRIG_EN</name>
|
|
<description>Enables manual trigger</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EXT_TRIG_EN</name>
|
|
<description>Enables external trigger</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL1</name>
|
|
<description>Control Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC_EN</name>
|
|
<description>Enables the DAC analog block</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_SETTLING</name>
|
|
<description>Sets the the amount of time in microseconds the control FSM waits for the DAC settling time</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_DATA</name>
|
|
<description>FIFO data</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data for FIFO write</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC_BUSY</name>
|
|
<description>Indicates a DAC data acquisition is in process</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_ENTRY_CNT</name>
|
|
<description>Indicates the number of entries in the FIFO</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_ENB</name>
|
|
<description>Interrupt Enable</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DEPTH_TRIG</name>
|
|
<description>Enables the interrupt for the FIFO entry count is less than or equal to the trigger level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Enables the interrupt for a trigger error</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_DONE</name>
|
|
<description>Enables the interrupt for a DAC data acquisition completion</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Enables the interrupt for a FIFO underflow</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Enables the interrupt for a FIFO overflow</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>Enables the interrupt for FIFO full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>Enables the interrupt for FIFO empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_RAW</name>
|
|
<description>Raw Interrupt Status</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000041</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DEPTH_TRIG</name>
|
|
<description>Indicates the FIFO entry count is less than or equal to the trigger level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_DONE</name>
|
|
<description>Indicates that a DAC conversion is done</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Indicates data was unavailable when a new trigger for DAC update is received</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Indicates a FIFO overflow occurred (FIFO was full when new data was written)</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>Indicates the FIFO is full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>Indicates the FIFO is empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_END</name>
|
|
<description>Enabled Interrupt Status</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_DEPTH_TRIG</name>
|
|
<description>Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_DONE</name>
|
|
<description>Indicates that a DAC conversion is done and the interrupt is enabled</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Indicates a FIFO underflow occurred and the interrupt is enabled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Indicates a FIFO overflow occurred and the interrupt is enabled</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>Indicates the FIFO is full and the interrupt is enabled</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>Indicates the FIFO is empty and the interrupt is enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_CLR</name>
|
|
<description>Clear Interrupt</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRIG_ERROR</name>
|
|
<description>Clears the trigger error interrupt status. Always reads 0</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_DONE</name>
|
|
<description>Clears the DAC done interrupt status. Always reads 0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_UFLOW</name>
|
|
<description>Clears the FIFO underflow interrupt status. Always reads 0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OFLOW</name>
|
|
<description>Clears the FIFO overflow interrupt status. Always reads 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFOIRQTRG</name>
|
|
<description>Receive FIFO Interrupt Trigger Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_CLR</name>
|
|
<description>FIFO Clear</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_CLR</name>
|
|
<description>Clears the DAC FIFO. Always reads 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0x7FC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x002007E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DAC0">
|
|
<name>DAC1</name>
|
|
<baseAddress>0x40023800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPW</name>
|
|
<version>1.0</version>
|
|
<description>SpaceWire Peripheral</description>
|
|
<groupName>SPW</groupName>
|
|
<headerStructName>SPW</headerStructName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SpW</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0xA2010004</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Reads as 1 if the RMAP command handler is available</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>Reads as 1 if unaligned writes are available for the receiver</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RC</name>
|
|
<description>Reads as 1 if RMAP CRC is enabled in the core</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NCH</name>
|
|
<description>Number of DMA Channels minus one</description>
|
|
<bitRange>[28:27]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PO</name>
|
|
<description>The number of available SpaceWire ports minus one</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>CCSDS/CCITT CRC-16</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Interrupt distribution available</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LE</name>
|
|
<description>Loop-back Enable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Selects the active port when the no port force bit is zero</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NP</name>
|
|
<description>Disable port force</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PNPA</name>
|
|
<description>SpW Plug-and-Play Available</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>If set only one RMAP buffer is used</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Enable RMAP command handler</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>SpW Plug-and-Play Enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TL</name>
|
|
<description>Transmitter Enable Lock Control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Time-code Flag Filter</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TR</name>
|
|
<description>Enable time-code receptions</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TT</name>
|
|
<description>Enable time-code transmissions</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LI</name>
|
|
<description>Generate interrupt when link error occurs</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TQ</name>
|
|
<description>Generate interrupt when a valid time-code is received</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Make complete reset of the SpaceWire node. Self-clearing</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Enable Promiscuous mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TI</name>
|
|
<description>The host can generate a tick by writing a one to this field</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AS</name>
|
|
<description>Automatically start the link when a NULL has been received</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Start the link</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LD</name>
|
|
<description>Disable the SpaceWire CODEC</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STS</name>
|
|
<description>Status/Interrupt Source Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x06400000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NRXD</name>
|
|
<description>Number of Receive Descriptors</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NTXD</name>
|
|
<description>Number of Transmit Descriptors</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Link State</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Active port</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EE</name>
|
|
<description>Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA</name>
|
|
<description>Packet is received with an invalid destination address field</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>A synchronization problem has occurred when receiving NChars</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity error has occurred</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DE</name>
|
|
<description>Disconnection error has occurred</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ER</name>
|
|
<description>Escape error has occurred</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Credit has occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TO</name>
|
|
<description>A new time count value was received</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEFADDR</name>
|
|
<description>Node Address Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FE</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEFMASK</name>
|
|
<description>8-bit default mask used for node identification on the SpaceWire network</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEFADDR</name>
|
|
<description>8-bit node address used for node identification on the SpaceWire network</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Divisor Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000909</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIVSTART</name>
|
|
<description>8-bit Clock divisor value used for the clock-divider during startup</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIVRUN</name>
|
|
<description>8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DKEY</name>
|
|
<description>Destination Key</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DESTKEY</name>
|
|
<description>RMAP destination key</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Time Code Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIRQ_END</name>
|
|
<description>The current value of the time control flags</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMECNT</name>
|
|
<description>The current value of the system time counter</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Timer and Disconnect Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DISCONNECT</name>
|
|
<description>Used to generate the 850 ns disconnect time period</description>
|
|
<bitRange>[21:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER64</name>
|
|
<description>Used to generate the 6.4 and 12.8 us time periods</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTRL0</name>
|
|
<description>DMA Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTNUM</name>
|
|
<description>Interrupt number used for this channel</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP</name>
|
|
<description>EEP Termination</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TR</name>
|
|
<description>Truncated</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt code transmit enable on EEP</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IT</name>
|
|
<description>Interrupt code transmit enable on truncation</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Receive Packet IRQ</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TP</name>
|
|
<description>Transmit Packet IRQ</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TL</name>
|
|
<description>Transmit Enable Lock</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LE</name>
|
|
<description>Disable transmitter when a link error occurs</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>Strip PID</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>Strip Address</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable Address</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NS</name>
|
|
<description>If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Indicates to the GRSPW that there are enabled descriptors in the descriptor table</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>Reception to the DMA channel is currently active</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AT</name>
|
|
<description>Abort the currently transmitting packet and disable transmissions</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>An error response was detected on the AHB bus - DMA receive</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TA</name>
|
|
<description>An error response was detected on the AHB bus - DMA transmit</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Set each time a packet has been received</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Set each time a packet has been sent</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AI</name>
|
|
<description>An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>An interrupt will be generated each time a packet has been received</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TI</name>
|
|
<description>An interrupt will be generated each time a packet is transmitted</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Packets are allowed to be received to this channel</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Write a one to this bit each time new descriptors are activated in the table</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAMAXLEN0</name>
|
|
<description>DMA RX Maximum Length Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXMAXLEN</name>
|
|
<description>Receiver packet maximum length in bytes</description>
|
|
<bitRange>[24:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMATXDESC0</name>
|
|
<description>DMA Transmitter Descriptor Table Address Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DESCBASEADDR</name>
|
|
<description>Sets the base address of the descriptor table</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DESCSEL</name>
|
|
<description>Offset into the descriptor table</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMARXDESC0</name>
|
|
<description>DMA Receiver Table Destination Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DESCBASEADDR</name>
|
|
<description>Sets the base address of the descriptor table</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DESCSEL</name>
|
|
<description>Offset into the descriptor table</description>
|
|
<bitRange>[9:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR0</name>
|
|
<description>DMA Receiver Table Address Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IRQ_ROUTER</name>
|
|
<version>1.0</version>
|
|
<description>Interrupt Router Peripheral</description>
|
|
<headerStructName>IRQ</headerStructName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>U0</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U1</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U2</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U3</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U4</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U5</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U6</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U7</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U8</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U9</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U10</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U11</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U12</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U13</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U14</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U15</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U37</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U39</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U73</name>
|
|
<value>73</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>U75</name>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>FPU</name>
|
|
<value>194</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TXEV</name>
|
|
<value>195</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DMASEL0</name>
|
|
<description>Interrupt select for DMA channel 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000007F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMASEL</name>
|
|
<description>DMA trigger source selection value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMASEL1</name>
|
|
<description>Interrupt select for DMA channel 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000007F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMASEL</name>
|
|
<description>DMA trigger source selection value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMASEL2</name>
|
|
<description>Interrupt select for DMA channel 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000007F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMASEL</name>
|
|
<description>DMA trigger source selection value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMASEL3</name>
|
|
<description>Interrupt select for DMA channel 3</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000007F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMASEL</name>
|
|
<description>DMA trigger source selection value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMATTSEL</name>
|
|
<description>Trigger select for the DMA channels</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMATTSEL</name>
|
|
<description>DMA trigger type selection value</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCSEL</name>
|
|
<description>Interrupt select for ADC</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADCSEL</name>
|
|
<description>ADC trigger source selection value</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACSEL0</name>
|
|
<description>Interrupt select for DAC0</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACSEL</name>
|
|
<description>DAC trigger source selection value</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACSEL1</name>
|
|
<description>Interrupt select for DAC1</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACSEL</name>
|
|
<description>DAC trigger source selection value</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_OUT0</name>
|
|
<description>DEBUG IRQ_OUT[31:0]</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_OUT0</name>
|
|
<description>IRQ_OUT[31:0]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_OUT1</name>
|
|
<description>DEBUG IRQ_OUT[63:32]</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_OUT1</name>
|
|
<description>IRQ_OUT[63:32]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_OUT2</name>
|
|
<description>DEBUG IRQ_OUT[95:64]</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_OUT2</name>
|
|
<description>IRQ_OUT[95:64]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_OUT3</name>
|
|
<description>DEBUG IRQ_OUT[127:96]</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_OUT3</name>
|
|
<description>IRQ_OUT[127:96]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_OUT4</name>
|
|
<description>DEBUG IRQ_OUT[159:128]</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_OUT4</name>
|
|
<description>IRQ_OUT[159:128]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_OUT5</name>
|
|
<description>DEBUG IRQ_OUT[179:160]</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ_OUT5</name>
|
|
<description>IRQ_OUT[179:160]</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERID</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x028107E9</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WATCH_DOG</name>
|
|
<version>1.0</version>
|
|
<description>Watchdog Block Peripheral</description>
|
|
<headerStructName>WDOG</headerStructName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WATCHDOG</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>WDOGLOAD</name>
|
|
<description>Counter Start Value</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Count to load</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGVALUE</name>
|
|
<description>Down Counter Value</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Actual Count</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGCONTROL</name>
|
|
<description>Enable for block reset and interrupt</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESEN</name>
|
|
<description>Enable watchdog reset output</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Enable watchdog interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGINTCLR</name>
|
|
<description>A write of any value clears the WDT module interrupt, and reloads
|
|
the counter from the value in the WDOGLOAD Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Write any value to clear interrupt</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGRIS</name>
|
|
<description>Raw interrupt status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRUPT</name>
|
|
<description>Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGMIS</name>
|
|
<description>Interrupt status</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRUPT</name>
|
|
<description>Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGLOCK</name>
|
|
<description>Lock</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REG_WR_EN</name>
|
|
<description>Register write enable status</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGITCR</name>
|
|
<description>Integration test control</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEST_MODE_EN</name>
|
|
<description>Enable test mode of WDOGINT and WDOGRES</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGITOP</name>
|
|
<description>Integration test output set</description>
|
|
<addressOffset>0xF04</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDOGINT</name>
|
|
<description>Set output value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WDOGRES</name>
|
|
<description>Set output value</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPERIPHID0</name>
|
|
<description>Peripheral ID</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000024</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPERIPHID1</name>
|
|
<description>Peripheral ID</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B8</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPERIPHID2</name>
|
|
<description>Peripheral ID</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000001B</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPERIPHID3</name>
|
|
<description>Peripheral ID</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>Peripheral ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPCELLID0</name>
|
|
<description>PrimeCell ID</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCELLID</name>
|
|
<description>Prime Cell ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPCELLID1</name>
|
|
<description>PrimeCell ID</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000F0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCELLID</name>
|
|
<description>Prime Cell ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPCELLID2</name>
|
|
<description>PrimeCell ID</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCELLID</name>
|
|
<description>Prime Cell ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGPCELLID3</name>
|
|
<description>PrimeCell ID</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCELLID</name>
|
|
<description>Prime Cell ID</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<version>1.0</version>
|
|
<description>True Random Number Generator</description>
|
|
<headerStructName>TRNG</headerStructName>
|
|
<baseAddress>0x40027000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TRNG</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VN_ERR_INT_MASK</name>
|
|
<description>Mask the Von Neumann error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRNGT_ERR_INT_MASK</name>
|
|
<description>Mask the CRNGT error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCORR_ERR_INT_MASK</name>
|
|
<description>Mask the Autocorrelation error</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EHR_VALID_INT_MASK</name>
|
|
<description>Mask when the TRNG has collected 192 bits</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VN_ERR</name>
|
|
<description>Indicates a Von Neumann error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRNGT_ERR</name>
|
|
<description>Indicates a Continuous Random Number Generation Testing (CRNGT) error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCORR_ERR</name>
|
|
<description>Indicates that the Autocorrelation test failed four times in a row</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EHR_VALID</name>
|
|
<description>192 bits have been collected in the TRNG</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VN_ERR</name>
|
|
<description>Clears a Von Neumann error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRNGT_ERR</name>
|
|
<description>Clear a Continuous Random Number Generation Testing (CRNGT) error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCORR_ERR</name>
|
|
<description>Software cannot clear this bit. Only a TRNG reset can clear this bit</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EHR_VALID</name>
|
|
<description>Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RND_SRC_SEL</name>
|
|
<description>Selects the number of inverters (out of four possible selections) in the ring oscillator</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VALID</name>
|
|
<description>Valid Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EHR_VALID</name>
|
|
<description>Indicates that the collection of bits in the TRNG is complete</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EHR_DATA0</name>
|
|
<description>Entropy Holding Register Data Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EHR_DATA</name>
|
|
<description>32 Bits of Entropy Holding Register</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="EHR_DATA0">
|
|
<name>EHR_DATA1</name>
|
|
<description>Entropy Holding Register Data Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
</register>
|
|
<register derivedFrom="EHR_DATA0">
|
|
<name>EHR_DATA2</name>
|
|
<description>Entropy Holding Register Data Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
</register>
|
|
<register derivedFrom="EHR_DATA0">
|
|
<name>EHR_DATA3</name>
|
|
<description>Entropy Holding Register Data Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
</register>
|
|
<register derivedFrom="EHR_DATA0">
|
|
<name>EHR_DATA4</name>
|
|
<description>Entropy Holding Register Data Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
</register>
|
|
<register derivedFrom="EHR_DATA0">
|
|
<name>EHR_DATA5</name>
|
|
<description>Entropy Holding Register Data Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>RND_SOURCE_ENABLE</name>
|
|
<description>Random Source Enable Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RND_SRC_EN</name>
|
|
<description>The entropy source, ring oscillator, is enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMPLE_CNT1</name>
|
|
<description>Section TBD</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLE_CNTR1</name>
|
|
<description>Sets the number of clk cycles between two consecutive ring oscillator samples</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUTOCORR_STATISTIC</name>
|
|
<description>Auto-correlator Statistic Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOCORR_FAILS</name>
|
|
<description>Count each time an autocorrelation test fails</description>
|
|
<bitRange>[21:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCORR_TRYS</name>
|
|
<description>Count each time an autocorrelation test starts</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_CONTROL</name>
|
|
<description>Section TBD</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AUTO_CORRELATE_BYPASS</name>
|
|
<description>The autocorrelation test in the TRNG module is bypassed</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRNGT_BYPASS</name>
|
|
<description>The CRNGT test in the TRNG is bypassed</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VNC_PYPASS</name>
|
|
<description>The Von Neumann balancer is bypassed</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_RESET</name>
|
|
<description>Reset Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SW_RESET</name>
|
|
<description>Writing 1 to this register causes an internal TRNG reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSY</name>
|
|
<description>Busy Register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Reflects the status of the rng_busy signal</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RST_BITS_COUNTER</name>
|
|
<description>Reset Bits Counter Register</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RST_BITS_COUNTER</name>
|
|
<description>Writing any value to this bit resets the bits counter and TRNG valid registers</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BIST_CNTR0</name>
|
|
<description>BIST Counter Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ROSC_CNTR_VAL</name>
|
|
<description>Returns the results of the TRNG BIST counter</description>
|
|
<bitRange>[21:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="BIST_CNTR0">
|
|
<name>BIST_CNTR1</name>
|
|
<description>BIST Counter Register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
</register>
|
|
<register derivedFrom="BIST_CNTR0">
|
|
<name>BIST_CNTR2</name>
|
|
<description>BIST Counter Register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ETH</name>
|
|
<version>1.1</version>
|
|
<description>Ethernet Block</description>
|
|
<headerStructName>ETH</headerStructName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>Ethernet</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MAC_CONFIG</name>
|
|
<description>Operation mode register for the MAC</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WD</name>
|
|
<description>Watchdog disable</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JD</name>
|
|
<description>Jabber Disable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>Frame Burst Enable</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JE</name>
|
|
<description>Jumbo Frame Enable</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IFG</name>
|
|
<description>Inter-Frame Gap</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCRS</name>
|
|
<description>Disable Carrier Sense During Transmission</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Port Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FES</name>
|
|
<description>Speed</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRO</name>
|
|
<description>Disable Receive Own</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LM</name>
|
|
<description>Loopback Mode</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DM</name>
|
|
<description>Duplex Mode</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IPC</name>
|
|
<description>Checksum Offload</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Disable Retry</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACS</name>
|
|
<description>Automatic Pad, or CRC Stripping</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BL</name>
|
|
<description>Back-Off-Limit</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Deferral Check</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRELEN</name>
|
|
<description>Preamble Length for Transmit frames</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_FRAME_FLTR</name>
|
|
<description>Contains the frame filtering controls</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Receive All</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DNTU</name>
|
|
<description>Drop non TCP/UDP over IP Frames</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VFTE</name>
|
|
<description>VLAN Tag Filter Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HDF</name>
|
|
<description>Hash or Perfect Filter</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SAF</name>
|
|
<description>Source Address Filter Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SAIF</name>
|
|
<description>SA Inverse Filtering</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCF</name>
|
|
<description>Pass Control Frames</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DBF</name>
|
|
<description>Disable Broadcast Frames</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Pass All Multicast</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAIF</name>
|
|
<description>DA Inverse Filtering</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HMC</name>
|
|
<description>Hash Multicast</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HUC</name>
|
|
<description>Hash Unicast</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Promiscuous Mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_GMII_ADDR</name>
|
|
<description>Controls the management cycles to an external PHY</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Physical Layer Address</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GR</name>
|
|
<description>GMII Register</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR</name>
|
|
<description>CSR Clock Range</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GW</name>
|
|
<description>GMII Write/Read</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GB</name>
|
|
<description>GMII Busy</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_GMII_DATA</name>
|
|
<description>Contains the data to be written to or read from the PHY register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GD</name>
|
|
<description>GMII Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_FLOW_CTRL</name>
|
|
<description>Controls the generation of control frames</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Pause time</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DZPQ</name>
|
|
<description>Disable Zero-Quanta Pause</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PLT</name>
|
|
<description>Pause Low Threshold</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UP</name>
|
|
<description>Unicast Pause Frame Detect</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFE</name>
|
|
<description>Receive Flow Control Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit Flow Control Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FCB_BPA</name>
|
|
<description>Flow Control Busy or Backpressure Activate</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_VLAN_TAG</name>
|
|
<description>Identifies IEEE 802.1Q VLAN type frames</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ESVL</name>
|
|
<description>Enable S-VLAN</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VTIM</name>
|
|
<description>VLAN Tag Inverse Match Enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETV</name>
|
|
<description>Enable 12-Bit VLAN Tag Comparison</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VL</name>
|
|
<description>VLAN Tag identifier for Receive Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_DEBUG</name>
|
|
<description>Gives the status of the various internal blocks for debugging</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXSTSFSTS</name>
|
|
<description>MTL TxStatus FIFO Full Status</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFSTS</name>
|
|
<description>MTL Tx FIFO Not Empty Status</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TWCSTS</name>
|
|
<description>MTL Tx FIFO Write Controller Status</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRCSTS</name>
|
|
<description>MTL Tx FIFO Read Controller Status</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPAUSED</name>
|
|
<description>MAC Transmitter in Pause</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TFCSTS</name>
|
|
<description>PAC Transmit Frame Controller Status</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TPESTS</name>
|
|
<description>MAC GMII or MII Transmit Protocol Engine Status</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFSTS</name>
|
|
<description>MTL RxFIFO Fill-Level Status</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RRCSTS</name>
|
|
<description>MTL RxFIFO Read Controller State</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RWCSTS</name>
|
|
<description>MTL Rx FIFO Write Controller Active Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFCFCSTS</name>
|
|
<description>MAC Receive Frame FIFO Controller Status</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RPESTS</name>
|
|
<description>MAC GMII or MII Receive Protocol Engine Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_INTR_STAT</name>
|
|
<description>Contains the interrupt status</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSIS</name>
|
|
<description>Timestamp Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MMCRXIPIS</name>
|
|
<description>MMC Receive Checksum Offload Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MMCTXIS</name>
|
|
<description>MMC Transmit Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MMCRXIS</name>
|
|
<description>MMC Receive Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MMCIS</name>
|
|
<description>MMC Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_INTR_MASK</name>
|
|
<description>Contains the masks for generating interrupt</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSIM</name>
|
|
<description>Timestamp Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR_H</name>
|
|
<description>Contains the high 16-bits of the first MAC Address</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AE</name>
|
|
<description>Address Enable, This bit is always set to 1</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDRHI</name>
|
|
<description>MAC Address0[47:32]</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR_L</name>
|
|
<description>Contains the Low 32-bits of the first MAC Address</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRLO</name>
|
|
<description>MAC Address0[31:0]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_WDOG_TO</name>
|
|
<description>Controls the watchdog time-out for received frames</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWE</name>
|
|
<description>Programmable Watchdog Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WTO</name>
|
|
<description>Watchdog Timeout</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMC_CNTRL</name>
|
|
<description>MMC Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UCDBC</name>
|
|
<description>Update MMC Counters for Dropped Broadcast Frames</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTPRSTLVL</name>
|
|
<description>Full-Half Preset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTPRST</name>
|
|
<description>Counters Preset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTFREEZ</name>
|
|
<description>MMC Counter Freeze</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTONRD</name>
|
|
<description>Reset on Read</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTSTOPRO</name>
|
|
<description>Counter Stop Rollover</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTRST</name>
|
|
<description>Counters Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMC_INTR_RX</name>
|
|
<description>MMC Receive Interrupt Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTRLFIS</name>
|
|
<description>MMC Receive Control Frame Counter Interrupt Status</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRCVERRFIS</name>
|
|
<description>MMC Receive Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXWDOGFIS</name>
|
|
<description>MMC Receive Watchdog Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXVLANGBFIS</name>
|
|
<description>MMC Receive VLAN Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFOVFIS</name>
|
|
<description>MMC Receive FIFO Overflow Frame Counter Interrupt Status</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXPAUSFIS</name>
|
|
<description>MMC Receive Pause Frame Counter Interrupt Status</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXORANGEFIS</name>
|
|
<description>MMC Receive Out Of Range Error Frame Counter Interrupt Status.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXLENERFIS</name>
|
|
<description>MMC Receive Length Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXUCGFIS</name>
|
|
<description>MMC Receive Unicast Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX1024TMAXOCTGBFIS</name>
|
|
<description>MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX512T1023OCTGBFIS</name>
|
|
<description>MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX256T511OCTGBFIS</name>
|
|
<description>MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX128T255OCTGBFIS</name>
|
|
<description>MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX65T127OCTGBFIS</name>
|
|
<description>MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX64OCTGBFIS</name>
|
|
<description>MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOSIZEGFIS</name>
|
|
<description>MMC Receive Oversize Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXUSIZEGFIS</name>
|
|
<description>MMC Receive Undersize Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXJABERFIS</name>
|
|
<description>MMC Receive Jabber Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRUNTFIS</name>
|
|
<description>MMC Receive Runt Frame Counter Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXALGNERFIS</name>
|
|
<description>MMC Receive Alignment Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXCRCERFIS</name>
|
|
<description>MMC Receive CRC Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXMCGFIS</name>
|
|
<description>MMC Receive Multicast Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXBCGFIS</name>
|
|
<description>MMC Receive Broadcast Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXGOCTIS</name>
|
|
<description>MMC Receive Good Octet Counter Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXGBOCTIS</name>
|
|
<description>MMC Receive Good Bad Octet Counter Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXGBFRMIS</name>
|
|
<description>MMC Receive Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMC_INTR_TX</name>
|
|
<description>MMC Transmit Interrupt Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXOSIZEGFIS</name>
|
|
<description>MMC Transmit Oversize Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXVLANGFIS</name>
|
|
<description>MMC Transmit VLAN Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPAUSFIS</name>
|
|
<description>MMC Transmit Pause Frame Counter Interrupt Status</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEXDEFFIS</name>
|
|
<description>MMC Transmit Excessive Deferral Frame Counter Interrupt Status</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGFRMIS</name>
|
|
<description>MMC Transmit Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGOCTIS</name>
|
|
<description>MMC Transmit Good Octet Counter Interrupt Status</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXCARERFIS</name>
|
|
<description>MMC Transmit Carrier Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEXCOLFIS</name>
|
|
<description>MMC Transmit Excessive Collision Frame Counter Interrupt Status</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXLATCOLFIS</name>
|
|
<description>MMC Transmit Late Collision Frame Counter Interrupt Status</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDEFFIS</name>
|
|
<description>MMC Transmit Deferred Frame Counter Interrupt Status</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMCOLGFIS</name>
|
|
<description>MMC Transmit Multiple Collision Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSCOLGFIS</name>
|
|
<description>MMC Transmit Single Collision Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUFLOWERFIS</name>
|
|
<description>MMC Transmit Underflow Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXBCGBFIS</name>
|
|
<description>MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMCGBFIS</name>
|
|
<description>MMC Transmit Multicast Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUCGBFIS</name>
|
|
<description>MMC Transmit Unicast Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX1024TMAXOCTGBFIS</name>
|
|
<description>MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX512T1023OCTGBFIS</name>
|
|
<description>MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX256T511OCTGBFIS</name>
|
|
<description>MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX128T255OCTGBFIS</name>
|
|
<description>MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX65T127OCTGBFIS</name>
|
|
<description>MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX64OCTGBFIS</name>
|
|
<description>MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMCGFIS</name>
|
|
<description>MMC Transmit Multicast Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXBCGFIS</name>
|
|
<description>MMC Transmit Broadcast Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGBFRMIS</name>
|
|
<description>MMC Transmit Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGBOCTIS</name>
|
|
<description>MMC Transmit Good Bad Octet Counter Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMC_INTR_MASK_RX</name>
|
|
<description>MMC Receive Interrupt Mask Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCTRLFIM</name>
|
|
<description>MMC Receive Control Frame Counter Interrupt Mask</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRCVERRFIM</name>
|
|
<description>MMC Receive Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXWDOGFIM</name>
|
|
<description>MMC Receive Watchdog Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXVLANGBFIM</name>
|
|
<description>MMC Receive VLAN Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFOVFIM</name>
|
|
<description>MMC Receive FIFO Overflow Frame Counter Interrupt Mask</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXPAUSFIM</name>
|
|
<description>MMC Receive Pause Frame Counter Interrupt Mask</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXORANGEFIM</name>
|
|
<description>MMC Receive Out Of Range Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXLENERFIM</name>
|
|
<description>MMC Receive Length Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXUCGFIM</name>
|
|
<description>MMC Receive Unicast Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX1024TMAXOCTGBFIM</name>
|
|
<description>MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX512T1023OCTGBFIM</name>
|
|
<description>MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX256T511OCTGBFIM</name>
|
|
<description>MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX128T255OCTGBFIM</name>
|
|
<description>MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX65T127OCTGBFIM</name>
|
|
<description>MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX64OCTGBFIM</name>
|
|
<description>MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOSIZEGFIM</name>
|
|
<description>MMC Receive Oversize Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXUSIZEGFIM</name>
|
|
<description>MMC Receive Undersize Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXJABERFIM</name>
|
|
<description>MMC Receive Jabber Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRUNTFIM</name>
|
|
<description>MMC Receive Runt Frame Counter Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXALGNERFIM</name>
|
|
<description>MMC Receive Alignment Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXCRCERFIM</name>
|
|
<description>MMC Receive CRC Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXMCGFIM</name>
|
|
<description>MMC Receive Multicast Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXBCGFIM</name>
|
|
<description>MMC Receive Broadcast Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXGOCTIM</name>
|
|
<description>MMC Receive Good Octet Counter Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXGBOCTIM</name>
|
|
<description>MMC Receive Good Bad Octet Counter Interrupt Mask.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXGBFRMIM</name>
|
|
<description>MMC Receive Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMC_INTR_MASK_TX</name>
|
|
<description>MMC Transmit Interrupt Mask Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXOSIZEGFIM</name>
|
|
<description>MMC Transmit Oversize Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXVLANGFIM</name>
|
|
<description>MMC Transmit VLAN Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPAUSFIM</name>
|
|
<description>MMC Transmit Pause Frame Counter Interrupt Mask</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEXDEFFIM</name>
|
|
<description>MMC Transmit Excessive Deferral Frame Counter Interrupt Mask</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGFRMIM</name>
|
|
<description>MMC Transmit Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGOCTIM</name>
|
|
<description>MMC Transmit Good Octet Counter Interrupt Mask</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXCARERFIM</name>
|
|
<description>MMC Transmit Carrier Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEXCOLFIM</name>
|
|
<description>MMC Transmit Excessive Collision Frame Counter Interrupt Mask</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXLATCOLFIM</name>
|
|
<description>MMC Transmit Late Collision Frame Counter Interrupt Mask</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDEFFIM</name>
|
|
<description>MMC Transmit Deferred Frame Counter Interrupt Mask</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMCOLGFIM</name>
|
|
<description>MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSCOLGFIM</name>
|
|
<description>MMC Transmit Single Collision Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUFLOWERFIM</name>
|
|
<description>MMC Transmit Underflow Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXBCGBFIM</name>
|
|
<description>MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMCGBFIM</name>
|
|
<description>MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUCGBFIM</name>
|
|
<description>MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX1024TMAXOCTGBFIM</name>
|
|
<description>MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX512T1023OCTGBFIM</name>
|
|
<description>MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX256T511OCTGBFIM</name>
|
|
<description>MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX128T255OCTGBFIM</name>
|
|
<description>MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX65T127OCTGBFIM</name>
|
|
<description>MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX64OCTGBFIM</name>
|
|
<description>MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMCGFIM</name>
|
|
<description>MMC Transmit Multicast Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXBCGFIM</name>
|
|
<description>MMC Transmit Broadcast Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGBFRMIM</name>
|
|
<description>MMC Transmit Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXGBOCTIM</name>
|
|
<description>MMC Transmit Good Bad Octet Counter Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXOCTETCOUNT_GB</name>
|
|
<description>MMC Transmit Count</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of bytes</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFRAMECOUNT_GB</name>
|
|
<description>MMC Frame Count Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBCASTFRAMES_G</name>
|
|
<description>MMC Good Broadcast Frames Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMCASTFRAMES_G</name>
|
|
<description>MMC Good Multicast Frames Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX64OCT_GB</name>
|
|
<description>MMC Good and bad Frames transmitted with length 64</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX65TO127OCT_GB</name>
|
|
<description>MMC Good and bad Frames transmitted with length 65 to 127</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX128TO255OCT_GB</name>
|
|
<description>MMC Good and bad Frames transmitted with length 128 to 255</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX256TO511OCT_GB</name>
|
|
<description>MMC Good and bad Frames transmitted with length 256 to 511</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX512TO1023OCT_GB</name>
|
|
<description>MMC Good and bad Frames transmitted with length 512 to 1023</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX1024MAXOCT_GB</name>
|
|
<description>MMC Good and bad Frames transmitted with length 1024 to max bytes</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXUCASTFRAME_GB</name>
|
|
<description>MMC number of good and bad unicast frames transmitted</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMCASTFRAME_GB</name>
|
|
<description>MMC number of good and bad MULTIcast frames transmitted</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBCASTFRAME_GB</name>
|
|
<description>MMC number of good and bad broadcast frames transmitted</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXUNDERERR</name>
|
|
<description>MMC number of frames aborted because of frame underflow error</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXSINGLECOL_G</name>
|
|
<description>MMC Number of successfully transmitted frames after a single collision</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMULTICOL_G</name>
|
|
<description>MMC Number of successfully transmitted frames after multiple collisions</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDEFERRED</name>
|
|
<description>MMC Number of successfully transmitted frames after a deferral</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXLATECOL</name>
|
|
<description>MMC Number of aborted frames because of late collision error</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXEXESSCOL</name>
|
|
<description>MMC Number of aborted frames because of excessive collision errors</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCARRIERERROR</name>
|
|
<description>MMC Number of aborted frames because of carrier sense error</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXOCTETCOUNT_G</name>
|
|
<description>MMC Number of bytes transmitted frames only in good frames</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of bytes</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFRAMECOUNT_G</name>
|
|
<description>MMC Number of good frames transmitted</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXEXCESSDEF</name>
|
|
<description>MMC Number of frames aborted because of excessive deferral error</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXPAUSEFRAMES</name>
|
|
<description>MMC Number of good pause frames transmitted</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXLANFRAMES_G</name>
|
|
<description>MMC Number of good VLAN frames transmitted</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXOVERSIZE_G</name>
|
|
<description>MMC Number of frames transmitted without errors</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFRAMECOUNT_GB</name>
|
|
<description>MMC Number of good and bad frames received</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXOCTETCOUNT_GB</name>
|
|
<description>MMC Number of bytes received in good and bad frames</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of bytes</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXOCTETCOUNT_G</name>
|
|
<description>MMC Number of bytes received in good frames only</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of bytes</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXBCASTFRAMES_G</name>
|
|
<description>MMC Number of good broadcast frames received</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMCASTFRAMES_G</name>
|
|
<description>MMC Number of good multicast frames received</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCRCERROR</name>
|
|
<description>MMC Number of frames received with CRC error</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXALIGNERROR</name>
|
|
<description>MMC Number of frames received with alignment error</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXRUNTERROR</name>
|
|
<description>MMC Number of frames received with runt error</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXJABBERERROR</name>
|
|
<description>MMC Number of giant frames received with length greater than 1518 bytes and with CRC error</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXUNDERSIZE_G</name>
|
|
<description>MMC Number of frames received with length less than 64 bytes</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXOVERSIZE_G</name>
|
|
<description>MMC Number of frames received without errors with length greater than the max size</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX64OCTETS_GB</name>
|
|
<description>MMC Number of good and bad frames received with length 64 bytes</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX65TO127OCT_GB</name>
|
|
<description>MMC Number of good and bad frames received with length between 65 and 127 bytes</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX128TO255OCT_GB</name>
|
|
<description>MMC Number of good and bad frames received with length between 128 and 255 bytes</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX256TO511OCT_GB</name>
|
|
<description>MMC Number of good and bad frames received with length between 256 and 511 bytes</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX512TO1023OCT_GB</name>
|
|
<description>MMC Number of good and bad frames received with length between 512 and 1023 bytes</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX1024MAXOCT_GB</name>
|
|
<description>MMC Number of good and bad frames received with length between 1024 and max size bytes</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXUCASTFRAMES_G</name>
|
|
<description>MMC Number of received good unicast frames</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXLENGTHERROR</name>
|
|
<description>MMC Number of frames received with length error</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXOUTRANGETYPE</name>
|
|
<description>MMC Number of frames received with length field not equal to the valid frame size</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPAUSEFRAMES</name>
|
|
<description>MMC Number of good and valid Pause frames received</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOOVERFLOW</name>
|
|
<description>MMC Number of missed received frames because of FIFO overflow</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXVLANFRAMES_GB</name>
|
|
<description>MMC Number of good and bad VLAN frames received</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXWDOGERROR</name>
|
|
<description>MMC Number of frames received with error because of watchdog timeout error</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXRCVERROR</name>
|
|
<description>MMC Number of frames received with Receive error or Frame Extension error</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCTRLFRAMES_G</name>
|
|
<description>MMC Number of received good control frames</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Number of frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VLAN_INCREPLACE</name>
|
|
<description>Holds the VLAN Tag for insertion into or replacement in the transmit frames</description>
|
|
<addressOffset>0x584</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSVL</name>
|
|
<description>C-VLAN or S-VLAN</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VLP</name>
|
|
<description>VLAN Priority Control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VLC</name>
|
|
<description>VLAN Tag Control in Transmit Frames</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VLT</name>
|
|
<description>VLAN Tag for Transmit Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VLAN_HASHTABLE</name>
|
|
<description>Holds the VLAN Hash Table</description>
|
|
<addressOffset>0x588</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VLHT</name>
|
|
<description>VLAN Hash Table</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP_CTRL</name>
|
|
<description>Controls the IEEE 1588 timestamp generation and update logic</description>
|
|
<addressOffset>0x700</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATSEN3</name>
|
|
<description>Auxiliary Snapshot 3 Enable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATSEN2</name>
|
|
<description>Auxiliary Snapshot 2 Enable</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATSEN1</name>
|
|
<description>Auxiliary Snapshot 1 Enable</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATSEN0</name>
|
|
<description>Auxiliary Snapshot 0 Enable</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATSFC</name>
|
|
<description>Auxiliary Snapshot FIFO Clear</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSENMACADDR</name>
|
|
<description>Enable MAC address for PTP Frame Filtering</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SNAPTYPSEL</name>
|
|
<description>Select PTP packets for Taking Snapshots</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSMSTRENA</name>
|
|
<description>Enable Snapshot for Messages Relevant to Master</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEVNTENA</name>
|
|
<description>Enable Timestamp Snapshot for Event Messages</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIPV4ENA</name>
|
|
<description>Enable Processing of PTP Frames Sent over IPv4-UDP</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIPV6ENA</name>
|
|
<description>Enable Processing of PTP Frames Sent over IPv6-UDP</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIPENA</name>
|
|
<description>Enable Processing of PTP over Ethernet Frames</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSVER2ENA</name>
|
|
<description>Enable PTP packet Processing for Version 2 Format</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSCTRLSSR</name>
|
|
<description>Timestamp Digital or Binary Rollover Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSENALL</name>
|
|
<description>Enable Timestamp for All Frames</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSADDRREG</name>
|
|
<description>Addend Reg Update</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSTRIG</name>
|
|
<description>Timestamp Interrupt Trigger Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSUPDT</name>
|
|
<description>Timestamp Update</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSINIT</name>
|
|
<description>Timestamp Initialize</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSCFUPDT</name>
|
|
<description>Timestamp Fine or Coarse Update</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSENA</name>
|
|
<description>Timestamp Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SUBSEC_INC</name>
|
|
<description>Holds the 8-bit value by which the Sub-Second register is incremented</description>
|
|
<addressOffset>0x704</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SSINC</name>
|
|
<description>Sub-Second Increment Valuee</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTIME_SECONDS</name>
|
|
<description>Holds the lower 32 bits of the second field of the system time</description>
|
|
<addressOffset>0x708</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSS</name>
|
|
<description>Timestamp Second</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTIME_NANOSEC</name>
|
|
<description>Holds 32 bits of the nano-second field of the system time</description>
|
|
<addressOffset>0x70C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSSS</name>
|
|
<description>Timestamp Sub Seconds</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTIME_SECSUPDAT</name>
|
|
<description>Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value</description>
|
|
<addressOffset>0x710</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSS</name>
|
|
<description>Timestamp Second</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTIME_NSECUP</name>
|
|
<description>Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value</description>
|
|
<addressOffset>0x714</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDSUB</name>
|
|
<description>Add or Subtract Time</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSSS</name>
|
|
<description>Timestamp Sub Seconds</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMPADDEND</name>
|
|
<description>This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency</description>
|
|
<addressOffset>0x718</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSAR</name>
|
|
<description>Timestamp Addend Register</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TARGET_TIME_SECS</name>
|
|
<description>Holds the high 32-bits of time to be compared with the system time</description>
|
|
<addressOffset>0x71C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSTR</name>
|
|
<description>Target Time Seconds Registe</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TARGET_TIME_NSEC</name>
|
|
<description>Holds the lower 32-bits of time to be compared with the system time</description>
|
|
<addressOffset>0x720</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGTBUSY</name>
|
|
<description>32 Bits of Hash Table</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TTSLO</name>
|
|
<description>Target Timestamp Low Register</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_BUS_MODE</name>
|
|
<description>Controls the DMA Host Interface Mode</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00020101</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RIB</name>
|
|
<description>Rebuild INCRx Burst</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRWG</name>
|
|
<description>Channel Priority Weights</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPR</name>
|
|
<description>Transmit Priority</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Mixed Burst</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAL</name>
|
|
<description>Address-Aligned Beats</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PBLx8</name>
|
|
<description>PBLx8 Mode</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USP</name>
|
|
<description>Use Separate PBL</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RPBL</name>
|
|
<description>Rx DMA PBL</description>
|
|
<bitRange>[22:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FB</name>
|
|
<description>Fixed Burste</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Priority Ratio</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PBL</name>
|
|
<description>Programmable Burst Lengthe</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DSL</name>
|
|
<description>Descriptor Skip Length</description>
|
|
<bitRange>[6:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DA</name>
|
|
<description>DMA Arbitration Scheme</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software Reset (Read, Write Set, and Self Clear)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_TX_POLL_DEMAND</name>
|
|
<description>Used by the host to instruct the DMA to poll the transmit Descriptor list</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TPD</name>
|
|
<description>Transmit Poll Demand (Read Only and Write Trigger)</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_RX_POLL_DEMAND</name>
|
|
<description>Used by the host to instruct the DMA to poll the Receive Descriptor list</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RPD</name>
|
|
<description>Receive Poll Demand (Read Only and Write Trigger)</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_RX_DESC_LIST_ADDR</name>
|
|
<description>Points the DMA to the start of the Receive Descriptor list</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDESLA</name>
|
|
<description>Start of Receive List</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_TX_DESC_LIST_ADDR</name>
|
|
<description>Points the DMA to the start of the Transmit Descriptor list</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDESLA</name>
|
|
<description>Start of Transmit List</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_STATUS</name>
|
|
<description>Used to determine the status of the DMA</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TTI</name>
|
|
<description>Timestamp Trigger Interrupt</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GMI</name>
|
|
<description>GMAC MMC Interrupt</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EB</name>
|
|
<description>Error Bits</description>
|
|
<bitRange>[25:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Transmit Process State</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Receive Process State</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NIS</name>
|
|
<description>Normal Interrupt Summary</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIS</name>
|
|
<description>Abnormal Interrupt Summary</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERI</name>
|
|
<description>Early Receive Interrupt</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBI</name>
|
|
<description>Fatal Bus Error Interruptble</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETI</name>
|
|
<description>Early Transmit Interrupt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RWT</name>
|
|
<description>Receive Watchdog Timeout</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RPS</name>
|
|
<description>Receive Process Stopped</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RU</name>
|
|
<description>Receive Buffer Unavailable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Receive Interrupt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UNF</name>
|
|
<description>Transmit Underflow</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Receive Underflow</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TJT</name>
|
|
<description>Transmit Jabber Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TU</name>
|
|
<description>Transmit Buffer Unavailable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TPS</name>
|
|
<description>Transmit Process Stopped</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TI</name>
|
|
<description>Transmit Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_OPER_MODE</name>
|
|
<description>Sets the Receive and Transmit operation mode and command</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Disable Dropping of TCP/IP Checksum Error Frames</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSF</name>
|
|
<description>Receive Store and Forward</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DFF</name>
|
|
<description>Disable Flushing of Received Frames</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSF</name>
|
|
<description>Transmit Store and Forward</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FTF</name>
|
|
<description>Flush Transmit FIFO</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TTC</name>
|
|
<description>Transmit Threshold Control</description>
|
|
<bitRange>[16:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Start or Stop Transmission Command</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFD</name>
|
|
<description>Threshold for Deactivating Flow Control</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFA</name>
|
|
<description>Threshold for Activating Flow Control</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>Forward Error Frames</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUF</name>
|
|
<description>Forward Undersized Good Frames</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DGF</name>
|
|
<description>Drop Giant Frames</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>Receive Threshold Control</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSF</name>
|
|
<description>Operate on Second Frame</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Start or Stop Receive</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INTR_EN</name>
|
|
<description>Enables the interrupts reported in the status register</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NIE</name>
|
|
<description>Normal Interrupt Summary Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIE</name>
|
|
<description>Abnormal Interrupt Summary Enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERE</name>
|
|
<description>Early Receive Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBE</name>
|
|
<description>Fatal Bus Error Enable</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETE</name>
|
|
<description>Early Transmit Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RWE</name>
|
|
<description>Receive Watchdog Timeout Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSE</name>
|
|
<description>Receive Stopped Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUE</name>
|
|
<description>Receive Buffer Unavailable Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UNE</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVE</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THE</name>
|
|
<description>Transmit Jabber Timeout Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TUE</name>
|
|
<description>Transmit Buffer Unavailable Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSE</name>
|
|
<description>Transmit Stopped Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_MISS_OVER_COUNTER</name>
|
|
<description>Contains the counters for discarded frames because no Receive Descriptor is available</description>
|
|
<addressOffset>0x1020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVFCNTOVF</name>
|
|
<description>This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVFFRMCNT</name>
|
|
<description>This field indicates the number of frames missed by the application</description>
|
|
<bitRange>[27:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MISCNTOVF</name>
|
|
<description>This bit is set every time Missed Frame Counter (Bits[15:0]) overflows</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MISFRMCNT</name>
|
|
<description>This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_RX_INTR_WDOG_TIMER</name>
|
|
<description>Watchdog timeout for Receive Interrupt from DMA</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RIWT</name>
|
|
<description>These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_AHB_STATUS</name>
|
|
<description>Provides the active status of the read and write channels of the AHB master interface</description>
|
|
<addressOffset>0x102C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AHBMASTRSTS</name>
|
|
<description>When high, indicates that the AHB master interface FSMs are in the non-idle state</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURR_TX_DESC</name>
|
|
<description>Contains the start address of the current Transmit Descriptor read by the DMA</description>
|
|
<addressOffset>0x1048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CURTDESAPTR</name>
|
|
<description>Cleared on Reset. Pointer updated by the DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURR_RX_DESC</name>
|
|
<description>Contains the start address of the current Receive Descriptor read by the DMA</description>
|
|
<addressOffset>0x104C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CURRDESAPTR</name>
|
|
<description>Cleared on Reset. Pointer updated by the DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURR_TX_BUFR_ADDR</name>
|
|
<description>Contains the start address of the current Receive Descriptor read by the DMA</description>
|
|
<addressOffset>0x1050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CURTBUFAPTR</name>
|
|
<description>Cleared on Reset. Pointer updated by the DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURR_RX_BUFR_ADDR</name>
|
|
<description>Contains the current Receive Buffer address read by the DMA</description>
|
|
<addressOffset>0x1054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CURTBUFAPTR</name>
|
|
<description>Cleared on Reset. Pointer updated by the DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> |