first building version of the PAC

src/sysconfig/adc_cal.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `ADC_CAL` reader"]
+pub struct R(crate::R<ADC_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ADC_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ADC_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ADC_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ADC_CAL` reader - ADC Calibration bits"]
+pub struct ADC_CAL_R(crate::FieldReader<u8, u8>);
+impl ADC_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADC_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADC_CAL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - ADC Calibration bits"]
+    #[inline(always)]
+    pub fn adc_cal(&self) -> ADC_CAL_R {
+        ADC_CAL_R::new((self.bits & 0x1f) as u8)
+    }
+}
+#[doc = "ADC Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adc_cal](index.html) module"]
+pub struct ADC_CAL_SPEC;
+impl crate::RegisterSpec for ADC_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [adc_cal::R](R) reader structure"]
+impl crate::Readable for ADC_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ADC_CAL to value 0"]
+impl crate::Resettable for ADC_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/analog_cntl.rs

@@ -0,0 +1,704 @@
+#[doc = "Register `ANALOG_CNTL` reader"]
+pub struct R(crate::R<ANALOG_CNTL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ANALOG_CNTL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ANALOG_CNTL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ANALOG_CNTL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ANALOG_CNTL` writer"]
+pub struct W(crate::W<ANALOG_CNTL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ANALOG_CNTL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ANALOG_CNTL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ANALOG_CNTL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TMOSC` reader - Test Mode"]
+pub struct TMOSC_R(crate::FieldReader<bool, bool>);
+impl TMOSC_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TMOSC_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TMOSC_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TMOSC` writer - Test Mode"]
+pub struct TMOSC_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TMOSC_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `TMPOKDIS` reader - Test Mode"]
+pub struct TMPOKDIS_R(crate::FieldReader<bool, bool>);
+impl TMPOKDIS_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TMPOKDIS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TMPOKDIS_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TMPOKDIS` writer - Test Mode"]
+pub struct TMPOKDIS_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TMPOKDIS_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `TM_ADCMUX_N` reader - Test Mode"]
+pub struct TM_ADCMUX_N_R(crate::FieldReader<bool, bool>);
+impl TM_ADCMUX_N_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TM_ADCMUX_N_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TM_ADCMUX_N_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TM_ADCMUX_N` writer - Test Mode"]
+pub struct TM_ADCMUX_N_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TM_ADCMUX_N_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `TM_ADCMUX_P` reader - Test Mode"]
+pub struct TM_ADCMUX_P_R(crate::FieldReader<bool, bool>);
+impl TM_ADCMUX_P_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TM_ADCMUX_P_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TM_ADCMUX_P_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TM_ADCMUX_P` writer - Test Mode"]
+pub struct TM_ADCMUX_P_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TM_ADCMUX_P_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `TMRATIO` reader - Test Mode"]
+pub struct TMRATIO_R(crate::FieldReader<bool, bool>);
+impl TMRATIO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TMRATIO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TMRATIO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TMRATIO` writer - Test Mode"]
+pub struct TMRATIO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TMRATIO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `TMATOMUX` reader - Test Mode"]
+pub struct TMATOMUX_R(crate::FieldReader<u8, u8>);
+impl TMATOMUX_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        TMATOMUX_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TMATOMUX_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TMATOMUX` writer - Test Mode"]
+pub struct TMATOMUX_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TMATOMUX_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5);
+        self.w
+    }
+}
+#[doc = "Field `ADC_STEST` reader - Number of clocks for sample time"]
+pub struct ADC_STEST_R(crate::FieldReader<u8, u8>);
+impl ADC_STEST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADC_STEST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADC_STEST_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADC_STEST` writer - Number of clocks for sample time"]
+pub struct ADC_STEST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADC_STEST_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x0f << 9)) | ((value as u32 & 0x0f) << 9);
+        self.w
+    }
+}
+#[doc = "Field `RCLK_POS_EN` reader - Enable normal test clock"]
+pub struct RCLK_POS_EN_R(crate::FieldReader<bool, bool>);
+impl RCLK_POS_EN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RCLK_POS_EN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RCLK_POS_EN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RCLK_POS_EN` writer - Enable normal test clock"]
+pub struct RCLK_POS_EN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RCLK_POS_EN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
+        self.w
+    }
+}
+#[doc = "Field `RCLK_NEG_EN` reader - Enable inverted test clock"]
+pub struct RCLK_NEG_EN_R(crate::FieldReader<bool, bool>);
+impl RCLK_NEG_EN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RCLK_NEG_EN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RCLK_NEG_EN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RCLK_NEG_EN` writer - Enable inverted test clock"]
+pub struct RCLK_NEG_EN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RCLK_NEG_EN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+        self.w
+    }
+}
+#[doc = "Field `APB2CLK_POS_EN` reader - Enable normal APB2CLK for test output"]
+pub struct APB2CLK_POS_EN_R(crate::FieldReader<bool, bool>);
+impl APB2CLK_POS_EN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        APB2CLK_POS_EN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for APB2CLK_POS_EN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `APB2CLK_POS_EN` writer - Enable normal APB2CLK for test output"]
+pub struct APB2CLK_POS_EN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> APB2CLK_POS_EN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Field `APB2CLK_NEG_EN` reader - Enable inverted APB2CLK for test output"]
+pub struct APB2CLK_NEG_EN_R(crate::FieldReader<bool, bool>);
+impl APB2CLK_NEG_EN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        APB2CLK_NEG_EN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for APB2CLK_NEG_EN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `APB2CLK_NEG_EN` writer - Enable inverted APB2CLK for test output"]
+pub struct APB2CLK_NEG_EN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> APB2CLK_NEG_EN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "Field `TM_ANALOG_PD_EN` reader - Enables pull down on analog pads"]
+pub struct TM_ANALOG_PD_EN_R(crate::FieldReader<bool, bool>);
+impl TM_ANALOG_PD_EN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TM_ANALOG_PD_EN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TM_ANALOG_PD_EN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TM_ANALOG_PD_EN` writer - Enables pull down on analog pads"]
+pub struct TM_ANALOG_PD_EN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TM_ANALOG_PD_EN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
+        self.w
+    }
+}
+#[doc = "Field `JMP2BOOT` reader - Enables a skip of all delay counters and eFuse read"]
+pub struct JMP2BOOT_R(crate::FieldReader<bool, bool>);
+impl JMP2BOOT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        JMP2BOOT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for JMP2BOOT_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `JMP2BOOT` writer - Enables a skip of all delay counters and eFuse read"]
+pub struct JMP2BOOT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> JMP2BOOT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
+        self.w
+    }
+}
+#[doc = "Field `SKIPBOOT` reader - Enables a skip of all delay counters, eFuse read, and boot"]
+pub struct SKIPBOOT_R(crate::FieldReader<bool, bool>);
+impl SKIPBOOT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SKIPBOOT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SKIPBOOT_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SKIPBOOT` writer - Enables a skip of all delay counters, eFuse read, and boot"]
+pub struct SKIPBOOT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SKIPBOOT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Test Mode"]
+    #[inline(always)]
+    pub fn tmosc(&self) -> TMOSC_R {
+        TMOSC_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Test Mode"]
+    #[inline(always)]
+    pub fn tmpokdis(&self) -> TMPOKDIS_R {
+        TMPOKDIS_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Test Mode"]
+    #[inline(always)]
+    pub fn tm_adcmux_n(&self) -> TM_ADCMUX_N_R {
+        TM_ADCMUX_N_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Test Mode"]
+    #[inline(always)]
+    pub fn tm_adcmux_p(&self) -> TM_ADCMUX_P_R {
+        TM_ADCMUX_P_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Test Mode"]
+    #[inline(always)]
+    pub fn tmratio(&self) -> TMRATIO_R {
+        TMRATIO_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bits 5:6 - Test Mode"]
+    #[inline(always)]
+    pub fn tmatomux(&self) -> TMATOMUX_R {
+        TMATOMUX_R::new(((self.bits >> 5) & 0x03) as u8)
+    }
+    #[doc = "Bits 9:12 - Number of clocks for sample time"]
+    #[inline(always)]
+    pub fn adc_stest(&self) -> ADC_STEST_R {
+        ADC_STEST_R::new(((self.bits >> 9) & 0x0f) as u8)
+    }
+    #[doc = "Bit 14 - Enable normal test clock"]
+    #[inline(always)]
+    pub fn rclk_pos_en(&self) -> RCLK_POS_EN_R {
+        RCLK_POS_EN_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - Enable inverted test clock"]
+    #[inline(always)]
+    pub fn rclk_neg_en(&self) -> RCLK_NEG_EN_R {
+        RCLK_NEG_EN_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - Enable normal APB2CLK for test output"]
+    #[inline(always)]
+    pub fn apb2clk_pos_en(&self) -> APB2CLK_POS_EN_R {
+        APB2CLK_POS_EN_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 17 - Enable inverted APB2CLK for test output"]
+    #[inline(always)]
+    pub fn apb2clk_neg_en(&self) -> APB2CLK_NEG_EN_R {
+        APB2CLK_NEG_EN_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 18 - Enables pull down on analog pads"]
+    #[inline(always)]
+    pub fn tm_analog_pd_en(&self) -> TM_ANALOG_PD_EN_R {
+        TM_ANALOG_PD_EN_R::new(((self.bits >> 18) & 0x01) != 0)
+    }
+    #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"]
+    #[inline(always)]
+    pub fn jmp2boot(&self) -> JMP2BOOT_R {
+        JMP2BOOT_R::new(((self.bits >> 19) & 0x01) != 0)
+    }
+    #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"]
+    #[inline(always)]
+    pub fn skipboot(&self) -> SKIPBOOT_R {
+        SKIPBOOT_R::new(((self.bits >> 20) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Test Mode"]
+    #[inline(always)]
+    pub fn tmosc(&mut self) -> TMOSC_W {
+        TMOSC_W { w: self }
+    }
+    #[doc = "Bit 1 - Test Mode"]
+    #[inline(always)]
+    pub fn tmpokdis(&mut self) -> TMPOKDIS_W {
+        TMPOKDIS_W { w: self }
+    }
+    #[doc = "Bit 2 - Test Mode"]
+    #[inline(always)]
+    pub fn tm_adcmux_n(&mut self) -> TM_ADCMUX_N_W {
+        TM_ADCMUX_N_W { w: self }
+    }
+    #[doc = "Bit 3 - Test Mode"]
+    #[inline(always)]
+    pub fn tm_adcmux_p(&mut self) -> TM_ADCMUX_P_W {
+        TM_ADCMUX_P_W { w: self }
+    }
+    #[doc = "Bit 4 - Test Mode"]
+    #[inline(always)]
+    pub fn tmratio(&mut self) -> TMRATIO_W {
+        TMRATIO_W { w: self }
+    }
+    #[doc = "Bits 5:6 - Test Mode"]
+    #[inline(always)]
+    pub fn tmatomux(&mut self) -> TMATOMUX_W {
+        TMATOMUX_W { w: self }
+    }
+    #[doc = "Bits 9:12 - Number of clocks for sample time"]
+    #[inline(always)]
+    pub fn adc_stest(&mut self) -> ADC_STEST_W {
+        ADC_STEST_W { w: self }
+    }
+    #[doc = "Bit 14 - Enable normal test clock"]
+    #[inline(always)]
+    pub fn rclk_pos_en(&mut self) -> RCLK_POS_EN_W {
+        RCLK_POS_EN_W { w: self }
+    }
+    #[doc = "Bit 15 - Enable inverted test clock"]
+    #[inline(always)]
+    pub fn rclk_neg_en(&mut self) -> RCLK_NEG_EN_W {
+        RCLK_NEG_EN_W { w: self }
+    }
+    #[doc = "Bit 16 - Enable normal APB2CLK for test output"]
+    #[inline(always)]
+    pub fn apb2clk_pos_en(&mut self) -> APB2CLK_POS_EN_W {
+        APB2CLK_POS_EN_W { w: self }
+    }
+    #[doc = "Bit 17 - Enable inverted APB2CLK for test output"]
+    #[inline(always)]
+    pub fn apb2clk_neg_en(&mut self) -> APB2CLK_NEG_EN_W {
+        APB2CLK_NEG_EN_W { w: self }
+    }
+    #[doc = "Bit 18 - Enables pull down on analog pads"]
+    #[inline(always)]
+    pub fn tm_analog_pd_en(&mut self) -> TM_ANALOG_PD_EN_W {
+        TM_ANALOG_PD_EN_W { w: self }
+    }
+    #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"]
+    #[inline(always)]
+    pub fn jmp2boot(&mut self) -> JMP2BOOT_W {
+        JMP2BOOT_W { w: self }
+    }
+    #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"]
+    #[inline(always)]
+    pub fn skipboot(&mut self) -> SKIPBOOT_W {
+        SKIPBOOT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Analog Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [analog_cntl](index.html) module"]
+pub struct ANALOG_CNTL_SPEC;
+impl crate::RegisterSpec for ANALOG_CNTL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [analog_cntl::R](R) reader structure"]
+impl crate::Readable for ANALOG_CNTL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [analog_cntl::W](W) writer structure"]
+impl crate::Writable for ANALOG_CNTL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ANALOG_CNTL to value 0"]
+impl crate::Resettable for ANALOG_CNTL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/areg_cal.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `AREG_CAL` reader"]
+pub struct R(crate::R<AREG_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<AREG_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<AREG_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<AREG_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `AREG_CAL` reader - Analog LDO Regulator Calibration bits"]
+pub struct AREG_CAL_R(crate::FieldReader<u16, u16>);
+impl AREG_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        AREG_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for AREG_CAL_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:8 - Analog LDO Regulator Calibration bits"]
+    #[inline(always)]
+    pub fn areg_cal(&self) -> AREG_CAL_R {
+        AREG_CAL_R::new((self.bits & 0x01ff) as u16)
+    }
+}
+#[doc = "Analog LDO Regulator Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [areg_cal](index.html) module"]
+pub struct AREG_CAL_SPEC;
+impl crate::RegisterSpec for AREG_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [areg_cal::R](R) reader structure"]
+impl crate::Readable for AREG_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets AREG_CAL to value 0"]
+impl crate::Resettable for AREG_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/bg_cal.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `BG_CAL` reader"]
+pub struct R(crate::R<BG_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BG_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BG_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BG_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `BG_CAL` reader - Bandgap Calibration bits"]
+pub struct BG_CAL_R(crate::FieldReader<u8, u8>);
+impl BG_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        BG_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for BG_CAL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Bandgap Calibration bits"]
+    #[inline(always)]
+    pub fn bg_cal(&self) -> BG_CAL_R {
+        BG_CAL_R::new((self.bits & 0x07) as u8)
+    }
+}
+#[doc = "Bandgap Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bg_cal](index.html) module"]
+pub struct BG_CAL_SPEC;
+impl crate::RegisterSpec for BG_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bg_cal::R](R) reader structure"]
+impl crate::Readable for BG_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets BG_CAL to value 0"]
+impl crate::Resettable for BG_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/dac0_cal.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `DAC0_CAL` reader"]
+pub struct R(crate::R<DAC0_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DAC0_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DAC0_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DAC0_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DAC0_CAL` reader - DAC0 Calibration bits"]
+pub struct DAC0_CAL_R(crate::FieldReader<u8, u8>);
+impl DAC0_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        DAC0_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DAC0_CAL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - DAC0 Calibration bits"]
+    #[inline(always)]
+    pub fn dac0_cal(&self) -> DAC0_CAL_R {
+        DAC0_CAL_R::new((self.bits & 0x1f) as u8)
+    }
+}
+#[doc = "DAC0 Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dac0_cal](index.html) module"]
+pub struct DAC0_CAL_SPEC;
+impl crate::RegisterSpec for DAC0_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dac0_cal::R](R) reader structure"]
+impl crate::Readable for DAC0_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DAC0_CAL to value 0"]
+impl crate::Resettable for DAC0_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/dac1_cal.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `DAC1_CAL` reader"]
+pub struct R(crate::R<DAC1_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DAC1_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DAC1_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DAC1_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DAC1_CAL` reader - DAC1 Calibration bits"]
+pub struct DAC1_CAL_R(crate::FieldReader<u8, u8>);
+impl DAC1_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        DAC1_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DAC1_CAL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - DAC1 Calibration bits"]
+    #[inline(always)]
+    pub fn dac1_cal(&self) -> DAC1_CAL_R {
+        DAC1_CAL_R::new((self.bits & 0x1f) as u8)
+    }
+}
+#[doc = "DAC1 Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dac1_cal](index.html) module"]
+pub struct DAC1_CAL_SPEC;
+impl crate::RegisterSpec for DAC1_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dac1_cal::R](R) reader structure"]
+impl crate::Readable for DAC1_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DAC1_CAL to value 0"]
+impl crate::Resettable for DAC1_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/dreg_cal.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `DREG_CAL` reader"]
+pub struct R(crate::R<DREG_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DREG_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DREG_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DREG_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DREG_CAL` reader - Digital LDO Regulator Calibration bits"]
+pub struct DREG_CAL_R(crate::FieldReader<u16, u16>);
+impl DREG_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        DREG_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DREG_CAL_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:8 - Digital LDO Regulator Calibration bits"]
+    #[inline(always)]
+    pub fn dreg_cal(&self) -> DREG_CAL_R {
+        DREG_CAL_R::new((self.bits & 0x01ff) as u16)
+    }
+}
+#[doc = "Digital LDO Regulator Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dreg_cal](index.html) module"]
+pub struct DREG_CAL_SPEC;
+impl crate::RegisterSpec for DREG_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dreg_cal::R](R) reader structure"]
+impl crate::Readable for DREG_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DREG_CAL to value 0"]
+impl crate::Resettable for DREG_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ebi_cfg0.rs

@@ -0,0 +1,298 @@
+#[doc = "Register `EBI_CFG0` reader"]
+pub struct R(crate::R<EBI_CFG0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EBI_CFG0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EBI_CFG0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EBI_CFG0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EBI_CFG0` writer"]
+pub struct W(crate::W<EBI_CFG0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EBI_CFG0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EBI_CFG0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EBI_CFG0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"]
+pub struct ADDRLOW0_R(crate::FieldReader<u8, u8>);
+impl ADDRLOW0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRLOW0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRLOW0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"]
+pub struct ADDRLOW0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRLOW0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
+        self.w
+    }
+}
+#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_R(crate::FieldReader<u8, u8>);
+impl ADDRHIGH0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRHIGH0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRHIGH0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRHIGH0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
+        self.w
+    }
+}
+#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGREADCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGREADCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGREADCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGREADCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
+        self.w
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGWRITECYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGWRITECYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGWRITECYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGWRITECYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19);
+        self.w
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGTURNAROUNDCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGTURNAROUNDCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGTURNAROUNDCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22);
+        self.w
+    }
+}
+#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_R(crate::FieldReader<bool, bool>);
+impl CFGSIZE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CFGSIZE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGSIZE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGSIZE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&self) -> ADDRLOW0_R {
+        ADDRLOW0_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&self) -> ADDRHIGH0_R {
+        ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R {
+        CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8)
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R {
+        CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8)
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R {
+        CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8)
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&self) -> CFGSIZE_R {
+        CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&mut self) -> ADDRLOW0_W {
+        ADDRLOW0_W { w: self }
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&mut self) -> ADDRHIGH0_W {
+        ADDRHIGH0_W { w: self }
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W {
+        CFGREADCYCLE_W { w: self }
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W {
+        CFGWRITECYCLE_W { w: self }
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W {
+        CFGTURNAROUNDCYCLE_W { w: self }
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&mut self) -> CFGSIZE_W {
+        CFGSIZE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "EBI Config Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg0](index.html) module"]
+pub struct EBI_CFG0_SPEC;
+impl crate::RegisterSpec for EBI_CFG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ebi_cfg0::R](R) reader structure"]
+impl crate::Readable for EBI_CFG0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ebi_cfg0::W](W) writer structure"]
+impl crate::Writable for EBI_CFG0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EBI_CFG0 to value 0"]
+impl crate::Resettable for EBI_CFG0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ebi_cfg1.rs

@@ -0,0 +1,298 @@
+#[doc = "Register `EBI_CFG1` reader"]
+pub struct R(crate::R<EBI_CFG1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EBI_CFG1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EBI_CFG1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EBI_CFG1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EBI_CFG1` writer"]
+pub struct W(crate::W<EBI_CFG1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EBI_CFG1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EBI_CFG1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EBI_CFG1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"]
+pub struct ADDRLOW0_R(crate::FieldReader<u8, u8>);
+impl ADDRLOW0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRLOW0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRLOW0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"]
+pub struct ADDRLOW0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRLOW0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
+        self.w
+    }
+}
+#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_R(crate::FieldReader<u8, u8>);
+impl ADDRHIGH0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRHIGH0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRHIGH0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRHIGH0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
+        self.w
+    }
+}
+#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGREADCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGREADCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGREADCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGREADCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
+        self.w
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGWRITECYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGWRITECYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGWRITECYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGWRITECYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19);
+        self.w
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGTURNAROUNDCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGTURNAROUNDCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGTURNAROUNDCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22);
+        self.w
+    }
+}
+#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_R(crate::FieldReader<bool, bool>);
+impl CFGSIZE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CFGSIZE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGSIZE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGSIZE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&self) -> ADDRLOW0_R {
+        ADDRLOW0_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&self) -> ADDRHIGH0_R {
+        ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R {
+        CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8)
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R {
+        CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8)
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R {
+        CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8)
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&self) -> CFGSIZE_R {
+        CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&mut self) -> ADDRLOW0_W {
+        ADDRLOW0_W { w: self }
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&mut self) -> ADDRHIGH0_W {
+        ADDRHIGH0_W { w: self }
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W {
+        CFGREADCYCLE_W { w: self }
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W {
+        CFGWRITECYCLE_W { w: self }
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W {
+        CFGTURNAROUNDCYCLE_W { w: self }
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&mut self) -> CFGSIZE_W {
+        CFGSIZE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "EBI Config Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg1](index.html) module"]
+pub struct EBI_CFG1_SPEC;
+impl crate::RegisterSpec for EBI_CFG1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ebi_cfg1::R](R) reader structure"]
+impl crate::Readable for EBI_CFG1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ebi_cfg1::W](W) writer structure"]
+impl crate::Writable for EBI_CFG1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EBI_CFG1 to value 0"]
+impl crate::Resettable for EBI_CFG1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ebi_cfg2.rs

@@ -0,0 +1,298 @@
+#[doc = "Register `EBI_CFG2` reader"]
+pub struct R(crate::R<EBI_CFG2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EBI_CFG2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EBI_CFG2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EBI_CFG2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EBI_CFG2` writer"]
+pub struct W(crate::W<EBI_CFG2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EBI_CFG2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EBI_CFG2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EBI_CFG2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"]
+pub struct ADDRLOW0_R(crate::FieldReader<u8, u8>);
+impl ADDRLOW0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRLOW0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRLOW0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"]
+pub struct ADDRLOW0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRLOW0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
+        self.w
+    }
+}
+#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_R(crate::FieldReader<u8, u8>);
+impl ADDRHIGH0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRHIGH0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRHIGH0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRHIGH0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
+        self.w
+    }
+}
+#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGREADCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGREADCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGREADCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGREADCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
+        self.w
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGWRITECYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGWRITECYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGWRITECYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGWRITECYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19);
+        self.w
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGTURNAROUNDCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGTURNAROUNDCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGTURNAROUNDCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22);
+        self.w
+    }
+}
+#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_R(crate::FieldReader<bool, bool>);
+impl CFGSIZE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CFGSIZE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGSIZE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGSIZE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&self) -> ADDRLOW0_R {
+        ADDRLOW0_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&self) -> ADDRHIGH0_R {
+        ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R {
+        CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8)
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R {
+        CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8)
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R {
+        CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8)
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&self) -> CFGSIZE_R {
+        CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&mut self) -> ADDRLOW0_W {
+        ADDRLOW0_W { w: self }
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&mut self) -> ADDRHIGH0_W {
+        ADDRHIGH0_W { w: self }
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W {
+        CFGREADCYCLE_W { w: self }
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W {
+        CFGWRITECYCLE_W { w: self }
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W {
+        CFGTURNAROUNDCYCLE_W { w: self }
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&mut self) -> CFGSIZE_W {
+        CFGSIZE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "EBI Config Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg2](index.html) module"]
+pub struct EBI_CFG2_SPEC;
+impl crate::RegisterSpec for EBI_CFG2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ebi_cfg2::R](R) reader structure"]
+impl crate::Readable for EBI_CFG2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ebi_cfg2::W](W) writer structure"]
+impl crate::Writable for EBI_CFG2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EBI_CFG2 to value 0"]
+impl crate::Resettable for EBI_CFG2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ebi_cfg3.rs

@@ -0,0 +1,298 @@
+#[doc = "Register `EBI_CFG3` reader"]
+pub struct R(crate::R<EBI_CFG3_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EBI_CFG3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EBI_CFG3_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EBI_CFG3_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EBI_CFG3` writer"]
+pub struct W(crate::W<EBI_CFG3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EBI_CFG3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EBI_CFG3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EBI_CFG3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"]
+pub struct ADDRLOW0_R(crate::FieldReader<u8, u8>);
+impl ADDRLOW0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRLOW0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRLOW0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"]
+pub struct ADDRLOW0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRLOW0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
+        self.w
+    }
+}
+#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_R(crate::FieldReader<u8, u8>);
+impl ADDRHIGH0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ADDRHIGH0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRHIGH0_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"]
+pub struct ADDRHIGH0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRHIGH0_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
+        self.w
+    }
+}
+#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGREADCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGREADCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGREADCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"]
+pub struct CFGREADCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGREADCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
+        self.w
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGWRITECYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGWRITECYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGWRITECYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"]
+pub struct CFGWRITECYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGWRITECYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19);
+        self.w
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader<u8, u8>);
+impl CFGTURNAROUNDCYCLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGTURNAROUNDCYCLE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"]
+pub struct CFGTURNAROUNDCYCLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGTURNAROUNDCYCLE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22);
+        self.w
+    }
+}
+#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_R(crate::FieldReader<bool, bool>);
+impl CFGSIZE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CFGSIZE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CFGSIZE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"]
+pub struct CFGSIZE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CFGSIZE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&self) -> ADDRLOW0_R {
+        ADDRLOW0_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&self) -> ADDRHIGH0_R {
+        ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R {
+        CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8)
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R {
+        CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8)
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R {
+        CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8)
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&self) -> CFGSIZE_R {
+        CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Lower bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrlow0(&mut self) -> ADDRLOW0_W {
+        ADDRLOW0_W { w: self }
+    }
+    #[doc = "Bits 8:15 - Upper bound address for CEN0"]
+    #[inline(always)]
+    pub fn addrhigh0(&mut self) -> ADDRHIGH0_W {
+        ADDRHIGH0_W { w: self }
+    }
+    #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
+    #[inline(always)]
+    pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W {
+        CFGREADCYCLE_W { w: self }
+    }
+    #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
+    #[inline(always)]
+    pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W {
+        CFGWRITECYCLE_W { w: self }
+    }
+    #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
+    #[inline(always)]
+    pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W {
+        CFGTURNAROUNDCYCLE_W { w: self }
+    }
+    #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
+    #[inline(always)]
+    pub fn cfgsize(&mut self) -> CFGSIZE_W {
+        CFGSIZE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "EBI Config Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg3](index.html) module"]
+pub struct EBI_CFG3_SPEC;
+impl crate::RegisterSpec for EBI_CFG3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ebi_cfg3::R](R) reader structure"]
+impl crate::Readable for EBI_CFG3_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ebi_cfg3::W](W) writer structure"]
+impl crate::Writable for EBI_CFG3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EBI_CFG3 to value 0"]
+impl crate::Resettable for EBI_CFG3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ef_config.rs

@@ -0,0 +1,253 @@
+#[doc = "Register `EF_CONFIG` reader"]
+pub struct R(crate::R<EF_CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EF_CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EF_CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EF_CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROM_SPEED` reader - Specifies the speed of ROM_SCK"]
+pub struct ROM_SPEED_R(crate::FieldReader<u8, u8>);
+impl ROM_SPEED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ROM_SPEED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_SPEED_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_SIZE` reader - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"]
+pub struct ROM_SIZE_R(crate::FieldReader<u8, u8>);
+impl ROM_SIZE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ROM_SIZE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_SIZE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_NOCHECK` reader - When set to 1, the ROM check is skipped"]
+pub struct ROM_NOCHECK_R(crate::FieldReader<bool, bool>);
+impl ROM_NOCHECK_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROM_NOCHECK_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_NOCHECK_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `BOOT_DELAY` reader - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"]
+pub struct BOOT_DELAY_R(crate::FieldReader<u8, u8>);
+impl BOOT_DELAY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        BOOT_DELAY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for BOOT_DELAY_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_READ` reader - SPI ROM read instruction code"]
+pub struct ROM_READ_R(crate::FieldReader<u8, u8>);
+impl ROM_READ_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ROM_READ_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_READ_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_LATENCY` reader - Number of bits of latency from Address until data from the SPI ROM"]
+pub struct ROM_LATENCY_R(crate::FieldReader<u8, u8>);
+impl ROM_LATENCY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ROM_LATENCY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_LATENCY_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_ADDRESS` reader - ROM Address Mode"]
+pub struct ROM_ADDRESS_R(crate::FieldReader<u8, u8>);
+impl ROM_ADDRESS_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        ROM_ADDRESS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_ADDRESS_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_DLYCAP` reader - ROM SPI Delayed capture"]
+pub struct ROM_DLYCAP_R(crate::FieldReader<bool, bool>);
+impl ROM_DLYCAP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROM_DLYCAP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_DLYCAP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROM_STATUS` reader - The first data byte from the SPI ROM following an address is taken as a status byte"]
+pub struct ROM_STATUS_R(crate::FieldReader<bool, bool>);
+impl ROM_STATUS_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROM_STATUS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROM_STATUS_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RM` reader - This bit controls the internal RAM read timing and must be maintained at this value"]
+pub struct RM_R(crate::FieldReader<bool, bool>);
+impl RM_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RM_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RM_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WM` reader - This bit controls the internal RAM write timing and must be maintained at this value"]
+pub struct WM_R(crate::FieldReader<bool, bool>);
+impl WM_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WM_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WM_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Specifies the speed of ROM_SCK"]
+    #[inline(always)]
+    pub fn rom_speed(&self) -> ROM_SPEED_R {
+        ROM_SPEED_R::new((self.bits & 0x03) as u8)
+    }
+    #[doc = "Bits 2:5 - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"]
+    #[inline(always)]
+    pub fn rom_size(&self) -> ROM_SIZE_R {
+        ROM_SIZE_R::new(((self.bits >> 2) & 0x0f) as u8)
+    }
+    #[doc = "Bit 6 - When set to 1, the ROM check is skipped"]
+    #[inline(always)]
+    pub fn rom_nocheck(&self) -> ROM_NOCHECK_R {
+        ROM_NOCHECK_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bits 7:9 - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"]
+    #[inline(always)]
+    pub fn boot_delay(&self) -> BOOT_DELAY_R {
+        BOOT_DELAY_R::new(((self.bits >> 7) & 0x07) as u8)
+    }
+    #[doc = "Bits 10:17 - SPI ROM read instruction code"]
+    #[inline(always)]
+    pub fn rom_read(&self) -> ROM_READ_R {
+        ROM_READ_R::new(((self.bits >> 10) & 0xff) as u8)
+    }
+    #[doc = "Bits 18:22 - Number of bits of latency from Address until data from the SPI ROM"]
+    #[inline(always)]
+    pub fn rom_latency(&self) -> ROM_LATENCY_R {
+        ROM_LATENCY_R::new(((self.bits >> 18) & 0x1f) as u8)
+    }
+    #[doc = "Bits 23:24 - ROM Address Mode"]
+    #[inline(always)]
+    pub fn rom_address(&self) -> ROM_ADDRESS_R {
+        ROM_ADDRESS_R::new(((self.bits >> 23) & 0x03) as u8)
+    }
+    #[doc = "Bit 25 - ROM SPI Delayed capture"]
+    #[inline(always)]
+    pub fn rom_dlycap(&self) -> ROM_DLYCAP_R {
+        ROM_DLYCAP_R::new(((self.bits >> 25) & 0x01) != 0)
+    }
+    #[doc = "Bit 26 - The first data byte from the SPI ROM following an address is taken as a status byte"]
+    #[inline(always)]
+    pub fn rom_status(&self) -> ROM_STATUS_R {
+        ROM_STATUS_R::new(((self.bits >> 26) & 0x01) != 0)
+    }
+    #[doc = "Bit 27 - This bit controls the internal RAM read timing and must be maintained at this value"]
+    #[inline(always)]
+    pub fn rm(&self) -> RM_R {
+        RM_R::new(((self.bits >> 27) & 0x01) != 0)
+    }
+    #[doc = "Bit 28 - This bit controls the internal RAM write timing and must be maintained at this value"]
+    #[inline(always)]
+    pub fn wm(&self) -> WM_R {
+        WM_R::new(((self.bits >> 28) & 0x01) != 0)
+    }
+}
+#[doc = "EFuse Config Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ef_config](index.html) module"]
+pub struct EF_CONFIG_SPEC;
+impl crate::RegisterSpec for EF_CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ef_config::R](R) reader structure"]
+impl crate::Readable for EF_CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets EF_CONFIG to value 0x0a80_0c40"]
+impl crate::Resettable for EF_CONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0a80_0c40
+    }
+}

src/sysconfig/ef_id0.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `EF_ID0` reader"]
+pub struct R(crate::R<EF_ID0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EF_ID0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EF_ID0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EF_ID0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "EFuse ID0 Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ef_id0](index.html) module"]
+pub struct EF_ID0_SPEC;
+impl crate::RegisterSpec for EF_ID0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ef_id0::R](R) reader structure"]
+impl crate::Readable for EF_ID0_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets EF_ID0 to value 0"]
+impl crate::Resettable for EF_ID0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ef_id1.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `EF_ID1` reader"]
+pub struct R(crate::R<EF_ID1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EF_ID1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EF_ID1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EF_ID1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "EFuse ID1 Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ef_id1](index.html) module"]
+pub struct EF_ID1_SPEC;
+impl crate::RegisterSpec for EF_ID1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ef_id1::R](R) reader structure"]
+impl crate::Readable for EF_ID1_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets EF_ID1 to value 0"]
+impl crate::Resettable for EF_ID1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/hbo_cal.rs

@@ -0,0 +1,73 @@
+#[doc = "Register `HBO_CAL` reader"]
+pub struct R(crate::R<HBO_CAL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HBO_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HBO_CAL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HBO_CAL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `OSC_CAL` reader - 1MHz OSC Calibration bit"]
+pub struct OSC_CAL_R(crate::FieldReader<bool, bool>);
+impl OSC_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        OSC_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for OSC_CAL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `HBO_CAL` reader - Heart Beat OSC Calibration bits"]
+pub struct HBO_CAL_R(crate::FieldReader<u8, u8>);
+impl HBO_CAL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        HBO_CAL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for HBO_CAL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 3 - 1MHz OSC Calibration bit"]
+    #[inline(always)]
+    pub fn osc_cal(&self) -> OSC_CAL_R {
+        OSC_CAL_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bits 0:2 - Heart Beat OSC Calibration bits"]
+    #[inline(always)]
+    pub fn hbo_cal(&self) -> HBO_CAL_R {
+        HBO_CAL_R::new((self.bits & 0x07) as u8)
+    }
+}
+#[doc = "Heart Beat OSC Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hbo_cal](index.html) module"]
+pub struct HBO_CAL_SPEC;
+impl crate::RegisterSpec for HBO_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hbo_cal::R](R) reader structure"]
+impl crate::Readable for HBO_CAL_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HBO_CAL to value 0"]
+impl crate::Resettable for HBO_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/irq_clr.rs

@@ -0,0 +1,207 @@
+#[doc = "Register `IRQ_CLR` writer"]
+pub struct W(crate::W<IRQ_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"]
+pub struct ROMMBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ROMMBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"]
+pub struct ROMSBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ROMSBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"]
+pub struct RAM0MBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM0MBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"]
+pub struct RAM0SBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM0SBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"]
+pub struct RAM1MBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM1MBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"]
+pub struct RAM1SBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM1SBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&mut self) -> ROMMBE_W {
+        ROMMBE_W { w: self }
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&mut self) -> ROMSBE_W {
+        ROMSBE_W { w: self }
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0mbe(&mut self) -> RAM0MBE_W {
+        RAM0MBE_W { w: self }
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0sbe(&mut self) -> RAM0SBE_W {
+        RAM0SBE_W { w: self }
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1mbe(&mut self) -> RAM1MBE_W {
+        RAM1MBE_W { w: self }
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1sbe(&mut self) -> RAM1SBE_W {
+        RAM1SBE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clear EDAC Error Interrupt Status\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"]
+pub struct IRQ_CLR_SPEC;
+impl crate::RegisterSpec for IRQ_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"]
+impl crate::Writable for IRQ_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_CLR to value 0"]
+impl crate::Resettable for IRQ_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/irq_enb.rs

@@ -0,0 +1,348 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub struct R(crate::R<IRQ_ENB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_ENB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_ENB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRQ_ENB` writer"]
+pub struct W(crate::W<IRQ_ENB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_ENB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_ENB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"]
+pub struct ROMMBE_R(crate::FieldReader<bool, bool>);
+impl ROMMBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROMMBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROMMBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"]
+pub struct ROMMBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ROMMBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"]
+pub struct ROMSBE_R(crate::FieldReader<bool, bool>);
+impl ROMSBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROMSBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROMSBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"]
+pub struct ROMSBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ROMSBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"]
+pub struct RAM0MBE_R(crate::FieldReader<bool, bool>);
+impl RAM0MBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM0MBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM0MBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"]
+pub struct RAM0MBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM0MBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"]
+pub struct RAM0SBE_R(crate::FieldReader<bool, bool>);
+impl RAM0SBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM0SBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM0SBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"]
+pub struct RAM0SBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM0SBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"]
+pub struct RAM1MBE_R(crate::FieldReader<bool, bool>);
+impl RAM1MBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM1MBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM1MBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"]
+pub struct RAM1MBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM1MBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"]
+pub struct RAM1SBE_R(crate::FieldReader<bool, bool>);
+impl RAM1SBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM1SBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM1SBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"]
+pub struct RAM1SBE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAM1SBE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&self) -> ROMMBE_R {
+        ROMMBE_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&self) -> ROMSBE_R {
+        ROMSBE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0mbe(&self) -> RAM0MBE_R {
+        RAM0MBE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0sbe(&self) -> RAM0SBE_R {
+        RAM0SBE_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1mbe(&self) -> RAM1MBE_R {
+        RAM1MBE_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1sbe(&self) -> RAM1SBE_R {
+        RAM1SBE_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&mut self) -> ROMMBE_W {
+        ROMMBE_W { w: self }
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&mut self) -> ROMSBE_W {
+        ROMSBE_W { w: self }
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0mbe(&mut self) -> RAM0MBE_W {
+        RAM0MBE_W { w: self }
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0sbe(&mut self) -> RAM0SBE_W {
+        RAM0SBE_W { w: self }
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1mbe(&mut self) -> RAM1MBE_W {
+        RAM1MBE_W { w: self }
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1sbe(&mut self) -> RAM1SBE_W {
+        RAM1SBE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable EDAC Error Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"]
+pub struct IRQ_ENB_SPEC;
+impl crate::RegisterSpec for IRQ_ENB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_enb::R](R) reader structure"]
+impl crate::Readable for IRQ_ENB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"]
+impl crate::Writable for IRQ_ENB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IRQ_ENB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/irq_end.rs

@@ -0,0 +1,153 @@
+#[doc = "Register `IRQ_END` reader"]
+pub struct R(crate::R<IRQ_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"]
+pub struct ROMMBE_R(crate::FieldReader<bool, bool>);
+impl ROMMBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROMMBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROMMBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"]
+pub struct ROMSBE_R(crate::FieldReader<bool, bool>);
+impl ROMSBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROMSBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROMSBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"]
+pub struct RAM0MBE_R(crate::FieldReader<bool, bool>);
+impl RAM0MBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM0MBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM0MBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"]
+pub struct RAM0SBE_R(crate::FieldReader<bool, bool>);
+impl RAM0SBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM0SBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM0SBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"]
+pub struct RAM1MBE_R(crate::FieldReader<bool, bool>);
+impl RAM1MBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM1MBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM1MBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"]
+pub struct RAM1SBE_R(crate::FieldReader<bool, bool>);
+impl RAM1SBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM1SBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM1SBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&self) -> ROMMBE_R {
+        ROMMBE_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&self) -> ROMSBE_R {
+        ROMSBE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0mbe(&self) -> RAM0MBE_R {
+        RAM0MBE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0sbe(&self) -> RAM0SBE_R {
+        RAM0SBE_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1mbe(&self) -> RAM1MBE_R {
+        RAM1MBE_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1sbe(&self) -> RAM1SBE_R {
+        RAM1SBE_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+#[doc = "Enabled EDAC Error Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"]
+pub struct IRQ_END_SPEC;
+impl crate::RegisterSpec for IRQ_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_end::R](R) reader structure"]
+impl crate::Readable for IRQ_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IRQ_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/irq_raw.rs

@@ -0,0 +1,153 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub struct R(crate::R<IRQ_RAW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_RAW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_RAW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_RAW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"]
+pub struct ROMMBE_R(crate::FieldReader<bool, bool>);
+impl ROMMBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROMMBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROMMBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"]
+pub struct ROMSBE_R(crate::FieldReader<bool, bool>);
+impl ROMSBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ROMSBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ROMSBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"]
+pub struct RAM0MBE_R(crate::FieldReader<bool, bool>);
+impl RAM0MBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM0MBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM0MBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"]
+pub struct RAM0SBE_R(crate::FieldReader<bool, bool>);
+impl RAM0SBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM0SBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM0SBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"]
+pub struct RAM1MBE_R(crate::FieldReader<bool, bool>);
+impl RAM1MBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM1MBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM1MBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"]
+pub struct RAM1SBE_R(crate::FieldReader<bool, bool>);
+impl RAM1SBE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAM1SBE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAM1SBE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ROM Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn rommbe(&self) -> ROMMBE_R {
+        ROMMBE_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - ROM Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn romsbe(&self) -> ROMSBE_R {
+        ROMSBE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0mbe(&self) -> RAM0MBE_R {
+        RAM0MBE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram0sbe(&self) -> RAM0SBE_R {
+        RAM0SBE_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1mbe(&self) -> RAM1MBE_R {
+        RAM1MBE_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
+    #[inline(always)]
+    pub fn ram1sbe(&self) -> RAM1SBE_R {
+        RAM1SBE_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+#[doc = "Raw EDAC Error Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"]
+pub struct IRQ_RAW_SPEC;
+impl crate::RegisterSpec for IRQ_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_raw::R](R) reader structure"]
+impl crate::Readable for IRQ_RAW_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQ_RAW to value 0"]
+impl crate::Resettable for IRQ_RAW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/perid.rs

@@ -0,0 +1,93 @@
+#[doc = "Register `PERID` reader"]
+pub struct R(crate::R<PERID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `MANUFACTURER_ID` reader - MANUFACTURER_ID"]
+pub struct MANUFACTURER_ID_R(crate::FieldReader<u16, u16>);
+impl MANUFACTURER_ID_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        MANUFACTURER_ID_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for MANUFACTURER_ID_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PERIPHERAL_ID` reader - PERIPHERAL_ID"]
+pub struct PERIPHERAL_ID_R(crate::FieldReader<u8, u8>);
+impl PERIPHERAL_ID_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        PERIPHERAL_ID_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PERIPHERAL_ID_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PERIPHERAL_VER` reader - PERIPHERAL_VER"]
+pub struct PERIPHERAL_VER_R(crate::FieldReader<u8, u8>);
+impl PERIPHERAL_VER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        PERIPHERAL_VER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PERIPHERAL_VER_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:11 - MANUFACTURER_ID"]
+    #[inline(always)]
+    pub fn manufacturer_id(&self) -> MANUFACTURER_ID_R {
+        MANUFACTURER_ID_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 16:23 - PERIPHERAL_ID"]
+    #[inline(always)]
+    pub fn peripheral_id(&self) -> PERIPHERAL_ID_R {
+        PERIPHERAL_ID_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - PERIPHERAL_VER"]
+    #[inline(always)]
+    pub fn peripheral_ver(&self) -> PERIPHERAL_VER_R {
+        PERIPHERAL_VER_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"]
+pub struct PERID_SPEC;
+impl crate::RegisterSpec for PERID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perid::R](R) reader structure"]
+impl crate::Readable for PERID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PERID to value 0x0280_07e9"]
+impl crate::Resettable for PERID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0280_07e9
+    }
+}

src/sysconfig/pmu_ctrl.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `PMU_CTRL` reader"]
+pub struct R(crate::R<PMU_CTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PMU_CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PMU_CTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PMU_CTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PMU_CTRL` writer"]
+pub struct W(crate::W<PMU_CTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PMU_CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PMU_CTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PMU_CTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LVL_SLCT` reader - Select the POK detect level"]
+pub struct LVL_SLCT_R(crate::FieldReader<u8, u8>);
+impl LVL_SLCT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        LVL_SLCT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LVL_SLCT_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LVL_SLCT` writer - Select the POK detect level"]
+pub struct LVL_SLCT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LVL_SLCT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Select the POK detect level"]
+    #[inline(always)]
+    pub fn lvl_slct(&self) -> LVL_SLCT_R {
+        LVL_SLCT_R::new((self.bits & 0x03) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Select the POK detect level"]
+    #[inline(always)]
+    pub fn lvl_slct(&mut self) -> LVL_SLCT_W {
+        LVL_SLCT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PMU Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmu_ctrl](index.html) module"]
+pub struct PMU_CTRL_SPEC;
+impl crate::RegisterSpec for PMU_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [pmu_ctrl::R](R) reader structure"]
+impl crate::Readable for PMU_CTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pmu_ctrl::W](W) writer structure"]
+impl crate::Writable for PMU_CTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PMU_CTRL to value 0"]
+impl crate::Resettable for PMU_CTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/procid.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `PROCID` reader"]
+pub struct R(crate::R<PROCID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PROCID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PROCID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PROCID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Processor ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [procid](index.html) module"]
+pub struct PROCID_SPEC;
+impl crate::RegisterSpec for PROCID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [procid::R](R) reader structure"]
+impl crate::Readable for PROCID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PROCID to value 0x0400_57e3"]
+impl crate::Resettable for PROCID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0400_57e3
+    }
+}

src/sysconfig/ram0_mbe.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `RAM0_MBE` reader"]
+pub struct R(crate::R<RAM0_MBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM0_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM0_MBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM0_MBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RAM0_MBE` writer"]
+pub struct W(crate::W<RAM0_MBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RAM0_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RAM0_MBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RAM0_MBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"]
+pub struct COUNT_R(crate::FieldReader<u16, u16>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"]
+pub struct COUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W {
+        COUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram0_mbe](index.html) module"]
+pub struct RAM0_MBE_SPEC;
+impl crate::RegisterSpec for RAM0_MBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram0_mbe::R](R) reader structure"]
+impl crate::Readable for RAM0_MBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ram0_mbe::W](W) writer structure"]
+impl crate::Writable for RAM0_MBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RAM0_MBE to value 0"]
+impl crate::Resettable for RAM0_MBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ram0_sbe.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `RAM0_SBE` reader"]
+pub struct R(crate::R<RAM0_SBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM0_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM0_SBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM0_SBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RAM0_SBE` writer"]
+pub struct W(crate::W<RAM0_SBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RAM0_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RAM0_SBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RAM0_SBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"]
+pub struct COUNT_R(crate::FieldReader<u16, u16>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"]
+pub struct COUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W {
+        COUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram0_sbe](index.html) module"]
+pub struct RAM0_SBE_SPEC;
+impl crate::RegisterSpec for RAM0_SBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram0_sbe::R](R) reader structure"]
+impl crate::Readable for RAM0_SBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ram0_sbe::W](W) writer structure"]
+impl crate::Writable for RAM0_SBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RAM0_SBE to value 0"]
+impl crate::Resettable for RAM0_SBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ram0_scrub.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `RAM0_SCRUB` reader"]
+pub struct R(crate::R<RAM0_SCRUB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM0_SCRUB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM0_SCRUB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM0_SCRUB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RAM0_SCRUB` writer"]
+pub struct W(crate::W<RAM0_SCRUB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RAM0_SCRUB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RAM0_SCRUB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RAM0_SCRUB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `VALUE` reader - Counter divide value"]
+pub struct VALUE_R(crate::FieldReader<u32, u32>);
+impl VALUE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        VALUE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for VALUE_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `VALUE` writer - Counter divide value"]
+pub struct VALUE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> VALUE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
+        self.w
+    }
+}
+#[doc = "Field `RESET` writer - Reset Counter"]
+pub struct RESET_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RESET_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&self) -> VALUE_R {
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&mut self) -> VALUE_W {
+        VALUE_W { w: self }
+    }
+    #[doc = "Bit 31 - Reset Counter"]
+    #[inline(always)]
+    pub fn reset(&mut self) -> RESET_W {
+        RESET_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RAM0 Scrub Period Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram0_scrub](index.html) module"]
+pub struct RAM0_SCRUB_SPEC;
+impl crate::RegisterSpec for RAM0_SCRUB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram0_scrub::R](R) reader structure"]
+impl crate::Readable for RAM0_SCRUB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ram0_scrub::W](W) writer structure"]
+impl crate::Writable for RAM0_SCRUB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RAM0_SCRUB to value 0"]
+impl crate::Resettable for RAM0_SCRUB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ram1_mbe.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `RAM1_MBE` reader"]
+pub struct R(crate::R<RAM1_MBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM1_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM1_MBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM1_MBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RAM1_MBE` writer"]
+pub struct W(crate::W<RAM1_MBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RAM1_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RAM1_MBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RAM1_MBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"]
+pub struct COUNT_R(crate::FieldReader<u16, u16>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"]
+pub struct COUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W {
+        COUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Count of RAM1 EDAC Multi Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram1_mbe](index.html) module"]
+pub struct RAM1_MBE_SPEC;
+impl crate::RegisterSpec for RAM1_MBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram1_mbe::R](R) reader structure"]
+impl crate::Readable for RAM1_MBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ram1_mbe::W](W) writer structure"]
+impl crate::Writable for RAM1_MBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RAM1_MBE to value 0"]
+impl crate::Resettable for RAM1_MBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ram1_sbe.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `RAM1_SBE` reader"]
+pub struct R(crate::R<RAM1_SBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM1_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM1_SBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM1_SBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RAM1_SBE` writer"]
+pub struct W(crate::W<RAM1_SBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RAM1_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RAM1_SBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RAM1_SBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"]
+pub struct COUNT_R(crate::FieldReader<u16, u16>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"]
+pub struct COUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W {
+        COUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Count of RAM1 EDAC Single Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram1_sbe](index.html) module"]
+pub struct RAM1_SBE_SPEC;
+impl crate::RegisterSpec for RAM1_SBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram1_sbe::R](R) reader structure"]
+impl crate::Readable for RAM1_SBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ram1_sbe::W](W) writer structure"]
+impl crate::Writable for RAM1_SBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RAM1_SBE to value 0"]
+impl crate::Resettable for RAM1_SBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/ram1_scrub.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `RAM1_SCRUB` reader"]
+pub struct R(crate::R<RAM1_SCRUB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM1_SCRUB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM1_SCRUB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM1_SCRUB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RAM1_SCRUB` writer"]
+pub struct W(crate::W<RAM1_SCRUB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RAM1_SCRUB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RAM1_SCRUB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RAM1_SCRUB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `VALUE` reader - Counter divide value"]
+pub struct VALUE_R(crate::FieldReader<u32, u32>);
+impl VALUE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        VALUE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for VALUE_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `VALUE` writer - Counter divide value"]
+pub struct VALUE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> VALUE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
+        self.w
+    }
+}
+#[doc = "Field `RESET` writer - Reset Counter"]
+pub struct RESET_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RESET_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&self) -> VALUE_R {
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&mut self) -> VALUE_W {
+        VALUE_W { w: self }
+    }
+    #[doc = "Bit 31 - Reset Counter"]
+    #[inline(always)]
+    pub fn reset(&mut self) -> RESET_W {
+        RESET_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RAM1 Scrub Period Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram1_scrub](index.html) module"]
+pub struct RAM1_SCRUB_SPEC;
+impl crate::RegisterSpec for RAM1_SCRUB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram1_scrub::R](R) reader structure"]
+impl crate::Readable for RAM1_SCRUB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ram1_scrub::W](W) writer structure"]
+impl crate::Writable for RAM1_SCRUB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RAM1_SCRUB to value 0"]
+impl crate::Resettable for RAM1_SCRUB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/refresh_config_h.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `REFRESH_CONFIG_H` reader"]
+pub struct R(crate::R<REFRESH_CONFIG_H_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<REFRESH_CONFIG_H_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<REFRESH_CONFIG_H_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<REFRESH_CONFIG_H_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `REFRESH_CONFIG_H` writer"]
+pub struct W(crate::W<REFRESH_CONFIG_H_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<REFRESH_CONFIG_H_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<REFRESH_CONFIG_H_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<REFRESH_CONFIG_H_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DIVCOUNT` reader - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub struct DIVCOUNT_R(crate::FieldReader<u8, u8>);
+impl DIVCOUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        DIVCOUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DIVCOUNT_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `DIVCOUNT` writer - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub struct DIVCOUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DIVCOUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
+        self.w
+    }
+}
+#[doc = "Field `TESTMODE` reader - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+pub struct TESTMODE_R(crate::FieldReader<u8, u8>);
+impl TESTMODE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        TESTMODE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TESTMODE_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TESTMODE` writer - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+pub struct TESTMODE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TESTMODE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    pub fn divcount(&self) -> DIVCOUNT_R {
+        DIVCOUNT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+    #[inline(always)]
+    pub fn testmode(&self) -> TESTMODE_R {
+        TESTMODE_R::new(((self.bits >> 30) & 0x03) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    pub fn divcount(&mut self) -> DIVCOUNT_W {
+        DIVCOUNT_W { w: self }
+    }
+    #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
+    #[inline(always)]
+    pub fn testmode(&mut self) -> TESTMODE_W {
+        TESTMODE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Register Refresh Rate for TMR registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refresh_config_h](index.html) module"]
+pub struct REFRESH_CONFIG_H_SPEC;
+impl crate::RegisterSpec for REFRESH_CONFIG_H_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [refresh_config_h::R](R) reader structure"]
+impl crate::Readable for REFRESH_CONFIG_H_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [refresh_config_h::W](W) writer structure"]
+impl crate::Writable for REFRESH_CONFIG_H_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets REFRESH_CONFIG_H to value 0"]
+impl crate::Resettable for REFRESH_CONFIG_H_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/refresh_config_l.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `REFRESH_CONFIG_L` reader"]
+pub struct R(crate::R<REFRESH_CONFIG_L_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<REFRESH_CONFIG_L_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<REFRESH_CONFIG_L_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<REFRESH_CONFIG_L_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `REFRESH_CONFIG_L` writer"]
+pub struct W(crate::W<REFRESH_CONFIG_L_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<REFRESH_CONFIG_L_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<REFRESH_CONFIG_L_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<REFRESH_CONFIG_L_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DIVCOUNT` reader - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub struct DIVCOUNT_R(crate::FieldReader<u32, u32>);
+impl DIVCOUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        DIVCOUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DIVCOUNT_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `DIVCOUNT` writer - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+pub struct DIVCOUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DIVCOUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    pub fn divcount(&self) -> DIVCOUNT_R {
+        DIVCOUNT_R::new((self.bits & 0xffff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
+    #[inline(always)]
+    pub fn divcount(&mut self) -> DIVCOUNT_W {
+        DIVCOUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Register Refresh Rate for TMR registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refresh_config_l](index.html) module"]
+pub struct REFRESH_CONFIG_L_SPEC;
+impl crate::RegisterSpec for REFRESH_CONFIG_L_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [refresh_config_l::R](R) reader structure"]
+impl crate::Readable for REFRESH_CONFIG_L_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [refresh_config_l::W](W) writer structure"]
+impl crate::Writable for REFRESH_CONFIG_L_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets REFRESH_CONFIG_L to value 0x0f"]
+impl crate::Resettable for REFRESH_CONFIG_L_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0f
+    }
+}

src/sysconfig/rom_mbe.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `ROM_MBE` reader"]
+pub struct R(crate::R<ROM_MBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROM_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROM_MBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROM_MBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ROM_MBE` writer"]
+pub struct W(crate::W<ROM_MBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ROM_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ROM_MBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ROM_MBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"]
+pub struct COUNT_R(crate::FieldReader<u16, u16>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"]
+pub struct COUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W {
+        COUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Count of ROM EDAC Multi Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_mbe](index.html) module"]
+pub struct ROM_MBE_SPEC;
+impl crate::RegisterSpec for ROM_MBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rom_mbe::R](R) reader structure"]
+impl crate::Readable for ROM_MBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rom_mbe::W](W) writer structure"]
+impl crate::Writable for ROM_MBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ROM_MBE to value 0"]
+impl crate::Resettable for ROM_MBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/rom_prot.rs

@@ -0,0 +1,113 @@
+#[doc = "Register `ROM_PROT` reader"]
+pub struct R(crate::R<ROM_PROT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROM_PROT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROM_PROT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROM_PROT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ROM_PROT` writer"]
+pub struct W(crate::W<ROM_PROT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ROM_PROT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ROM_PROT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ROM_PROT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `WREN` reader - ROM Write Enable Bit"]
+pub struct WREN_R(crate::FieldReader<bool, bool>);
+impl WREN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WREN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WREN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WREN` writer - ROM Write Enable Bit"]
+pub struct WREN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WREN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ROM Write Enable Bit"]
+    #[inline(always)]
+    pub fn wren(&self) -> WREN_R {
+        WREN_R::new((self.bits & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - ROM Write Enable Bit"]
+    #[inline(always)]
+    pub fn wren(&mut self) -> WREN_W {
+        WREN_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ROM Protection Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_prot](index.html) module"]
+pub struct ROM_PROT_SPEC;
+impl crate::RegisterSpec for ROM_PROT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rom_prot::R](R) reader structure"]
+impl crate::Readable for ROM_PROT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rom_prot::W](W) writer structure"]
+impl crate::Writable for ROM_PROT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ROM_PROT to value 0"]
+impl crate::Resettable for ROM_PROT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/rom_retries.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `ROM_RETRIES` reader"]
+pub struct R(crate::R<ROM_RETRIES_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROM_RETRIES_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROM_RETRIES_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROM_RETRIES_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `COUNT` reader - Count of ROM block Retries"]
+pub struct COUNT_R(crate::FieldReader<u8, u8>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Count of ROM block Retries"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[doc = "ROM BOOT Retry count\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_retries](index.html) module"]
+pub struct ROM_RETRIES_SPEC;
+impl crate::RegisterSpec for ROM_RETRIES_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rom_retries::R](R) reader structure"]
+impl crate::Readable for ROM_RETRIES_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ROM_RETRIES to value 0"]
+impl crate::Resettable for ROM_RETRIES_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/rom_sbe.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `ROM_SBE` reader"]
+pub struct R(crate::R<ROM_SBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROM_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROM_SBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROM_SBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ROM_SBE` writer"]
+pub struct W(crate::W<ROM_SBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ROM_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ROM_SBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ROM_SBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"]
+pub struct COUNT_R(crate::FieldReader<u16, u16>);
+impl COUNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        COUNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COUNT_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"]
+pub struct COUNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COUNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&self) -> COUNT_R {
+        COUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
+    #[inline(always)]
+    pub fn count(&mut self) -> COUNT_W {
+        COUNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Count of ROM EDAC Single Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_sbe](index.html) module"]
+pub struct ROM_SBE_SPEC;
+impl crate::RegisterSpec for ROM_SBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rom_sbe::R](R) reader structure"]
+impl crate::Readable for ROM_SBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rom_sbe::W](W) writer structure"]
+impl crate::Writable for ROM_SBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ROM_SBE to value 0"]
+impl crate::Resettable for ROM_SBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/rom_scrub.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `ROM_SCRUB` reader"]
+pub struct R(crate::R<ROM_SCRUB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROM_SCRUB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROM_SCRUB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROM_SCRUB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ROM_SCRUB` writer"]
+pub struct W(crate::W<ROM_SCRUB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ROM_SCRUB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ROM_SCRUB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ROM_SCRUB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `VALUE` reader - Counter divide value"]
+pub struct VALUE_R(crate::FieldReader<u32, u32>);
+impl VALUE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        VALUE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for VALUE_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `VALUE` writer - Counter divide value"]
+pub struct VALUE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> VALUE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
+        self.w
+    }
+}
+#[doc = "Field `RESET` writer - Reset Counter"]
+pub struct RESET_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RESET_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&self) -> VALUE_R {
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Counter divide value"]
+    #[inline(always)]
+    pub fn value(&mut self) -> VALUE_W {
+        VALUE_W { w: self }
+    }
+    #[doc = "Bit 31 - Reset Counter"]
+    #[inline(always)]
+    pub fn reset(&mut self) -> RESET_W {
+        RESET_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ROM Scrub Period Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_scrub](index.html) module"]
+pub struct ROM_SCRUB_SPEC;
+impl crate::RegisterSpec for ROM_SCRUB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rom_scrub::R](R) reader structure"]
+impl crate::Readable for ROM_SCRUB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rom_scrub::W](W) writer structure"]
+impl crate::Writable for ROM_SCRUB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ROM_SCRUB to value 0"]
+impl crate::Resettable for ROM_SCRUB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/rst_cntl_ram0.rs

@@ -0,0 +1,321 @@
+#[doc = "Register `RST_CNTL_RAM0` reader"]
+pub struct R(crate::R<RST_CNTL_RAM0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RST_CNTL_RAM0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RST_CNTL_RAM0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RST_CNTL_RAM0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RST_CNTL_RAM0` writer"]
+pub struct W(crate::W<RST_CNTL_RAM0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RST_CNTL_RAM0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RST_CNTL_RAM0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RST_CNTL_RAM0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POR` reader - Power On Reset Status"]
+pub struct POR_R(crate::FieldReader<bool, bool>);
+impl POR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        POR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for POR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `POR` writer - Power On Reset Status"]
+pub struct POR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> POR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `EXTRST` reader - External Reset Status"]
+pub struct EXTRST_R(crate::FieldReader<bool, bool>);
+impl EXTRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        EXTRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for EXTRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `EXTRST` writer - External Reset Status"]
+pub struct EXTRST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EXTRST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_R(crate::FieldReader<bool, bool>);
+impl SYSRSTREQ_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SYSRSTREQ_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SYSRSTREQ_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SYSRSTREQ_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"]
+pub struct LOOKUP_R(crate::FieldReader<bool, bool>);
+impl LOOKUP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        LOOKUP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LOOKUP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"]
+pub struct LOOKUP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LOOKUP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"]
+pub struct WATCHDOG_R(crate::FieldReader<bool, bool>);
+impl WATCHDOG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WATCHDOG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WATCHDOG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"]
+pub struct WATCHDOG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WATCHDOG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `MEMERR` reader - Memory Error Reset Status"]
+pub struct MEMERR_R(crate::FieldReader<bool, bool>);
+impl MEMERR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        MEMERR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for MEMERR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&self) -> POR_R {
+        POR_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&self) -> EXTRST_R {
+        EXTRST_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&self) -> SYSRSTREQ_R {
+        SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&self) -> LOOKUP_R {
+        LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&self) -> WATCHDOG_R {
+        WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    pub fn memerr(&self) -> MEMERR_R {
+        MEMERR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&mut self) -> POR_W {
+        POR_W { w: self }
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&mut self) -> EXTRST_W {
+        EXTRST_W { w: self }
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&mut self) -> SYSRSTREQ_W {
+        SYSRSTREQ_W { w: self }
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&mut self) -> LOOKUP_W {
+        LOOKUP_W { w: self }
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&mut self) -> WATCHDOG_W {
+        WATCHDOG_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RAM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_cntl_ram0](index.html) module"]
+pub struct RST_CNTL_RAM0_SPEC;
+impl crate::RegisterSpec for RST_CNTL_RAM0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rst_cntl_ram0::R](R) reader structure"]
+impl crate::Readable for RST_CNTL_RAM0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rst_cntl_ram0::W](W) writer structure"]
+impl crate::Writable for RST_CNTL_RAM0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RST_CNTL_RAM0 to value 0x3f"]
+impl crate::Resettable for RST_CNTL_RAM0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x3f
+    }
+}

src/sysconfig/rst_cntl_ram1.rs

@@ -0,0 +1,321 @@
+#[doc = "Register `RST_CNTL_RAM1` reader"]
+pub struct R(crate::R<RST_CNTL_RAM1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RST_CNTL_RAM1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RST_CNTL_RAM1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RST_CNTL_RAM1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RST_CNTL_RAM1` writer"]
+pub struct W(crate::W<RST_CNTL_RAM1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RST_CNTL_RAM1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RST_CNTL_RAM1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RST_CNTL_RAM1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POR` reader - Power On Reset Status"]
+pub struct POR_R(crate::FieldReader<bool, bool>);
+impl POR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        POR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for POR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `POR` writer - Power On Reset Status"]
+pub struct POR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> POR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `EXTRST` reader - External Reset Status"]
+pub struct EXTRST_R(crate::FieldReader<bool, bool>);
+impl EXTRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        EXTRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for EXTRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `EXTRST` writer - External Reset Status"]
+pub struct EXTRST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EXTRST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_R(crate::FieldReader<bool, bool>);
+impl SYSRSTREQ_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SYSRSTREQ_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SYSRSTREQ_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SYSRSTREQ_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"]
+pub struct LOOKUP_R(crate::FieldReader<bool, bool>);
+impl LOOKUP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        LOOKUP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LOOKUP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"]
+pub struct LOOKUP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LOOKUP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"]
+pub struct WATCHDOG_R(crate::FieldReader<bool, bool>);
+impl WATCHDOG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WATCHDOG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WATCHDOG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"]
+pub struct WATCHDOG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WATCHDOG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `MEMERR` reader - Memory Error Reset Status"]
+pub struct MEMERR_R(crate::FieldReader<bool, bool>);
+impl MEMERR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        MEMERR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for MEMERR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&self) -> POR_R {
+        POR_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&self) -> EXTRST_R {
+        EXTRST_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&self) -> SYSRSTREQ_R {
+        SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&self) -> LOOKUP_R {
+        LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&self) -> WATCHDOG_R {
+        WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    pub fn memerr(&self) -> MEMERR_R {
+        MEMERR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&mut self) -> POR_W {
+        POR_W { w: self }
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&mut self) -> EXTRST_W {
+        EXTRST_W { w: self }
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&mut self) -> SYSRSTREQ_W {
+        SYSRSTREQ_W { w: self }
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&mut self) -> LOOKUP_W {
+        LOOKUP_W { w: self }
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&mut self) -> WATCHDOG_W {
+        WATCHDOG_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RAM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_cntl_ram1](index.html) module"]
+pub struct RST_CNTL_RAM1_SPEC;
+impl crate::RegisterSpec for RST_CNTL_RAM1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rst_cntl_ram1::R](R) reader structure"]
+impl crate::Readable for RST_CNTL_RAM1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rst_cntl_ram1::W](W) writer structure"]
+impl crate::Writable for RST_CNTL_RAM1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RST_CNTL_RAM1 to value 0x3f"]
+impl crate::Resettable for RST_CNTL_RAM1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x3f
+    }
+}

src/sysconfig/rst_cntl_rom.rs

@@ -0,0 +1,321 @@
+#[doc = "Register `RST_CNTL_ROM` reader"]
+pub struct R(crate::R<RST_CNTL_ROM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RST_CNTL_ROM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RST_CNTL_ROM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RST_CNTL_ROM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RST_CNTL_ROM` writer"]
+pub struct W(crate::W<RST_CNTL_ROM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RST_CNTL_ROM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RST_CNTL_ROM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RST_CNTL_ROM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POR` reader - Power On Reset Status"]
+pub struct POR_R(crate::FieldReader<bool, bool>);
+impl POR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        POR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for POR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `POR` writer - Power On Reset Status"]
+pub struct POR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> POR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `EXTRST` reader - External Reset Status"]
+pub struct EXTRST_R(crate::FieldReader<bool, bool>);
+impl EXTRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        EXTRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for EXTRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `EXTRST` writer - External Reset Status"]
+pub struct EXTRST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EXTRST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_R(crate::FieldReader<bool, bool>);
+impl SYSRSTREQ_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SYSRSTREQ_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SYSRSTREQ_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SYSRSTREQ_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"]
+pub struct LOOKUP_R(crate::FieldReader<bool, bool>);
+impl LOOKUP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        LOOKUP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LOOKUP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"]
+pub struct LOOKUP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LOOKUP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"]
+pub struct WATCHDOG_R(crate::FieldReader<bool, bool>);
+impl WATCHDOG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WATCHDOG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WATCHDOG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"]
+pub struct WATCHDOG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WATCHDOG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `MEMERR` reader - Memory Error Reset Status"]
+pub struct MEMERR_R(crate::FieldReader<bool, bool>);
+impl MEMERR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        MEMERR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for MEMERR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&self) -> POR_R {
+        POR_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&self) -> EXTRST_R {
+        EXTRST_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&self) -> SYSRSTREQ_R {
+        SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&self) -> LOOKUP_R {
+        LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&self) -> WATCHDOG_R {
+        WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    pub fn memerr(&self) -> MEMERR_R {
+        MEMERR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&mut self) -> POR_W {
+        POR_W { w: self }
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&mut self) -> EXTRST_W {
+        EXTRST_W { w: self }
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&mut self) -> SYSRSTREQ_W {
+        SYSRSTREQ_W { w: self }
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&mut self) -> LOOKUP_W {
+        LOOKUP_W { w: self }
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&mut self) -> WATCHDOG_W {
+        WATCHDOG_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ROM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_cntl_rom](index.html) module"]
+pub struct RST_CNTL_ROM_SPEC;
+impl crate::RegisterSpec for RST_CNTL_ROM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rst_cntl_rom::R](R) reader structure"]
+impl crate::Readable for RST_CNTL_ROM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rst_cntl_rom::W](W) writer structure"]
+impl crate::Writable for RST_CNTL_ROM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RST_CNTL_ROM to value 0x3f"]
+impl crate::Resettable for RST_CNTL_ROM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x3f
+    }
+}

src/sysconfig/rst_stat.rs

@@ -0,0 +1,321 @@
+#[doc = "Register `RST_STAT` reader"]
+pub struct R(crate::R<RST_STAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RST_STAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RST_STAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RST_STAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RST_STAT` writer"]
+pub struct W(crate::W<RST_STAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RST_STAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RST_STAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RST_STAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POR` reader - Power On Reset Status"]
+pub struct POR_R(crate::FieldReader<bool, bool>);
+impl POR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        POR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for POR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `POR` writer - Power On Reset Status"]
+pub struct POR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> POR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `EXTRST` reader - External Reset Status"]
+pub struct EXTRST_R(crate::FieldReader<bool, bool>);
+impl EXTRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        EXTRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for EXTRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `EXTRST` writer - External Reset Status"]
+pub struct EXTRST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> EXTRST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_R(crate::FieldReader<bool, bool>);
+impl SYSRSTREQ_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SYSRSTREQ_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SYSRSTREQ_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"]
+pub struct SYSRSTREQ_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SYSRSTREQ_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"]
+pub struct LOOKUP_R(crate::FieldReader<bool, bool>);
+impl LOOKUP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        LOOKUP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LOOKUP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"]
+pub struct LOOKUP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LOOKUP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"]
+pub struct WATCHDOG_R(crate::FieldReader<bool, bool>);
+impl WATCHDOG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WATCHDOG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WATCHDOG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"]
+pub struct WATCHDOG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WATCHDOG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `MEMERR` reader - Memory Error Reset Status"]
+pub struct MEMERR_R(crate::FieldReader<bool, bool>);
+impl MEMERR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        MEMERR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for MEMERR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&self) -> POR_R {
+        POR_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&self) -> EXTRST_R {
+        EXTRST_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&self) -> SYSRSTREQ_R {
+        SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&self) -> LOOKUP_R {
+        LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&self) -> WATCHDOG_R {
+        WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Memory Error Reset Status"]
+    #[inline(always)]
+    pub fn memerr(&self) -> MEMERR_R {
+        MEMERR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Power On Reset Status"]
+    #[inline(always)]
+    pub fn por(&mut self) -> POR_W {
+        POR_W { w: self }
+    }
+    #[doc = "Bit 1 - External Reset Status"]
+    #[inline(always)]
+    pub fn extrst(&mut self) -> EXTRST_W {
+        EXTRST_W { w: self }
+    }
+    #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
+    #[inline(always)]
+    pub fn sysrstreq(&mut self) -> SYSRSTREQ_W {
+        SYSRSTREQ_W { w: self }
+    }
+    #[doc = "Bit 3 - LOOKUP Reset Status"]
+    #[inline(always)]
+    pub fn lookup(&mut self) -> LOOKUP_W {
+        LOOKUP_W { w: self }
+    }
+    #[doc = "Bit 4 - WATCHDOG Reset Status"]
+    #[inline(always)]
+    pub fn watchdog(&mut self) -> WATCHDOG_W {
+        WATCHDOG_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "System Reset Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_stat](index.html) module"]
+pub struct RST_STAT_SPEC;
+impl crate::RegisterSpec for RST_STAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rst_stat::R](R) reader structure"]
+impl crate::Readable for RST_STAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rst_stat::W](W) writer structure"]
+impl crate::Writable for RST_STAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RST_STAT to value 0"]
+impl crate::Resettable for RST_STAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/spw_m4_ctrl.rs

@@ -0,0 +1,197 @@
+#[doc = "Register `SPW_M4_CTRL` reader"]
+pub struct R(crate::R<SPW_M4_CTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SPW_M4_CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SPW_M4_CTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SPW_M4_CTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SPW_M4_CTRL` writer"]
+pub struct W(crate::W<SPW_M4_CTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SPW_M4_CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SPW_M4_CTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SPW_M4_CTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LREN` reader - Lockup reset enable"]
+pub struct LREN_R(crate::FieldReader<bool, bool>);
+impl LREN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        LREN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LREN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LREN` writer - Lockup reset enable"]
+pub struct LREN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LREN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "Field `SPW_PAD_EN` reader - SPW pad enable"]
+pub struct SPW_PAD_EN_R(crate::FieldReader<bool, bool>);
+impl SPW_PAD_EN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPW_PAD_EN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPW_PAD_EN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPW_PAD_EN` writer - SPW pad enable"]
+pub struct SPW_PAD_EN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPW_PAD_EN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Field `REG_WR_KEY` reader - Fuse-analog register writes enabled when key = 0xfeed"]
+pub struct REG_WR_KEY_R(crate::FieldReader<u16, u16>);
+impl REG_WR_KEY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u16) -> Self {
+        REG_WR_KEY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for REG_WR_KEY_R {
+    type Target = crate::FieldReader<u16, u16>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `REG_WR_KEY` writer - Fuse-analog register writes enabled when key = 0xfeed"]
+pub struct REG_WR_KEY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> REG_WR_KEY_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 17 - Lockup reset enable"]
+    #[inline(always)]
+    pub fn lren(&self) -> LREN_R {
+        LREN_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - SPW pad enable"]
+    #[inline(always)]
+    pub fn spw_pad_en(&self) -> SPW_PAD_EN_R {
+        SPW_PAD_EN_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"]
+    #[inline(always)]
+    pub fn reg_wr_key(&self) -> REG_WR_KEY_R {
+        REG_WR_KEY_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bit 17 - Lockup reset enable"]
+    #[inline(always)]
+    pub fn lren(&mut self) -> LREN_W {
+        LREN_W { w: self }
+    }
+    #[doc = "Bit 16 - SPW pad enable"]
+    #[inline(always)]
+    pub fn spw_pad_en(&mut self) -> SPW_PAD_EN_W {
+        SPW_PAD_EN_W { w: self }
+    }
+    #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"]
+    #[inline(always)]
+    pub fn reg_wr_key(&mut self) -> REG_WR_KEY_W {
+        REG_WR_KEY_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPW M4 control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spw_m4_ctrl](index.html) module"]
+pub struct SPW_M4_CTRL_SPEC;
+impl crate::RegisterSpec for SPW_M4_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [spw_m4_ctrl::R](R) reader structure"]
+impl crate::Readable for SPW_M4_CTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [spw_m4_ctrl::W](W) writer structure"]
+impl crate::Writable for SPW_M4_CTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SPW_M4_CTRL to value 0x0003_0000"]
+impl crate::Resettable for SPW_M4_CTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0003_0000
+    }
+}

src/sysconfig/sw_clkdiv10.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `SW_CLKDIV10` reader"]
+pub struct R(crate::R<SW_CLKDIV10_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SW_CLKDIV10_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SW_CLKDIV10_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SW_CLKDIV10_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SW_CLKDIV10` writer"]
+pub struct W(crate::W<SW_CLKDIV10_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SW_CLKDIV10_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SW_CLKDIV10_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SW_CLKDIV10_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SW_CLKDIV10` reader - Defines the initial value for the SpW clock, defaults to divide by ten"]
+pub struct SW_CLKDIV10_R(crate::FieldReader<u8, u8>);
+impl SW_CLKDIV10_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        SW_CLKDIV10_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SW_CLKDIV10_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SW_CLKDIV10` writer - Defines the initial value for the SpW clock, defaults to divide by ten"]
+pub struct SW_CLKDIV10_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SW_CLKDIV10_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"]
+    #[inline(always)]
+    pub fn sw_clkdiv10(&self) -> SW_CLKDIV10_R {
+        SW_CLKDIV10_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"]
+    #[inline(always)]
+    pub fn sw_clkdiv10(&mut self) -> SW_CLKDIV10_W {
+        SW_CLKDIV10_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Initial SpW Clock Divider Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sw_clkdiv10](index.html) module"]
+pub struct SW_CLKDIV10_SPEC;
+impl crate::RegisterSpec for SW_CLKDIV10_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sw_clkdiv10::R](R) reader structure"]
+impl crate::Readable for SW_CLKDIV10_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sw_clkdiv10::W](W) writer structure"]
+impl crate::Writable for SW_CLKDIV10_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SW_CLKDIV10 to value 0x09"]
+impl crate::Resettable for SW_CLKDIV10_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x09
+    }
+}

src/sysconfig/tim_clk_enable.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `TIM_CLK_ENABLE` reader"]
+pub struct R(crate::R<TIM_CLK_ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TIM_CLK_ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TIM_CLK_ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TIM_CLK_ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TIM_CLK_ENABLE` writer"]
+pub struct W(crate::W<TIM_CLK_ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TIM_CLK_ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TIM_CLK_ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TIM_CLK_ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TIMERS` reader - Clock enable of a given TIMER"]
+pub struct TIMERS_R(crate::FieldReader<u32, u32>);
+impl TIMERS_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        TIMERS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TIMERS_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TIMERS` writer - Clock enable of a given TIMER"]
+pub struct TIMERS_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TIMERS_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:23 - Clock enable of a given TIMER"]
+    #[inline(always)]
+    pub fn timers(&self) -> TIMERS_R {
+        TIMERS_R::new((self.bits & 0x00ff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Clock enable of a given TIMER"]
+    #[inline(always)]
+    pub fn timers(&mut self) -> TIMERS_W {
+        TIMERS_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "TIM Enable Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tim_clk_enable](index.html) module"]
+pub struct TIM_CLK_ENABLE_SPEC;
+impl crate::RegisterSpec for TIM_CLK_ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [tim_clk_enable::R](R) reader structure"]
+impl crate::Readable for TIM_CLK_ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [tim_clk_enable::W](W) writer structure"]
+impl crate::Writable for TIM_CLK_ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"]
+impl crate::Resettable for TIM_CLK_ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/sysconfig/tim_reset.rs

@@ -0,0 +1,103 @@
+#[doc = "Register `TIM_RESET` reader"]
+pub struct R(crate::R<TIM_RESET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TIM_RESET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TIM_RESET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TIM_RESET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TIM_RESET` writer"]
+pub struct W(crate::W<TIM_RESET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TIM_RESET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TIM_RESET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TIM_RESET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TIM_RESET` reader - Reset of a given TIMER"]
+pub struct TIM_RESET_R(crate::FieldReader<u32, u32>);
+impl TIM_RESET_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        TIM_RESET_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TIM_RESET_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TIM_RESET` writer - Reset of a given TIMER"]
+pub struct TIM_RESET_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TIM_RESET_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:23 - Reset of a given TIMER"]
+    #[inline(always)]
+    pub fn tim_reset(&self) -> TIM_RESET_R {
+        TIM_RESET_R::new((self.bits & 0x00ff_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Reset of a given TIMER"]
+    #[inline(always)]
+    pub fn tim_reset(&mut self) -> TIM_RESET_W {
+        TIM_RESET_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "TIM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tim_reset](index.html) module"]
+pub struct TIM_RESET_SPEC;
+impl crate::RegisterSpec for TIM_RESET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [tim_reset::R](R) reader structure"]
+impl crate::Readable for TIM_RESET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [tim_reset::W](W) writer structure"]
+impl crate::Writable for TIM_RESET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"]
+impl crate::Resettable for TIM_RESET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/sysconfig/wakeup_cnt.rs

@@ -0,0 +1,150 @@
+#[doc = "Register `WAKEUP_CNT` reader"]
+pub struct R(crate::R<WAKEUP_CNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<WAKEUP_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<WAKEUP_CNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<WAKEUP_CNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `WAKEUP_CNT` writer"]
+pub struct W(crate::W<WAKEUP_CNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<WAKEUP_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<WAKEUP_CNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<WAKEUP_CNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNTSTRT` reader - Launch SLP mode in analog block"]
+pub struct CNTSTRT_R(crate::FieldReader<bool, bool>);
+impl CNTSTRT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CNTSTRT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CNTSTRT_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CNTSTRT` writer - Launch SLP mode in analog block"]
+pub struct CNTSTRT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CNTSTRT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `WKUP_CNT` reader - Used to set a time to wake up the processor after the device has been put in a low power state"]
+pub struct WKUP_CNT_R(crate::FieldReader<u8, u8>);
+impl WKUP_CNT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        WKUP_CNT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WKUP_CNT_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WKUP_CNT` writer - Used to set a time to wake up the processor after the device has been put in a low power state"]
+pub struct WKUP_CNT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WKUP_CNT_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 3 - Launch SLP mode in analog block"]
+    #[inline(always)]
+    pub fn cntstrt(&self) -> CNTSTRT_R {
+        CNTSTRT_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"]
+    #[inline(always)]
+    pub fn wkup_cnt(&self) -> WKUP_CNT_R {
+        WKUP_CNT_R::new((self.bits & 0x07) as u8)
+    }
+}
+impl W {
+    #[doc = "Bit 3 - Launch SLP mode in analog block"]
+    #[inline(always)]
+    pub fn cntstrt(&mut self) -> CNTSTRT_W {
+        CNTSTRT_W { w: self }
+    }
+    #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"]
+    #[inline(always)]
+    pub fn wkup_cnt(&mut self) -> WKUP_CNT_W {
+        WKUP_CNT_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Wakeup Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wakeup_cnt](index.html) module"]
+pub struct WAKEUP_CNT_SPEC;
+impl crate::RegisterSpec for WAKEUP_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [wakeup_cnt::R](R) reader structure"]
+impl crate::Readable for WAKEUP_CNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [wakeup_cnt::W](W) writer structure"]
+impl crate::Writable for WAKEUP_CNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets WAKEUP_CNT to value 0x07"]
+impl crate::Resettable for WAKEUP_CNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x07
+    }
+}