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Browse Source
This commit is contained in:
Robin Mueller
2025-10-28 22:54:11 +01:00
parent cdf5b2a07e
commit 78396da160
61 changed files with 196 additions and 156 deletions
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8
README.md Normal file
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@@ -0,0 +1,8 @@
Vorago Microcontroller Rust Repository
=========
This monorepo contains the following three workspaces / projects with dedicated READMEs:
- [`va108xx`](https://github.com/us-irs/vorago-rs/tree/main/va108xx): Support for the VA108xx family of Cortex-M0 based MCUs
- [`va416xx`](https://github.com/us-irs/vorago-rs/tree/main/va416xx): Support for the VA416xx family of Cortex-M4 based MCUs
- [`vorago-shared-hal`](https://github.com/us-irs/vorago-rs/tree/main/vorago-shared-hal): Shared peripheral used by both the VA108xx and VA416xx family

28
justfile
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@@ -1,13 +1,14 @@
all: check-all \
build-all \
fmt-all \
check-fmt-all \
clippy-all \
docs-all
check-all: check-va108xx check-va416xx
build-all: build-va108xx build-va416xx
fmt-all: fmt-va108xx fmt-va416xx
clippy-all: clippy-va108xx clippy-va416xx
check-fmt-all: check-fmt-va108xx check-fmt-va416xx
fmt-all: fmt-va108xx fmt-va416xx fmt-shared-hal
clippy-all: clippy-va108xx clippy-va416xx clippy-shared-hal
docs-all: docs-va108xx docs-va416xx
clean-all: clean-va108xx clean-va416xx
@@ -34,13 +35,25 @@ build-va416xx:
cargo build --target thumbv7em-none-eabihf
[working-directory: 'va108xx']
fmt-va108xx:
check-fmt-va108xx:
cargo fmt --all -- --check
[working-directory: 'va416xx']
fmt-va416xx:
check-fmt-va416xx:
cargo fmt --all -- --check
[working-directory: 'va108xx']
fmt-va108xx:
cargo fmt
[working-directory: 'va416xx']
fmt-va416xx:
cargo fmt
[working-directory: 'vorago-shared-hal']
fmt-shared-hal:
cargo fmt
[working-directory: 'va108xx']
clippy-va108xx:
cargo clippy --target thumbv6m-none-eabi -- -D warnings
@@ -49,6 +62,11 @@ clippy-va108xx:
clippy-va416xx:
cargo clippy --target thumbv7em-none-eabihf -- -D warnings
[working-directory: 'vorago-shared-hal']
clippy-shared-hal:
cargo clippy --target thumbv7em-none-eabihf --features "vor4x" -- -D warnings
cargo clippy --target thumbv6m-none-eabi --features "vor1x" -- -D warnings
[working-directory: 'va108xx']
docs-va108xx:
RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx --all-features

22
va108xx/README.md
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@@ -1,4 +1,4 @@
[![build](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml)
[![build](https://github.com/us-irs/vorago-rs/actions/workflows/va108xx.yml/badge.svg)](https://github.com/us-irs/vorago-rs/actions/workflows/va108xx.yml)
Vorago VA108xx Rust Support
=========
@@ -10,32 +10,32 @@ of devices.
This workspace contains the following released crates:
- The [`va108xx`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx) PAC
- The [`va108xx`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/va108xx) PAC
crate containing basic low-level register definition.
- The [`va108xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal)
- The [`va108xx-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/va108xx-hal)
HAL crate containing higher-level abstractions on top of the PAC register crate.
- The [`va108xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-embassy)
crate containing support for running the embassy-rs RTOS.
- The [`vorago-reb1`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1)
- The [`va108xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/va108xx-embassy)
crate containing support for running the embassy-rs asynchronous runtime.
- The [`vorago-reb1`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1)
BSP crate containing support for the REB1 development board.
It also contains the following helper crates:
- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/bootloader)
- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/bootloader)
crate contains a sample bootloader strongly based on the one provided by Vorago.
- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/flashloader)
crate contains a sample flashloader which is able to update the redundant images in the NVM which
is compatible to the provided bootloader as well.
- The [`board-tests`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/board-tests)
- The [`board-tests`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/board-tests)
contains an application which can be used to test the libraries on the board.
- The [`examples`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples)
- The [`examples`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples)
folder contains various example applications crates using the HAL and the PAC.
This folder also contains dedicated example applications using the
[`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy)
native Rust RTOSes.
The majority of the HAL implementation and the Embassy-rs support are contained in the external
[`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) crate.
[`vorago-shared-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/vorago-shared-hal) crate.
## Using the `.cargo/config.toml` file

2
va108xx/bootloader/README.md
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@@ -28,7 +28,7 @@ of time before booting. This allows to catch the RTT printout, but should probab
for production firmware.
This bootloader does not provide tools to flash the NVM memory by itself. Instead, you can use
the [flashloader](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
the [flashloader](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/flashloader)
application to perform this task using a CCSDS interface via a UART.
The bootloader performs the following steps:

4
va108xx/examples/embassy/Cargo.toml
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@@ -7,8 +7,8 @@ edition = "2021"
cfg-if = "1"
cortex-m-rt = "0.7"
embedded-hal-async = "1"
embedded-io = "0.6"
embedded-io-async = "0.6"
embedded-io = "0.7"
embedded-io-async = "0.7"
heapless = "0.9"
static_cell = "2"

2
va108xx/examples/rtic/Cargo.toml
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@@ -5,7 +5,7 @@ edition = "2021"
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
embedded-io = "0.6"
embedded-io = "0.7"
defmt-rtt = "1"
defmt = "1"
panic-probe = { version = "1", features = ["defmt"] }

2
va108xx/examples/simple/Cargo.toml
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@@ -12,7 +12,7 @@ defmt = "1"
panic-probe = { version = "1", features = ["defmt"] }
embedded-hal = "1"
embedded-hal-nb = "1"
embedded-io = "0.6"
embedded-io = "0.7"
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
[dependencies.va108xx-hal]

9
va108xx/flashloader/Cargo.toml
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@@ -6,15 +6,16 @@ edition = "2021"
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
cortex-m-rt = "0.7"
embedded-io = "0.6"
embedded-io = "0.7"
defmt = "1"
defmt-rtt = { version = "1" }
panic-probe = { version = "1", features = ["print-defmt"] }
num_enum = { version = "0.7", default-features = false }
cobs = { version = "0.4", default-features = false }
satrs = { version = "0.3.0-alpha.1", default-features = false }
cobs = { version = "0.5", default-features = false }
satrs = { version = "0.3.0-alpha.1", git = "https://egit.irs.uni-stuttgart.de/rust/sat-rs.git", default-features = false, features = ["defmt"] }
arbitrary-int = "2"
ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
spacepackets = { version = "0.15", default-features = false, features = ["defmt"] }
# spacepackets = { version = "0.17", path = "https://egit.irs.uni-stuttgart.de/rust/spacepackets.git", default-features = false, features = ["defmt"] }
# Even though we do not use this directly, we need to activate this feature explicitely
# so that RTIC compiles because thumv6 does not have CAS operations natively.
portable-atomic = {version = "1", features = ["unsafe-assume-single-core"]}

2
va108xx/flashloader/README.md
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@@ -7,7 +7,7 @@ called the `image-loader.py` which can be used to upload compiled images to the
application to write them to the NVM.
Please note that the both the application and the image loader are tailored towards usage
with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/bootloader).
with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/bootloader).
The software can quickly be adapted to interface with a real primary on-board software instead of
the Python script provided here to upload images because it uses a low-level CCSDS based packet

24
va108xx/flashloader/src/main.rs
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@@ -59,13 +59,15 @@ pub const PREFERRED_SLOT_OFFSET: u32 = 0x20000 - 1;
#[rtic::app(device = pac, dispatchers = [OC20, OC21, OC22])]
mod app {
use super::*;
use arbitrary_int::traits::Integer as _;
use arbitrary_int::{u11, u14};
use cortex_m::asm;
use embedded_io::Write;
use rtic::Mutex;
use rtic_monotonics::systick::prelude::*;
use satrs::pus::verification::{FailParams, VerificationReportCreator};
use spacepackets::ecss::PusServiceId;
use spacepackets::ecss::{
use satrs::spacepackets::ecss::PusServiceId;
use satrs::spacepackets::ecss::{
tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
};
use va108xx_hal::pins::PinsA;
@@ -127,7 +129,7 @@ mod app {
// Unwrap is okay, we explicitely set the interrupt ID.
let mut rx = rx.into_rx_with_irq();
let verif_reporter = VerificationReportCreator::new(0).unwrap();
let verif_reporter = VerificationReportCreator::new(u11::new(0));
let mut rx_context = InterruptContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context)
@@ -284,14 +286,14 @@ mod app {
let tm = cx
.local
.verif_reporter
.acceptance_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.acceptance_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("acceptance success failed");
write_and_send(&tm);
let tm = cx
.local
.verif_reporter
.start_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.start_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("acceptance success failed");
write_and_send(&tm);
@@ -310,7 +312,7 @@ mod app {
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
};
@@ -341,7 +343,7 @@ mod app {
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
}
@@ -351,7 +353,7 @@ mod app {
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
} else if pus_tc.service() == PusServiceId::MemoryManagement as u8 {
@@ -361,7 +363,7 @@ mod app {
.step_success(
cx.local.src_data_buf,
&request_id,
0,
u14::ZERO,
0,
&[],
EcssEnumU8::new(0),
@@ -411,7 +413,7 @@ mod app {
.completion_failure(
cx.local.src_data_buf,
&request_id,
0,
u14::ZERO,
0,
FailParams::new(&[], &EcssEnumU8::new(0), &[]),
)
@@ -419,7 +421,7 @@ mod app {
} else {
cx.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed")
};
write_and_send(&tm);

8
va108xx/va108xx-embassy/Cargo.toml
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@@ -4,15 +4,15 @@ version = "0.3.0"
edition = "2021"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies]
vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
va108xx-hal = { version = "0.12" }
vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor1x"] }
va108xx-hal = { version = "0.12", path = "../va108xx-hal" }
[features]
default = ["irq-oc30-oc31"]

4
va108xx/va108xx-embassy/src/lib.rs
View File

@@ -29,9 +29,9 @@
//!
//! ## Examples
//!
//! [embassy example projects](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy)
//! [embassy example projects](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/embassy)
#![no_std]
#![cfg_attr(docsrs, feature(doc_auto_cfg))]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[cfg(feature = "irqs-in-lib")]
use va108xx_hal::pac::{self, interrupt};

8
va108xx/va108xx-hal/Cargo.toml
View File

@@ -4,18 +4,18 @@ version = "0.12.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor1x"] }
fugit = "0.3"
thiserror = { version = "2", default-features = false }
va108xx = { version = "0.6", default-features = false, features = ["critical-section", "defmt"] }
va108xx = { version = "0.6", path = "../va108xx", default-features = false, features = ["critical-section", "defmt"] }
defmt = { version = "1", optional = true }
[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]

4
va108xx/va108xx-hal/README.md
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@@ -4,7 +4,7 @@
# HAL for the Vorago VA108xx MCU family
This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional
hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx).
hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/va108xx).
It is the result of reading the datasheet for the device and encoding a type-safe layer over the
raw PAC. This crate also implements traits specified by the
@@ -33,7 +33,7 @@ your custom board.
The hello world of embedded development is usually to blinky a LED. This example
is contained within the
[examples folder](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs).
[examples folder](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/blinky.rs).
1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
2. Create a new binary crate with `cargo init`

4
va108xx/va108xx-hal/src/gpio/mod.rs
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@@ -15,6 +15,6 @@
//!
//! ## Examples
//!
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/embassy/src/bin/async-gpio.rs)
pub use vorago_shared_hal::gpio::*;

2
va108xx/va108xx-hal/src/i2c.rs
View File

@@ -2,5 +2,5 @@
//!
//! ## Examples
//!
//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/adt75-temp-sensor.rs)
pub use vorago_shared_hal::i2c::*;

2
va108xx/va108xx-hal/src/pwm.rs
View File

@@ -4,5 +4,5 @@
//!
//! ## Examples
//!
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/pwm.rs)
pub use vorago_shared_hal::pwm::*;

6
va108xx/va108xx-hal/src/spi/mod.rs
View File

@@ -6,7 +6,7 @@
//!
//! ## Examples
//!
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/spi.rs)
//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/max11519-adc.rs)
//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/src/m95m01.rs)
pub use vorago_shared_hal::spi::*;

4
va108xx/va108xx-hal/src/timer.rs
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@@ -2,6 +2,6 @@
//!
//! ## Examples
//!
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/cascade.rs)
pub use vorago_shared_hal::timer::*;

10
va108xx/va108xx-hal/src/uart/mod.rs
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@@ -9,9 +9,9 @@
//!
//! ## Examples
//!
//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs)
//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/uart.rs)
//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs)
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/embassy/src/bin/async-uart-tx.rs)
pub use vorago_shared_hal::uart::*;

4
va108xx/va108xx/Cargo.toml
View File

@@ -4,8 +4,8 @@ version = "0.6.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "PAC for the Vorago VA108xx family of microcontrollers"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
categories = ["embedded", "no-std", "hardware-support"]

6
va108xx/vorago-reb1/Cargo.toml
View File

@@ -4,8 +4,8 @@ version = "0.9.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "Board Support Crate for the Vorago REB1 development board"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "reb1", "cortex-m", "vorago", "va108xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"]
@@ -19,7 +19,7 @@ bitbybit = "1.3"
arbitrary-int = "2"
max116xx-10bit = "0.3"
va108xx-hal = { version = "0.12", features = ["rt"] }
va108xx-hal = { version = "0.12", path = "../va108xx-hal", features = ["rt"] }
[features]
rt = ["va108xx-hal/rt"]

2
va108xx/vorago-reb1/README.md
View File

@@ -6,5 +6,5 @@
This is the Rust **B**oard **S**upport **P**ackage crate for the Vorago REB1 development board.
Its aim is to provide drivers for the board features of the REB1 board
The BSP builds on top of the [HAL crate for VA108xx devices](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal).
The BSP builds on top of the [HAL crate for VA108xx devices](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/va108xx-hal).
The example folder contains some example applications using the on-board peripherals.

4
va108xx/vorago-reb1/src/button.rs
View File

@@ -2,8 +2,8 @@
//!
//! ## Examples
//!
//! - [Button Blinky with IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs)
//! - [Button Blinky with IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs)
//! - [Button Blinky with IRQs](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/blinky-button-irq.rs)
//! - [Button Blinky with IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/blinky-button-rtic.rs)
use va108xx_hal::{
clock::FilterClockSelect,
gpio::{FilterType, Input, InterruptEdge, InterruptLevel, Pin},

6
va108xx/vorago-reb1/src/leds.rs
View File

@@ -2,9 +2,9 @@
//!
//! ## Examples
//!
//! - [LED example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-leds.rs)
//! - [Button Blinky using IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs)
//! - [Button Blinky using IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs)
//! - [LED example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/blinky-leds.rs)
//! - [Button Blinky using IRQs](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/blinky-button-irq.rs)
//! - [Button Blinky using IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/blinky-button-rtic.rs)
use va108xx_hal::{
gpio::{Output, PinState},
pins::{Pa10, Pa6, Pa7, Pin},

2
va108xx/vorago-reb1/src/max11619.rs
View File

@@ -2,7 +2,7 @@
//!
//! ## Examples
//!
//! - [ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11619-adc.rs)
//! - [ADC example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/max11619-adc.rs)
use core::convert::Infallible;
use embedded_hal::spi::SpiDevice;
use max116xx_10bit::{

2
va108xx/vorago-reb1/src/temp_sensor.rs
View File

@@ -4,7 +4,7 @@
//!
//! ## Examples
//!
//! - [Temperature Sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
//! - [Temperature Sensor example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/vorago-reb1/examples/adt75-temp-sensor.rs)
use embedded_hal::i2c::{I2c, SevenBitAddress};
use va108xx_hal::{
i2c::{Error, I2cMaster, I2cSpeed, InitError, MasterConfig},

18
va416xx/README.md
View File

@@ -1,4 +1,4 @@
[![build](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml)
[![build](https://github.com/us-irs/vorago-rs/actions/workflows/va416xx.yml/badge.svg)](https://github.com/us-irs/vorago-rs/actions/workflows/va416xx.yml)
Vorago VA416xx Rust Support
=========
@@ -10,23 +10,23 @@ of devices.
This workspace contains the following crates:
- The [`va416xx`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx)
- The [`va416xx`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/va416xx)
PAC crate containing basic low-level register definition
- The [`va416xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal)
- The [`va416xx-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/va416xx-hal)
HAL crate containing higher-level abstractions on top of the PAC register crate.
- The [`va416xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-embassy)
crate containing support for running the embassy-rs RTOS.
- The [`vorago-peb1`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/vorago-peb1)
- The [`va416xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/va416xx-embassy)
crate containing support for running the embassy-rs asynchronous runtime.
- The [`vorago-peb1`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/vorago-peb1)
BSP crate containing support for the PEB1 development board.
It also contains the following helper crates:
- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/bootloader)
- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/bootloader)
crate contains a sample bootloader strongly based on the one provided by Vorago.
- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader)
- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/flashloader)
crate contains a sample flashloader which is able to update the redundant images in the NVM which
is compatible to the provided bootloader as well.
- The [`examples`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples)
- The [`examples`](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples)
folder contains various example applications crates using the HAL and the PAC.
This folder also contains dedicated example applications using the
[`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy)

2
va416xx/bootloader/README.md
View File

@@ -26,7 +26,7 @@ but does not scale that clock up. It also uses a word (4 bytes) instead of a hal
and uses the ISO 3309 CRC32 standard checksum.
This bootloader does not provide tools to flash the NVM memories by itself. Instead, you can use
the [flashloader](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader)
the [flashloader](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/flashloader)
application to perform this task using a CCSDS interface via a UART.
The bootloader performs the following steps:

4
va416xx/examples/embassy/Cargo.toml
View File

@@ -7,9 +7,9 @@ edition = "2021"
cortex-m = "0.7"
cortex-m-rt = "0.7"
cfg-if = "1"
embedded-io = "0.6"
embedded-io = "0.7"
embedded-hal-async = "1"
embedded-io-async = "0.6"
embedded-io-async = "0.7"
heapless = "0.9"
defmt-rtt = "1"

3
va416xx/examples/simple/Cargo.toml
View File

@@ -13,11 +13,12 @@ panic-probe = { version = "1", features = ["defmt"] }
embedded-hal = "1"
embedded-hal-nb = "1"
nb = "1"
embedded-io = "0.6"
embedded-io = "0.7"
panic-halt = "1"
accelerometer = "0.12"
va416xx-hal = { version = "0.6", path = "../../va416xx-hal", features = ["va41630", "defmt"] }
va416xx = { version = "0.5", path = "../../va416xx" }
[dependencies.vorago-peb1]
path = "../../vorago-peb1"

2
va416xx/examples/simple/src/main.rs
View File

@@ -4,6 +4,8 @@
use cortex_m_rt::entry;
use panic_halt as _;
// Need this for linking to work.
use va416xx as _;
#[entry]
fn main() -> ! {

8
va416xx/flashloader/Cargo.toml
View File

@@ -5,16 +5,16 @@ edition = "2021"
[dependencies]
cortex-m = "0.7"
embedded-io = "0.6"
embedded-io = "0.7"
defmt-rtt = "1"
defmt = "1"
panic-probe = { version = "1", features = ["defmt"] }
static_cell = "2"
satrs = { version = "0.3.0-alpha.1", default-features = false }
ringbuf = { version = "0.4", default-features = false }
once_cell = { version = "1", default-features = false, features = ["critical-section"] }
spacepackets = { version = "0.15", default-features = false, features = ["defmt"] }
cobs = { version = "0.4", default-features = false }
satrs = { version = "0.3.0-alpha.1", git = "https://egit.irs.uni-stuttgart.de/rust/sat-rs.git", default-features = false, features = ["defmt"] }
cobs = { version = "0.5", default-features = false }
arbitrary-int = "2"
va416xx-hal = { version = "0.6", features = ["va41630", "defmt"], path = "../va416xx-hal" }

2
va416xx/flashloader/README.md
View File

@@ -7,7 +7,7 @@ called the `image-loader.py` which can be used to upload compiled images to the
application to write them to the NVM.
Please note that the both the application and the image loader are tailored towards usage
with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/bootloader).
with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/bootloader).
The software can quickly be adapted to interface with a real primary on-board software instead of
the Python script provided here to upload images because it uses a low-level CCSDS based packet

20
va416xx/flashloader/src/main.rs
View File

@@ -93,6 +93,8 @@ pub const APP_B_END_ADDR: u32 = 0x40000;
#[rtic::app(device = pac, dispatchers = [U1, U2, U3])]
mod app {
use super::*;
use arbitrary_int::traits::Integer as _;
use arbitrary_int::{u11, u14};
use cortex_m::asm;
use embedded_io::Write;
// Import panic provider.
@@ -102,8 +104,8 @@ mod app {
use rtic::Mutex;
use rtic_monotonics::systick::prelude::*;
use satrs::pus::verification::VerificationReportCreator;
use spacepackets::ecss::PusServiceId;
use spacepackets::ecss::{
use satrs::spacepackets::ecss::PusServiceId;
use satrs::spacepackets::ecss::{
tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
};
use va416xx_hal::clock::ClockConfigurator;
@@ -175,7 +177,7 @@ mod app {
.unwrap();
let (tx, rx) = uart0.split();
let verif_reporter = VerificationReportCreator::new(0).unwrap();
let verif_reporter = VerificationReportCreator::new(u11::new(0));
let (buf_prod_tm, buf_cons_tm) = BUF_RB_TM
.init(StaticRb::<u8, BUF_RB_SIZE_TM>::default())
@@ -360,14 +362,14 @@ mod app {
let tm = cx
.local
.verif_reporter
.acceptance_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.acceptance_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("acceptance success failed");
write_and_send(&tm);
let tm = cx
.local
.verif_reporter
.start_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.start_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("acceptance success failed");
write_and_send(&tm);
@@ -387,7 +389,7 @@ mod app {
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
};
@@ -405,7 +407,7 @@ mod app {
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
} else if pus_tc.service() == PusServiceId::MemoryManagement as u8 {
@@ -415,7 +417,7 @@ mod app {
.step_success(
cx.local.src_data_buf,
&request_id,
0,
u14::ZERO,
0,
&[],
EcssEnumU8::new(0),
@@ -460,7 +462,7 @@ mod app {
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
.completion_success(cx.local.src_data_buf, &request_id, u14::ZERO, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
defmt::info!("NVM operation done");

6
va416xx/va416xx-embassy/Cargo.toml
View File

@@ -4,14 +4,14 @@ version = "0.1.2"
edition = "2021"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
description = "Embassy-rs support for the Vorago VA416xx family of microcontrollers"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies]
vorago-shared-hal = { version = "0.2", features = ["vor4x"] }
vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor4x"] }
va416xx-hal = { version = "0.6", path = "../va416xx-hal" }
[features]

8
va416xx/va416xx-hal/Cargo.toml
View File

@@ -4,18 +4,18 @@ version = "0.6.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA416xx family of MCUs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
va416xx = { version = "0.5", features = ["critical-section"], default-features = false }
va416xx = { version = "0.5", path = "../va416xx", features = ["critical-section"], default-features = false }
derive-mmio = "0.6.1"
static_assertions = "1.1"
vorago-shared-hal = { version = "0.2", features = ["vor4x"] }
vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor4x"] }
libm = "0.2"
nb = "1"

4
va416xx/va416xx-hal/README.md
View File

@@ -41,12 +41,12 @@ your custom board.
The hello world of embedded development is usually to blinky a LED. This example
is contained within the
[examples folder](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/blinky.rs).
[examples folder](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/blinky.rs).
1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
2. Create a new binary crate with `cargo init`
3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml`
file. You can use [this](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/.cargo/def-config.toml)
file. You can use [this](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/.cargo/config.toml.template)
sample file as a starting point.
4. Copy the `memory.x` file into your project. This file contains information required by the linker.
5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate

4
va416xx/va416xx-hal/src/adc.rs
View File

@@ -2,8 +2,8 @@
//!
//! ## Examples
//!
//! - [ADC and DAC example](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/dac-adc.rs)
//! - [ADC](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/adc.rs)
//! - [ADC and DAC example](https://github.com/us-irs/vorago-rs/blob/main/va416xx/examples/simple/examples/dac-adc.rs)
//! - [ADC](https://github.com/us-irs/vorago-rs/blob/main/va416xx/examples/simple/examples/adc.rs)
use core::marker::PhantomData;
use crate::clock::Clocks;

2
va416xx/va416xx-hal/src/can/mod.rs
View File

@@ -16,7 +16,7 @@
//!
//! # Example
//!
//! - [CAN example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/can.rs)
//! - [CAN example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/embassy/src/bin/can.rs)
use core::sync::atomic::AtomicBool;
use arbitrary_int::{prelude::*, u11, u15, u2, u3, u4, u7};

2
va416xx/va416xx-hal/src/clock.rs
View File

@@ -9,7 +9,7 @@
//!
//! # Examples
//!
//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs)
//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/uart.rs)
#[cfg(not(feature = "va41628"))]
use crate::adc::ADC_MAX_CLK;
use crate::pac;

2
va416xx/va416xx-hal/src/dac.rs
View File

@@ -2,7 +2,7 @@
//!
//! ## Examples
//!
//! - [ADC and DAC example](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/dac-adc.rs)
//! - [ADC and DAC example](https://github.com/us-irs/vorago-rs/blob/main/va416xx/examples/simple/examples/dac-adc.rs)
use core::ops::Deref;
use vorago_shared_hal::{

2
va416xx/va416xx-hal/src/dma.rs
View File

@@ -2,7 +2,7 @@
//!
//! ## Examples
//!
//! - [Simple DMA example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/dma.rs)
//! - [Simple DMA example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/dma.rs)
use arbitrary_int::{u10, u3};
use vorago_shared_hal::{enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect};

4
va416xx/va416xx-hal/src/gpio/mod.rs
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@@ -15,6 +15,6 @@
//!
//! # Examples
//!
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/embassy/src/bin/async-gpio.rs)
pub use vorago_shared_hal::gpio::*;

2
va416xx/va416xx-hal/src/i2c.rs
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@@ -2,5 +2,5 @@
//!
//! ## Examples
//!
//! - [PEB1 accelerometer example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs)
//! - [PEB1 accelerometer example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/peb1-accelerometer.rs)
pub use vorago_shared_hal::i2c::*;

3
va416xx/va416xx-hal/src/lib.rs
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@@ -1,6 +1,7 @@
//! This is the **H**ardware **A**bstraction **L**ayer (HAL) for the VA416xx MCU family.
//!
//! It is an additional hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx).
//! It is an additional hardware abstraction on top of the
//! [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/va416xx).
//!
//! It is the result of reading the datasheet for the device and encoding a type-safe layer over the
//! raw PAC. This crate also implements traits specified by the

2
va416xx/va416xx-hal/src/nvm.rs
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@@ -4,7 +4,7 @@
//!
//! # Examples
//!
//! - [Flashloader application](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader)
//! - [Flashloader application](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/flashloader)
use embedded_hal::spi::MODE_0;
use vorago_shared_hal::{
disable_peripheral_clock, enable_peripheral_clock, reset_peripheral_for_cycles,

2
va416xx/va416xx-hal/src/pwm.rs
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@@ -4,5 +4,5 @@
//!
//! ## Examples
//!
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/pwm.rs)
pub use vorago_shared_hal::pwm::*;

2
va416xx/va416xx-hal/src/spi.rs
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@@ -6,6 +6,6 @@
//!
//! ## Examples
//!
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/spi.rs)
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/spi.rs)
//! - [NVM library][crate::nvm]
pub use vorago_shared_hal::spi::*;

4
va416xx/va416xx-hal/src/timer.rs
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@@ -2,8 +2,8 @@
//!
//! ## Examples
//!
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/cascade.rs)
pub use vorago_shared_hal::timer::*;
pub const TIM_IRQ_OFFSET: usize = 48;

10
va416xx/va416xx-hal/src/uart/mod.rs
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@@ -9,9 +9,9 @@
//!
//! ## Examples
//!
//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs)
//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/uart.rs)
//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/rtic/src/bin/uart-echo-rtic.rs)
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/embassy/src/bin/async-uart-tx.rs)
pub use vorago_shared_hal::uart::*;

2
va416xx/va416xx-hal/src/wdt.rs
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@@ -2,7 +2,7 @@
//!
//! ## Examples
//!
//! - [Watchdog simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/wdt.rs)
//! - [Watchdog simple example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/wdt.rs)
use vorago_shared_hal::{enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect};
use crate::time::Hertz;

4
va416xx/va416xx/Cargo.toml
View File

@@ -4,8 +4,8 @@ version = "0.5.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "PAC for the Vorago VA416xx family of MCUs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "arm", "cortex-m", "vorago", "va416xx"]
categories = ["embedded", "no-std", "hardware-support"]

4
va416xx/vorago-peb1/Cargo.toml
View File

@@ -4,8 +4,8 @@ version = "0.1.3"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "Board Support Crate for the Vorago PEB1 development board"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
keywords = ["no-std", "peb1", "cortex-m", "vorago", "va416xx"]
categories = ["embedded", "no-std", "hardware-support"]

2
va416xx/vorago-peb1/README.md
View File

@@ -6,7 +6,7 @@
This is the Rust **B**oard **S**upport **P**ackage crate for the Vorago PEB1 development board.
Its aim is to provide drivers for the board features of the PEB1 board.
The BSP builds on top of the [HAL crate for VA416xx devices](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal).
The BSP builds on top of the [HAL crate for VA416xx devices](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/va416xx-hal).
## Notes on board revisions

2
va416xx/vorago-peb1/src/lib.rs
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@@ -8,7 +8,7 @@ pub use lis2dh12;
///
/// # Example
///
/// - [PEB1 Accelerometer](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs)
/// - [PEB1 Accelerometer](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/examples/simple/examples/peb1-accelerometer.rs)
pub mod accelerometer {
use lis2dh12::{self, detect_i2c_addr, AddrDetectionError, Lis2dh12};

12
vorago-shared-hal/Cargo.toml
View File

@@ -3,8 +3,8 @@ name = "vorago-shared-hal"
version = "0.2.0"
description = "Peripheral HAL components shared between Vorago families"
edition = "2024"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs"
homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
license = "Apache-2.0"
[dependencies]
@@ -20,15 +20,15 @@ critical-section = "1"
embedded-hal = "1.0"
embedded-hal-async = "1"
embedded-hal-nb = "1"
embedded-io = "0.6"
embedded-io-async = "0.6"
embedded-io = "0.7"
embedded-io-async = "0.7"
raw-slicee = "0.1"
thiserror = { version = "2", default-features = false }
paste = "1"
fugit = "0.3"
defmt = { version = "1", optional = true }
va108xx = { version = "0.6", default-features = false, optional = true }
va416xx = { version = ">=0.4, <=0.5", default-features = false, optional = true }
va108xx = { version = "0.6", path = "../va108xx/va108xx", default-features = false, optional = true }
va416xx = { version = "0.5", path = "../va416xx/va416xx", default-features = false, optional = true }
embassy-sync = "0.7"
embassy-time-driver = "0.2"
embassy-time-queue-utils = "0.3"

4
vorago-shared-hal/README.md
View File

@@ -6,8 +6,8 @@ Vorago Shared Peripherals
Peripheral drivers shared between Vorago families.
This library should not used directly. Instead, use the re-exported modules of the repective
[VA108xx HAL](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal) and
[VA416xx HAL](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs).
[VA108xx HAL](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/va108xx-hal) and
[VA416xx HAL](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va416xx/va416xx-hal).
## Check / Build for VA1XXX family

6
vorago-shared-hal/src/spi/mod.rs
View File

@@ -414,14 +414,14 @@ pub fn spi_clk_config_from_div(mut div: u16) -> Result<SpiClockConfig, SpiClockC
if div == 0 {
return Err(SpiClockConfigError::DivIsZero);
}
if div % 2 != 0 {
if !div.is_multiple_of(2) {
return Err(SpiClockConfigError::DivideValueNotEven);
}
let mut prescale_val = 0;
// find largest (even) prescale value that divides into div
for i in (2..=0xfe).rev().step_by(2) {
if div % i == 0 {
if div.is_multiple_of(i) {
prescale_val = i;
break;
}
@@ -458,7 +458,7 @@ pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option<u16> {
raw_div
};
if rounded_div % 2 != 0 {
if !rounded_div.is_multiple_of(2) {
// Take slower clock conservatively.
rounded_div += 1;
}

6
vorago-shared-hal/src/uart/mod.rs
View File

@@ -9,9 +9,9 @@
//!
//! ## Examples
//!
//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs)
//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/uart.rs)
//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs)
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/flashloader)
use core::convert::Infallible;
pub mod regs;
#[cfg(feature = "vor1x")]

11
vorago-shared-hal/src/uart/tx_asynch.rs
View File

@@ -163,9 +163,10 @@ impl Future for TxFuture {
impl Drop for TxFuture {
fn drop(&mut self) {
let mut reg_block = unsafe { self.id.steal_regs() };
disable_tx_interrupts(&mut reg_block);
disable_tx(&mut reg_block);
if !TX_DONE[self.id as usize].load(core::sync::atomic::Ordering::Relaxed) {
disable_tx_interrupts(&mut reg_block);
disable_tx(&mut reg_block);
}
}
}
@@ -205,4 +206,8 @@ impl Write for TxAsync {
let fut = unsafe { TxFuture::new(&mut self.0, buf) };
fut.await
}
async fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
}