URLs and other improvements

vorago-shared-hal/src/spi/mod.rs

@@ -414,14 +414,14 @@ pub fn spi_clk_config_from_div(mut div: u16) -> Result<SpiClockConfig, SpiClockC
     if div == 0 {
         return Err(SpiClockConfigError::DivIsZero);
     }
-    if div % 2 != 0 {
+    if !div.is_multiple_of(2) {
         return Err(SpiClockConfigError::DivideValueNotEven);
     }
     let mut prescale_val = 0;
 
     // find largest (even) prescale value that divides into div
     for i in (2..=0xfe).rev().step_by(2) {
-        if div % i == 0 {
+        if div.is_multiple_of(i) {
             prescale_val = i;
             break;
         }
@@ -458,7 +458,7 @@ pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option<u16> {
         raw_div
     };
 
-    if rounded_div % 2 != 0 {
+    if !rounded_div.is_multiple_of(2) {
         // Take slower clock conservatively.
         rounded_div += 1;
     }

vorago-shared-hal/src/uart/mod.rs

@@ -9,9 +9,9 @@
 //!
 //! ## Examples
 //!
-//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs)
-//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
-//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
+//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/simple/examples/uart.rs)
+//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs)
+//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/vorago-rs/src/branch/main/va108xx/flashloader)
 use core::convert::Infallible;
 pub mod regs;
 #[cfg(feature = "vor1x")]

vorago-shared-hal/src/uart/tx_asynch.rs

@@ -163,9 +163,10 @@ impl Future for TxFuture {
 impl Drop for TxFuture {
     fn drop(&mut self) {
         let mut reg_block = unsafe { self.id.steal_regs() };
-
-        disable_tx_interrupts(&mut reg_block);
-        disable_tx(&mut reg_block);
+        if !TX_DONE[self.id as usize].load(core::sync::atomic::Ordering::Relaxed) {
+            disable_tx_interrupts(&mut reg_block);
+            disable_tx(&mut reg_block);
+        }
     }
 }
 
@@ -205,4 +206,8 @@ impl Write for TxAsync {
         let fut = unsafe { TxFuture::new(&mut self.0, buf) };
         fut.await
     }
+
+    async fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
 }