vorago-shared-hal/CHANGELOG.md

@@ -26,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Fixed
 
+- `Pull::Up` and `Pull::High` were inverted.
 - Removed HW CS pin provider implementation for PA23, PA22 and PA21, which are multi HW CS pins.
 - Added missing `AnyPin` trait impl for Multi HW CS pins.
 - Expose inner `Input` pin for `InputPinAsync`.

vorago-shared-hal/src/ioconfig/regs.rs

@@ -39,8 +39,8 @@ pub enum FilterClockSelect {
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Pull {
-    Up = 0,
-    Down = 1,
+    Down = 0,
+    Up = 1,
 }
 
 #[derive(Debug, Eq, PartialEq)]