rust/vorago-shared-hal
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This commit is contained in:
Robin Mueller
2025-09-02 23:37:57 +02:00
parent 6aac1e41c5
commit b61feb62a7
5 changed files with 10 additions and 10 deletions
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4
Cargo.toml
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@@ -27,8 +27,8 @@ thiserror = { version = "2", default-features = false }
paste = "1" paste = "1"
fugit = "0.3" fugit = "0.3"
defmt = { version = "1", optional = true } defmt = { version = "1", optional = true }
va108xx = { version = "0.5", default-features = false, optional = true } va108xx = { version = "0.6", default-features = false, optional = true }
va416xx = { version = "0.4", default-features = false, optional = true } va416xx = { version = ">=0.4, <=0.5", default-features = false, optional = true }
embassy-sync = "0.7" embassy-sync = "0.7"
embassy-time-driver = "0.2" embassy-time-driver = "0.2"
embassy-time-queue-utils = "0.3" embassy-time-queue-utils = "0.3"

4
src/embassy.rs
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@@ -86,7 +86,7 @@ impl TimerDriver {
let irqsel = unsafe { va108xx::Irqsel::steal() }; let irqsel = unsafe { va108xx::Irqsel::steal() };
// Switch on. Timekeeping should always be done. // Switch on. Timekeeping should always be done.
irqsel irqsel
.tim0(TimekeeperTim::ID.value() as usize) .tim(TimekeeperTim::ID.value() as usize)
.write(|w| unsafe { w.bits(timekeeper_irq as u32) }); .write(|w| unsafe { w.bits(timekeeper_irq as u32) });
unsafe { unsafe {
enable_nvic_interrupt(timekeeper_irq); enable_nvic_interrupt(timekeeper_irq);
@@ -111,7 +111,7 @@ impl TimerDriver {
enable_nvic_interrupt(alarm_irq); enable_nvic_interrupt(alarm_irq);
} }
irqsel irqsel
.tim0(AlarmTim::ID.value() as usize) .tim(AlarmTim::ID.value() as usize)
.write(|w| unsafe { w.bits(alarm_irq as u32) }); .write(|w| unsafe { w.bits(alarm_irq as u32) });
} }

8
src/gpio/ll.rs
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@@ -546,12 +546,12 @@ impl LowLevelGpio {
// Set the correct interrupt number in the IRQSEL register // Set the correct interrupt number in the IRQSEL register
super::Port::A => { super::Port::A => {
irqsel irqsel
.porta0(self.id().offset()) .porta(self.id().offset())
.write(|w| unsafe { w.bits(id as u32) }); .write(|w| unsafe { w.bits(id as u32) });
} }
super::Port::B => { super::Port::B => {
irqsel irqsel
.portb0(self.id().offset()) .portb(self.id().offset())
.write(|w| unsafe { w.bits(id as u32) }); .write(|w| unsafe { w.bits(id as u32) });
} }
} }
@@ -566,12 +566,12 @@ impl LowLevelGpio {
// Set the correct interrupt number in the IRQSEL register // Set the correct interrupt number in the IRQSEL register
super::Port::A => { super::Port::A => {
irqsel irqsel
.porta0(self.id().offset()) .porta(self.id().offset())
.write(|w| unsafe { w.bits(u32::MAX) }); .write(|w| unsafe { w.bits(u32::MAX) });
} }
super::Port::B => { super::Port::B => {
irqsel irqsel
.portb0(self.id().offset()) .portb(self.id().offset())
.write(|w| unsafe { w.bits(u32::MAX) }); .write(|w| unsafe { w.bits(u32::MAX) });
} }
} }

2
src/timer/mod.rs
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@@ -261,7 +261,7 @@ impl CountdownTimer {
let irqsel = unsafe { pac::Irqsel::steal() }; let irqsel = unsafe { pac::Irqsel::steal() };
enable_peripheral_clock(PeripheralSelect::Irqsel); enable_peripheral_clock(PeripheralSelect::Irqsel);
irqsel irqsel
.tim0(self.id.value() as usize) .tim(self.id.value() as usize)
.write(|w| unsafe { w.bits(irq_cfg.id as u32) }); .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
} }
if irq_cfg.enable_in_nvic { if irq_cfg.enable_in_nvic {

2
src/uart/mod.rs
View File

@@ -529,7 +529,7 @@ impl Uart {
if irq_cfg.route { if irq_cfg.route {
enable_peripheral_clock(PeripheralSelect::Irqsel); enable_peripheral_clock(PeripheralSelect::Irqsel);
unsafe { va108xx::Irqsel::steal() } unsafe { va108xx::Irqsel::steal() }
.uart0(UartI::ID as usize) .uart(UartI::ID as usize)
.write(|w| unsafe { w.bits(irq_cfg.id as u32) }); .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
} }
if irq_cfg.enable_in_nvic { if irq_cfg.enable_in_nvic {