Introduce Rust FSBL

This PR introduces some major features while also changing the project structure to be more flexible
for multiple platforms (e.g. host tooling).

Added features:

1. Pure Rust FSBL for the Zedboard. This first variant is simplistic. It
   is currently only capable of QSPI boot. It searches for a bitstream
   and ELF file inside the boot binary, flashes them and jumps to them.
2. DDR, QSPI, private CPU timer modules
3. Tooling to auto-generate board specific DDR and DDRIOB config
   parameters from the vendor provided ps7init.tcl file

Changed project structure:

1. All target specific project are inside a dedicated workspace inside
   the `zynq` folder now.
2. All tool intended to be run on a host are inside a `tools` workspace
3. All other common projects are at the project root

zedboard-fpga-design/README.md

@@ -38,3 +38,25 @@ vivado zedboard-rust.xpr
 
 You can perform all the steps specified in the Vivado GUI as well using `Execute TCL script` and
 `Load Project`.
+
+# Generating the SDT folder from a hardware description
+
+You can generate a hardware description by building the block design by using `Generate Bitstream`
+inside the Vivado GUI and then exporting the hardware description via
+`File -> Export -> Export Hardware`. This allows to generate a `*.xsa` file which describes the
+hardware.
+
+After that, you can generate the SDT output folder which contains various useful files like
+the `ps7_init.tcl` script. The provided ` sdtgen.tcl` and `stdgen.py` script simplify this process.
+
+For example, the following command generates the SDT output folder inside a folder
+named `sdt_out` for a hardware description files `zedboard-rust/zedboard-rust.xsa`,
+assuming that the Vitis tool suite is installed at `/tools/Xilinx/Vitis/2024.1`:
+
+```sh
+export AMD_TOOLS="/tools/Xilinx/Vitis/2024.1"
+./sdtgen.py -x ./zedboard-rust/zedboard-rust.xsa
+```
+
+Run `stdgen.py -h` for more information and configuration options. The `stdgen.py` is a helper
+script which will invoke `sdtgen.tcl` to generate the SDT.

zedboard-fpga-design/src/zedboard-bd.tcl

@@ -675,6 +675,18 @@ proc create_root_design { parentCell } {
   connect_bd_net -net xlslice_0_Dout1 [get_bd_pins UART_MUX/Dout] [get_bd_pins uart_mux_0/sel]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins EMIO_O_0/Dout] [get_bd_pins LEDS/Din] [get_bd_pins EMIO_I/In0] [get_bd_pins UART_MUX/Din]
 
+  # Set DDR properties specified in the datasheet.
+  set_property -dict [list \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.410} \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} \
+  ] [get_bd_cells processing_system7_0]
+
   # Create address segments
   assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
   assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] -force