continue with FSBL

zynq7000/src/ddrc.rs

@@ -1,4 +1,4 @@
-use arbitrary_int::{u11, u12, u3, u4, u5, u6, u7};
+use arbitrary_int::{u2, u3, u4, u5, u6, u7, u11, u12};
 
 pub const DDRC_BASE_ADDR: usize = 0xF800_6000;
 
@@ -39,6 +39,9 @@ pub struct DdrcControl {
 pub struct TwoRankConfig {
     #[bits(14..=18, rw)]
     addrmap_cs_bit0: u5,
+    /// Reserved register, but for some reason, Xilinx tooling writes a 1 here?
+    #[bits(12..=13, rw)]
+    ddrc_active_ranks: u2,
     /// tREFI - Average time between refreshes, in multiples of 32 clocks.
     #[bits(0..=11, rw)]
     rfc_nom_x32: u12,
@@ -137,9 +140,38 @@ pub struct DramParamReg3 {
     #[bits(5..=7, rw)]
     t_rrd: u3,
     #[bits(2..=4, rw)]
-    t_ccd: u3
+    t_ccd: u3,
 }
 
+#[bitbybit::bitfield(u32, default = 0x0)]
+pub struct DramParamReg4 {
+    #[bit(27, rw)]
+    mr_rdata_valid: bool,
+    #[bit(26, rw)]
+    mr_type: bool,
+    #[bit(25, rw)]
+    mr_wr_busy: bool,
+    #[bits(9..=24, rw)]
+    mr_data: u16,
+    #[bits(7..=8, rw)]
+    mr_addr: u2,
+    #[bit(6, rw)]
+    mr_wr: bool,
+    #[bit(1, rw)]
+    prefer_write: bool,
+    #[bit(0, rw)]
+    enable_2t_timing_mode: bool,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+pub struct DramInitParam {
+    #[bits(11..=13, rw)]
+    t_mrd: u3,
+    #[bits(7..=10, rw)]
+    pre_ocd_x32: u4,
+    #[bits(0..=6, rw)]
+    final_wait_x32: u7,
+}
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DdrController {
@@ -149,13 +181,13 @@ pub struct DdrController {
     lpr_queue_ctrl: LprHprQueueControl,
     wr_reg: WriteQueueControl,
     dram_param_reg0: DramParamReg0,
-    dram_param_reg1: u32,
-    dram_param_reg2: u32,
-    dram_param_reg3: u32,
-    dram_param_reg4: u32,
-    dram_init_param: u32,
-    dram_emr_reg: u32,
-    dram_emr_mr_reg: u32,
+    dram_param_reg1: DramParamReg1,
+    dram_param_reg2: DramParamReg2,
+    dram_param_reg3: DramParamReg3,
+    dram_param_reg4: DramParamReg4,
+    dram_init_param: DramInitParam,
+    dram_emr: u32,
+    dram_emr_mr: u32,
     dram_burst8_rdwr: u32,
     dram_disable_dq: u32,
     dram_addr_map_bank: u32,
@@ -164,7 +196,8 @@ pub struct DdrController {
     dram_odt_reg: u32,
     phy_debug_reg: u32,
     phy_cmd_timeout_rddata_cpt: u32,
-    mode_status_reg: u32,
+    #[mmio(PureRead)]
+    mode_status: u32,
     dll_calib: u32,
     odt_delay_hold: u32,
     ctrl_reg1: u32,
@@ -186,16 +219,28 @@ pub struct DdrController {
     dfi_timing: u32,
     _reserved2: [u32; 0x2],
     che_corr_control: u32,
+    #[mmio(PureRead)]
     che_corr_ecc_log: u32,
+    #[mmio(PureRead)]
     che_corr_ecc_addr: u32,
+    #[mmio(PureRead)]
     che_corr_ecc_data_31_0: u32,
+    #[mmio(PureRead)]
     che_corr_ecc_data_63_32: u32,
+    #[mmio(PureRead)]
     che_corr_ecc_data_71_64: u32,
+    /// Clear on write, but the write is performed on another register.
+    #[mmio(PureRead)]
     che_uncorr_ecc_log: u32,
+    #[mmio(PureRead)]
     che_uncorr_ecc_addr: u32,
+    #[mmio(PureRead)]
     che_uncorr_ecc_data_31_0: u32,
+    #[mmio(PureRead)]
     che_uncorr_ecc_data_63_32: u32,
+    #[mmio(PureRead)]
     che_uncorr_ecc_data_71_64: u32,
+    #[mmio(PureRead)]
     che_ecc_stats: u32,
     ecc_scrub: u32,
     che_ecc_corr_bit_mask_31_0: u32,
@@ -221,44 +266,47 @@ pub struct DdrController {
     reg_64: u32,
     reg_65: u32,
     _reserved10: [u32; 3],
+    #[mmio(PureRead)]
     reg69_6a0: u32,
+    #[mmio(PureRead)]
     reg69_6a1: u32,
     _reserved11: u32,
+    #[mmio(PureRead)]
     reg69_6d2: u32,
+    #[mmio(PureRead)]
     reg69_6d3: u32,
+    #[mmio(PureRead)]
     reg69_710: u32,
+    #[mmio(PureRead)]
     reg6e_711: u32,
+    #[mmio(PureRead)]
     reg6e_712: u32,
+    #[mmio(PureRead)]
     reg6e_713: u32,
     _reserved12: u32,
-    phy_dll_status_0: u32,
-    phy_dll_status_1: u32,
-    phy_dll_status_2: u32,
-    phy_dll_status_3: u32,
+    #[mmio(PureRead)]
+    phy_dll_status: [u32; 4],
     _reserved13: u32,
+    #[mmio(PureRead)]
     dll_lock_status: u32,
+    #[mmio(PureRead)]
     phy_control_status: u32,
+    #[mmio(PureRead)]
     phy_control_status_2: u32,
 
     _reserved14: [u32; 0x5],
 
+    // DDRI registers.
+    #[mmio(PureRead)]
     axi_id: u32,
     page_mask: u32,
-    axi_priority_wr_port_0: u32,
-    axi_priority_wr_port_1: u32,
-    axi_priority_wr_port_2: u32,
-    axi_priority_wr_port_3: u32,
-    axi_priority_rd_port_0: u32,
-    axi_priority_rd_port_1: u32,
-    axi_priority_rd_port_2: u32,
-    axi_priority_rd_port_3: u32,
+    axi_priority_wr_port: [u32; 4],
+    axi_priority_rd_port: [u32; 4],
 
     _reserved15: [u32; 0x1B],
 
-    excl_access_cfg_0: u32,
-    excl_access_cfg_1: u32,
-    excl_access_cfg_2: u32,
-    excl_access_cfg_3: u32,
+    excl_access_cfg: [u32; 4],
+    #[mmio(PureRead)]
     mode_reg_read: u32,
     lpddr_ctrl_0: u32,
     lpddr_ctrl_1: u32,

zynq7000/src/lib.rs

@@ -17,6 +17,7 @@ extern crate std;
 
 pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000;
 
+pub mod ddrc;
 pub mod eth;
 pub mod gic;
 pub mod gpio;
@@ -28,7 +29,6 @@ pub mod slcr;
 pub mod spi;
 pub mod ttc;
 pub mod uart;
-pub mod ddrc;
 
 static PERIPHERALS_TAKEN: AtomicBool = AtomicBool::new(false);
 

zynq7000/src/slcr/clocks.rs

@@ -169,7 +169,7 @@ pub struct DdrClkCtrl {
     ddr_3x_clk_act: bool,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x0)]
 pub struct DciClkCtrl {
     /// Second cascade divider. Reset value: 0x1E
     #[bits(20..=25, rw)]