first tested QSPI code

examples/zedboard/Cargo.toml

@@ -16,6 +16,7 @@ zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
 zynq7000-embassy = { path = "../../zynq7000-embassy" }
+zedboard-bsp = { path = "../../zedboard-bsp" }
 num_enum = { version = "0.7", default-features = false }
 l3gd20 = { git = "https://github.com/us-irs/l3gd20.git", branch = "add-async-if" }
 embedded-io = "0.6"

examples/zedboard/src/bin/ethernet.rs

@@ -33,10 +33,8 @@ use embedded_io::Write;
 use embedded_io_async::Write as _;
 use log::{LevelFilter, debug, error, info, warn};
 use rand::{RngCore, SeedableRng};
-use zedboard::{
-    PS_CLOCK_FREQUENCY,
-    phy_marvell::{LatchingLinkStatus, MARVELL_88E1518_OUI},
-};
+use zedboard::PS_CLOCK_FREQUENCY;
+use zedboard_bsp::phy_marvell;
 use zynq7000_hal::{
     BootMode,
     clocks::Clocks,
@@ -72,8 +70,8 @@ const INIT_STRING: &str = "-- Zynq 7000 Zedboard Ethernet Example --\n\r";
 // Unicast address with OUI of the Marvell 88E1518 PHY.
 const MAC_ADDRESS: [u8; 6] = [
     0x00,
-    ((MARVELL_88E1518_OUI >> 8) & 0xff) as u8,
-    (MARVELL_88E1518_OUI & 0xff) as u8,
+    ((phy_marvell::MARVELL_88E1518_OUI >> 8) & 0xff) as u8,
+    (phy_marvell::MARVELL_88E1518_OUI & 0xff) as u8,
     0x00,
     0x00,
     0x01,
@@ -317,9 +315,8 @@ async fn main(spawner: Spawner) -> ! {
     eth.set_rx_buf_descriptor_base_address(rx_descr_ref.base_addr());
     eth.set_tx_buf_descriptor_base_address(tx_descr_ref.base_addr());
     eth.start();
-    let (mut phy, phy_rev) =
-        zedboard::phy_marvell::Marvell88E1518Phy::new_autoprobe_addr(eth.mdio_mut())
-            .expect("could not auto-detect phy");
+    let (mut phy, phy_rev) = phy_marvell::Marvell88E1518Phy::new_autoprobe_addr(eth.mdio_mut())
+        .expect("could not auto-detect phy");
     info!(
         "Detected Marvell 88E1518 PHY with revision number: {:?}",
         phy_rev
@@ -456,7 +453,8 @@ async fn main(spawner: Spawner) -> ! {
             IpMode::StackReady => {
                 let status = phy.read_copper_status();
                 // Periodically check for link changes.
-                if status.copper_link_status() == LatchingLinkStatus::DownSinceLastRead {
+                if status.copper_link_status() == phy_marvell::LatchingLinkStatus::DownSinceLastRead
+                {
                     warn!("ethernet link is down.");
                     ip_mode = IpMode::LinkDown;
                     continue;

examples/zedboard/src/bin/qspi.rs

@@ -0,0 +1,189 @@
+#![no_std]
+#![no_main]
+
+use core::panic::PanicInfo;
+use cortex_ar::asm::nop;
+use embassy_executor::Spawner;
+use embassy_time::{Duration, Ticker};
+use embedded_hal::digital::StatefulOutputPin;
+use embedded_io::Write;
+use log::{error, info};
+use zedboard::PS_CLOCK_FREQUENCY;
+use zedboard_bsp::qspi_spansion;
+use zynq7000_hal::{
+    BootMode,
+    clocks::Clocks,
+    configure_level_shifter,
+    gic::{GicConfigurator, GicInterruptHelper, Interrupt},
+    gpio::{GpioPins, Output, PinState},
+    gtc::GlobalTimerCounter,
+    l2_cache,
+    prelude::*,
+    qspi,
+    uart::{ClockConfigRaw, Uart, UartConfig},
+};
+
+use zynq7000::{
+    PsPeripherals,
+    slcr::{LevelShifterConfig, clocks::SrcSelIo},
+};
+use zynq7000_rt as _;
+
+const INIT_STRING: &str = "-- Zynq 7000 Zedboard QSPI example --\n\r";
+
+/// Entry point (not called like a normal main function)
+#[unsafe(no_mangle)]
+pub extern "C" fn boot_core(cpu_id: u32) -> ! {
+    if cpu_id != 0 {
+        panic!("unexpected CPU ID {}", cpu_id);
+    }
+    main();
+}
+
+#[embassy_executor::main]
+#[unsafe(export_name = "main")]
+async fn main(_spawner: Spawner) -> ! {
+    let mut dp = PsPeripherals::take().unwrap();
+    l2_cache::init_with_defaults(&mut dp.l2c);
+
+    // Enable PS-PL level shifters.
+    configure_level_shifter(LevelShifterConfig::EnableAll);
+
+    // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
+    let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
+    // Set up the global interrupt controller.
+    let mut gic = GicConfigurator::new_with_init(dp.gicc, dp.gicd);
+    gic.enable_all_interrupts();
+    gic.set_all_spi_interrupt_targets_cpu0();
+    gic.enable();
+    unsafe {
+        gic.enable_interrupts();
+    }
+    let gpio_pins = GpioPins::new(dp.gpio);
+
+    // Set up global timer counter and embassy time driver.
+    let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks());
+    zynq7000_embassy::init(clocks.arm_clocks(), gtc);
+
+    // Set up the UART, we are logging with it.
+    let uart_clk_config = ClockConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200)
+        .unwrap()
+        .0;
+    let mut uart = Uart::new_with_mio(
+        dp.uart_1,
+        UartConfig::new_with_clk_config(uart_clk_config),
+        (gpio_pins.mio.mio48, gpio_pins.mio.mio49),
+    )
+    .unwrap();
+    uart.write_all(INIT_STRING.as_bytes()).unwrap();
+    // Safety: We are not multi-threaded yet.
+    unsafe {
+        zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
+            uart,
+            log::LevelFilter::Trace,
+            false,
+        )
+    };
+
+    let boot_mode = BootMode::new_from_regs();
+    info!("Boot mode: {:?}", boot_mode);
+
+    let qspi_clock_config =
+        qspi::ClockConfig::calculate_with_loopback(SrcSelIo::IoPll, &clocks, 100.MHz())
+            .expect("QSPI clock calculation failed");
+    let qspi = qspi::Qspi::new_single_qspi_with_feedback(
+        dp.qspi,
+        qspi_clock_config,
+        embedded_hal::spi::MODE_0,
+        gpio_pins.mio.mio1,
+        (
+            gpio_pins.mio.mio2,
+            gpio_pins.mio.mio3,
+            gpio_pins.mio.mio4,
+            gpio_pins.mio.mio5,
+        ),
+        gpio_pins.mio.mio6,
+        gpio_pins.mio.mio8,
+    );
+
+    let qspi_io_mode = qspi.into_io_mode(false);
+
+    let mut spansion_qspi = qspi_spansion::QspiSpansionS25Fl256S::new(qspi_io_mode);
+
+    let rdid = spansion_qspi.read_rdid_extended();
+    info!(
+        "QSPI Info: manufacturer ID: {:?}, interface type: {:?}, density: {:?}, sector arch: {:?}, model number: {:?}",
+        rdid.base_id().manufacturer_id(),
+        rdid.base_id().memory_interface_type(),
+        rdid.base_id().density(),
+        rdid.sector_arch(),
+        rdid.model_number()
+    );
+
+    let mut rdsr1 = spansion_qspi.read_status_register_1();
+    info!("QSPI Status Register 1: {}", rdsr1.raw_value());
+
+    spansion_qspi.write_enable();
+
+    rdsr1 = spansion_qspi.read_status_register_1();
+    info!("QSPI Status Register 1: {}", rdsr1.raw_value());
+
+    spansion_qspi.write_disable();
+
+    let mut ticker = Ticker::every(Duration::from_millis(200));
+
+    let mut mio_led = Output::new_for_mio(gpio_pins.mio.mio7, PinState::Low);
+    loop {
+        mio_led.toggle().unwrap();
+
+        ticker.next().await; // Wait for the next cycle of the ticker
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _irq_handler() {
+    let mut gic_helper = GicInterruptHelper::new();
+    let irq_info = gic_helper.acknowledge_interrupt();
+    match irq_info.interrupt() {
+        Interrupt::Sgi(_) => (),
+        Interrupt::Ppi(ppi_interrupt) => {
+            if ppi_interrupt == zynq7000_hal::gic::PpiInterrupt::GlobalTimer {
+                unsafe {
+                    zynq7000_embassy::on_interrupt();
+                }
+            }
+        }
+        Interrupt::Spi(_spi_interrupt) => (),
+        Interrupt::Invalid(_) => (),
+        Interrupt::Spurious => (),
+    }
+    gic_helper.end_of_interrupt(irq_info);
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _abort_handler() {
+    loop {
+        nop();
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _undefined_handler() {
+    loop {
+        nop();
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _prefetch_handler() {
+    loop {
+        nop();
+    }
+}
+
+/// Panic handler
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    error!("Panic: {info:?}");
+    loop {}
+}

examples/zedboard/src/lib.rs

@@ -1,7 +1,5 @@
 #![no_std]
 use zynq7000_hal::time::Hertz;
-pub mod phy_marvell;
-pub mod qspi_spansion;
 
 // Define the clock frequency as a constant
 pub const PS_CLOCK_FREQUENCY: Hertz = Hertz::from_raw(33_333_333);

examples/zedboard/src/phy_marvell.rs

@@ -1,246 +0,0 @@
-use arbitrary_int::{u2, u4, u5};
-
-#[derive(Clone, Debug)]
-pub struct PhyIdentifier {
-    pub oui: u32,
-    pub model: u8,
-    pub rev: u8,
-}
-
-// Organizational Unique Identifier for Marvell 88E1518 PHY
-pub const MARVELL_88E1518_OUI: u32 = 0x005043;
-pub const MARVELL_88E1518_MODELL_NUMBER: u8 = 0b011101;
-
-#[bitbybit::bitenum(u5, exhaustive = false)]
-pub enum MarvellRegistersPage0 {
-    CopperControl = 0,
-    CopperStatus = 1,
-    IdReg1 = 2,
-    IdReg2 = 3,
-    CopperSpecificStatus = 17,
-    PageSel = 22,
-}
-
-#[bitbybit::bitfield(u16)]
-pub struct CopperControlRegister {
-    #[bit(15, rw)]
-    copper_reset: bool,
-    #[bit(14, rw)]
-    loopback: bool,
-    #[bit(12, rw)]
-    auto_negotiation_enable: bool,
-    #[bit(11, rw)]
-    power_down: bool,
-    #[bit(10, rw)]
-    isolate: bool,
-    #[bit(9, rw)]
-    restart_auto_negotiation: bool,
-    /// 1: Full-duplex, 0: Half-duplex
-    #[bit(8, rw)]
-    copper_duplex_mode: bool,
-    #[bits([13, 6], rw)]
-    speed_selection: u2,
-}
-
-#[bitbybit::bitenum(u1, exhaustive = true)]
-#[derive(Debug, PartialEq, Eq)]
-pub enum LatchingLinkStatus {
-    Up = 1,
-    DownSinceLastRead = 0,
-}
-
-#[bitbybit::bitfield(u16)]
-pub struct CopperStatusRegister {
-    /// Always 0, the 100BASE-T4 protocol is not available on Marvell 88E15XX.
-    #[bit(15, r)]
-    p_100_base_t4: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(14, r)]
-    p_100_base_x_full_duplex: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(13, r)]
-    p_100_base_x_half_duplex: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(12, r)]
-    p_10_base_t_full_duplex: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(11, r)]
-    p_10_base_t_half_duplex: bool,
-    /// Always 0 for Marvell 88E15XX
-    #[bit(10, r)]
-    p_100_base_t2_full_duplex: bool,
-    /// Always 0 for Marvell 88E15XX
-    #[bit(9, r)]
-    p_100_base_t2_half_duplex: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(8, r)]
-    extended_status: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(6, r)]
-    mf_preamble_suppression: bool,
-    #[bit(5, r)]
-    auto_negotiation_complete: bool,
-    // Latching high register bit.
-    #[bit(4, r)]
-    copper_remote_fault: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(3, r)]
-    auto_negotation_ability: bool,
-    // Latching low register bit. For the current link status, this register should be read back
-    // to back, or the link real time register (17_0.10) should be read
-    #[bit(2, r)]
-    copper_link_status: LatchingLinkStatus,
-    // Latching high register bit.
-    #[bit(1, r)]
-    jabber_detect: bool,
-    /// Always 1 for Marvell 88E15XX
-    #[bit(0, r)]
-    extended_capabilities: bool,
-}
-
-#[bitbybit::bitenum(u2, exhaustive = true)]
-#[derive(Debug, PartialEq, Eq)]
-pub enum PhySpeedBits {
-    Reserved = 0b11,
-    Mbps1000 = 0b10,
-    Mbps100 = 0b01,
-    Mbps10 = 0b00,
-}
-
-impl PhySpeedBits {
-    #[inline]
-    pub fn as_zynq7000_eth_speed(&self) -> Option<zynq7000_hal::eth::Speed> {
-        match self {
-            PhySpeedBits::Reserved => None,
-            PhySpeedBits::Mbps1000 => Some(zynq7000_hal::eth::Speed::Mbps1000),
-            PhySpeedBits::Mbps100 => Some(zynq7000_hal::eth::Speed::Mbps100),
-            PhySpeedBits::Mbps10 => Some(zynq7000_hal::eth::Speed::Mbps10),
-        }
-    }
-}
-
-#[bitbybit::bitenum(u1, exhaustive = true)]
-#[derive(Debug, PartialEq, Eq)]
-pub enum PhyDuplexBit {
-    Full = 1,
-    Half = 0,
-}
-
-impl PhyDuplexBit {
-    #[inline]
-    pub fn as_zynq7000_eth_duplex(&self) -> zynq7000_hal::eth::Duplex {
-        match self {
-            PhyDuplexBit::Full => zynq7000_hal::eth::Duplex::Full,
-            PhyDuplexBit::Half => zynq7000_hal::eth::Duplex::Half,
-        }
-    }
-}
-
-#[bitbybit::bitfield(u16)]
-pub struct CopperSpecificStatusRegister {
-    #[bits(14..=15, r)]
-    speed: PhySpeedBits,
-    #[bit(13, r)]
-    duplex: PhyDuplexBit,
-    /// Latching high register bit.
-    #[bit(12, r)]
-    page_received: bool,
-    /// This is 1 when auto-negotiation is not enabled.
-    #[bit(11, r)]
-    speed_and_duplex_resolved: bool,
-    /// This is the real-time link status.
-    #[bit(10, r)]
-    copper_link: bool,
-    #[bit(9, r)]
-    transmit_pause_enabled: bool,
-    #[bit(8, r)]
-    received_pause_enabled: bool,
-    #[bit(6, r)]
-    mdi_crossover_status: bool,
-    #[bit(4, r)]
-    copper_energy_detect_status: bool,
-    #[bit(3, r)]
-    global_link_status: bool,
-    #[bit(1, r)]
-    polarity: bool,
-    #[bit(0, r)]
-    jabber: bool,
-}
-
-pub struct Marvell88E1518Phy {
-    mdio: zynq7000_hal::eth::mdio::Mdio,
-    addr: u5,
-}
-
-impl Marvell88E1518Phy {
-    pub fn new_autoprobe_addr(mdio: &mut zynq7000_hal::eth::mdio::Mdio) -> Option<(Self, u4)> {
-        for addr in 0..32 {
-            let phy_id_1 =
-                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg1.raw_value());
-            let phy_id_2 =
-                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg2.raw_value());
-            // PHY ID 1 contains bits 3 to 18 of the OUI in the goofy IEEE ordering scheme,
-            // which corresponds to bit \[21:6\] of the OUI.
-            // PHY ID 2 contains bits 19 to 24 which correspond to bits \[5:0\] of the OUI.
-            let oui = ((phy_id_1 as u32) << 6) | ((phy_id_2 >> 10) & 0b111111) as u32;
-            let model_number = ((phy_id_2 >> 4) & 0b111111) as u8;
-            let revision_number = u4::new((phy_id_2 & 0b1111) as u8);
-            if oui == MARVELL_88E1518_OUI && model_number == MARVELL_88E1518_MODELL_NUMBER {
-                return Some((
-                    Self {
-                        mdio: unsafe { mdio.clone() },
-                        addr: u5::new(addr),
-                    },
-                    revision_number,
-                ));
-            }
-        }
-        None
-    }
-
-    pub fn new(mdio: zynq7000_hal::eth::mdio::Mdio, addr: u5) -> Self {
-        Self { mdio, addr }
-    }
-
-    pub fn reset(&mut self) {
-        let mut ctrl = CopperControlRegister::new_with_raw_value(
-            self.mdio
-                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
-        );
-        ctrl.set_copper_reset(true);
-        self.mdio.write_blocking(
-            self.addr,
-            MarvellRegistersPage0::CopperControl.raw_value(),
-            ctrl.raw_value(),
-        );
-    }
-
-    pub fn restart_auto_negotiation(&mut self) {
-        let mut ctrl = CopperControlRegister::new_with_raw_value(
-            self.mdio
-                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
-        );
-        ctrl.set_auto_negotiation_enable(true);
-        ctrl.set_restart_auto_negotiation(true);
-        self.mdio.write_blocking(
-            self.addr,
-            MarvellRegistersPage0::CopperControl.raw_value(),
-            ctrl.raw_value(),
-        );
-    }
-
-    pub fn read_copper_status(&mut self) -> CopperStatusRegister {
-        let raw_value = self
-            .mdio
-            .read_blocking(self.addr, MarvellRegistersPage0::CopperStatus.raw_value());
-        CopperStatusRegister::new_with_raw_value(raw_value)
-    }
-
-    pub fn read_copper_specific_status_register_1(&mut self) -> CopperSpecificStatusRegister {
-        let raw_value = self.mdio.read_blocking(
-            self.addr,
-            MarvellRegistersPage0::CopperSpecificStatus.raw_value(),
-        );
-        CopperSpecificStatusRegister::new_with_raw_value(raw_value)
-    }
-}

examples/zedboard/src/qspi_spansion.rs

@@ -1,161 +0,0 @@
-use core::cell::RefCell;
-
-use zynq7000_hal::qspi::QspiIoMode;
-
-pub enum RegisterId {
-    /// PP
-    PageProgram = 0x02,
-    /// READ
-    Read = 0x03,
-    /// WRDI
-    WriteDisable = 0x04,
-    /// RDSR1
-    ReadStatus1 = 0x05,
-    /// RDSR2
-    ReadStatus2 = 0x07,
-    /// WREN
-    WriteEnable = 0x06,
-    /// SE
-    SectorErase = 0xD8,
-    /// RDID
-    ReadId = 0x9F,
-}
-
-pub struct QspiSpansionS25Fl256S {
-    pub qspi: RefCell<QspiIoMode>,
-}
-
-#[derive(Debug, Clone, Copy, num_enum::TryFromPrimitive)]
-#[repr(u8)]
-pub enum MemoryInterfaceType {
-    _128Mb = 0x20,
-    _256Mb = 0x02,
-}
-
-#[derive(Debug, Clone, Copy, num_enum::TryFromPrimitive)]
-#[repr(u8)]
-pub enum Density {
-    _128Mb = 0x18,
-    _256Mb = 0x19,
-}
-
-#[derive(Debug, Clone, Copy)]
-pub struct BaseDeviceId {
-    manufacturer_id: u8,
-    device_id: u16,
-}
-
-impl BaseDeviceId {
-    #[inline]
-    pub const fn new(manufacturer_id: u8, device_id: u16) -> Self {
-        BaseDeviceId {
-            manufacturer_id,
-            device_id,
-        }
-    }
-
-    #[inline]
-    pub const fn from_raw(raw: u32) -> Self {
-        let manufacturer_id = ((raw >> 16) & 0xff) as u8;
-        let device_id = (raw & 0xffff) as u16;
-        BaseDeviceId::new(manufacturer_id, device_id)
-    }
-
-    #[inline]
-    pub const fn manufacturer_id(&self) -> u8 {
-        self.manufacturer_id
-    }
-
-    #[inline]
-    pub const fn device_id_raw(&self) -> u16 {
-        self.device_id
-    }
-
-    #[inline]
-    pub fn memory_interface_type(&self) -> Result<MemoryInterfaceType, u8> {
-        MemoryInterfaceType::try_from((self.device_id & 0xff) as u8).map_err(|e| e.number as u8)
-    }
-
-    #[inline]
-    pub fn density(&self) -> Result<Density, u8> {
-        Density::try_from((self.device_id) as u8).map_err(|e| e.number as u8)
-    }
-}
-
-pub struct ExtendedDeviceId {
-    base: BaseDeviceId,
-    id_cfi_len: u8,
-    sector_arch: u8,
-    familiy_id: u8,
-    model_number: [u8; 2],
-}
-
-impl ExtendedDeviceId {
-    #[inline]
-    pub fn base_id(&self) -> BaseDeviceId {
-        self.base
-    }
-}
-
-#[bitbybit::bitfield(u8)]
-pub struct StatusRegister1 {
-    #[bit(7, rw)]
-    status_register_write_disable: bool,
-    #[bit(6, r)]
-    programming_error: bool,
-    #[bit(5, r)]
-    erase_error: bool,
-    #[bit(4, r)]
-    bp_2: bool,
-    #[bit(3, r)]
-    bp_1: bool,
-    #[bit(2, r)]
-    bp_0: bool,
-    #[bit(1, r)]
-    write_enable_latch: bool,
-    #[bit(0, r)]
-    write_in_progress: bool,
-}
-
-impl QspiSpansionS25Fl256S {
-    pub fn new(qspi: QspiIoMode) -> Self {
-        QspiSpansionS25Fl256S {
-            qspi: RefCell::new(qspi),
-        }
-    }
-
-    pub fn write_enable(&mut self) {
-        let qspi = self.qspi.get_mut();
-        qspi.clear_rx_fifo();
-        qspi.transfer_init();
-        qspi.regs().write_tx_data_01(0x06);
-        qspi.transfer_start();
-        while !qspi.read_status().rx_not_empty() {}
-        qspi.read_rx_data();
-        qspi.transfer_done();
-    }
-
-    pub fn read_rdsr1(&self) -> StatusRegister1 {
-        let mut qspi = self.qspi.borrow_mut();
-        qspi.clear_rx_fifo();
-        qspi.transfer_init();
-        qspi.regs().write_tx_data_10(0x05);
-        qspi.transfer_start();
-        while !qspi.read_status().rx_not_empty() {}
-        let reply = qspi.read_rx_data();
-        qspi.transfer_done();
-        StatusRegister1::new_with_raw_value(((reply >> 24) & 0xff) as u8)
-    }
-
-    pub fn read_rdid_base(&self) -> BaseDeviceId {
-        let mut qspi = self.qspi.borrow_mut();
-        qspi.clear_rx_fifo();
-        qspi.transfer_init();
-        qspi.regs().write_tx_data_00(0x9F);
-        qspi.transfer_start();
-        while !qspi.read_status().rx_not_empty() {}
-        let reply = qspi.read_rx_data();
-        qspi.transfer_done();
-        BaseDeviceId::from_raw(reply)
-    }
-}