phy stuff

examples/zedboard/Cargo.toml

@@ -20,6 +20,7 @@ zynq7000-hal = { path = "../../zynq7000-hal" }
 zynq7000-embassy = { path = "../../zynq7000-embassy" }
 l3gd20 = { git = "https://github.com/us-irs/l3gd20.git", branch = "add-async-if" }
 embedded-io = "0.6"
+bitbybit = "1.3"
 arbitrary-int = "1.3"
 embedded-io-async = "0.6"
 critical-section = "1"

examples/zedboard/src/bin/ethernet.rs

@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
 
+use arbitrary_int::{u2, u4, u5};
+use bitbybit::bitfield;
 use core::{mem::MaybeUninit, panic::PanicInfo};
 use cortex_ar::asm::nop;
 use embassy_executor::Spawner;
@@ -10,19 +12,21 @@ use embedded_io::Write;
 use log::{error, info};
 use zedboard::PS_CLOCK_FREQUENCY;
 use zynq7000_hal::{
-    BootMode,
     clocks::Clocks,
     configure_level_shifter,
+    eth::{EthernetConfig, EthernetLowLevel},
     gic::{GicConfigurator, GicInterruptHelper, Interrupt},
     gpio::{GpioPins, Output, PinState},
     gtc::Gtc,
     uart::{ClkConfigRaw, Uart, UartConfig},
+    BootMode,
 };
 
-use zynq7000::{PsPeripherals, slcr::LevelShifterConfig};
+use zynq7000::{eth::MdcClkDiv, slcr::LevelShifterConfig, PsPeripherals};
 use zynq7000_rt::{self as _, mmu::section_attrs::SHAREABLE_DEVICE, mmu_l1_table_mut};
 
 const INIT_STRING: &str = "-- Zynq 7000 Zedboard Ethernet Example --\n\r";
+const MAC_ADDRESS: [u8; 6] = [0x01, 0x02, 0x03, 0x04, 0x05, 0x06];
 
 #[unsafe(link_section = ".uncached")]
 static RX_DESCRIPTORS: static_cell::ConstStaticCell<
@@ -59,11 +63,117 @@ pub extern "C" fn boot_core(cpu_id: u32) -> ! {
     main();
 }
 
+#[derive(Clone, Debug)]
+pub struct PhyIdentifier {
+    pub oui: u32,
+    pub model: u8,
+    pub rev: u8,
+}
+
+// Organizational Unique Identifier for Marvell 88E1518 PHY
+const MARVELL_88E1518_OUI: u32 = 0x005043;
+const MARVELL_88E1518_MODELL_NUMBER: u8 = 0b011101;
+
+#[bitbybit::bitenum(u5, exhaustive = false)]
+pub enum MarvellRegistersPage0 {
+    CopperControl = 0x00,
+    CopperStatus = 0x01,
+    IdReg1 = 0x02,
+    IdReg2 = 0x03,
+}
+
+pub struct Marvell88E1518Phy {
+    mdio: zynq7000_hal::eth::mdio::Mdio,
+    addr: u5,
+}
+
+impl<'mdio> Marvell88E1518Phy<'mdio> {
+    pub fn new_autoprobe_addr(
+        mdio: &zynq7000_hal::eth::mdio::Mdio,
+    ) -> Option<(Self, u4)> {
+        for addr in 0..32 {
+            let phy_id_1 =
+                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg1.raw_value());
+            let phy_id_2 =
+                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg2.raw_value());
+            let oui = (((phy_id_2 as u32) >> 10) << 19) | ((phy_id_1 as u32) << 3);
+            let model_number = ((phy_id_2 >> 4) & 0b111111) as u8;
+            let revision_number = u4::new((phy_id_2 & 0b1111) as u8);
+            if oui == MARVELL_88E1518_OUI && model_number == MARVELL_88E1518_MODELL_NUMBER {
+                return Some((
+                    Self {
+                        mdio: unsafe { mdio.clone() },
+                        addr: u5::new(addr),
+                    },
+                    revision_number,
+                ));
+            }
+        }
+        None
+    }
+
+    pub fn new(mdio: zynq7000_hal::eth::mdio::Mdio, addr: u5) -> Self {
+        Self { mdio, addr }
+    }
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperControlRegister {
+    #[bit(15, rw)]
+    copper_reset: bool,
+    #[bit(14, rw)]
+    loopback: bool,
+    #[bit(12, rw)]
+    auto_negotiation_enable: bool,
+    #[bit(11, rw)]
+    power_down: bool,
+    #[bit(10, rw)]
+    isolate: bool,
+    #[bit(9, rw)]
+    restart_auto_negotiation: bool,
+    /// 1: Full-duplex, 0: Half-duplex
+    #[bit(8, rw)]
+    copper_duplex_mode: bool,
+    #[bits([13, 6], rw)]
+    speed_selection: u2,
+}
+
+impl Marvell88E1518Phy<'_> {
+    pub fn reset(&mut self) {
+        let mut ctrl = CopperControlRegister::new_with_raw_value(
+            self.mdio
+                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
+        );
+        ctrl.set_copper_reset(true);
+        self.mdio.write_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperControl.raw_value(),
+            ctrl.raw_value(),
+        );
+    }
+
+    pub fn restart_auto_negotiation(&mut self) {
+        let mut ctrl = CopperControlRegister::new_with_raw_value(
+            self.mdio
+                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
+        );
+        ctrl.set_auto_negotiation_enable(true);
+        ctrl.set_restart_auto_negotiation(true);
+        self.mdio.write_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperControl.raw_value(),
+            ctrl.raw_value(),
+        );
+    }
+}
+
 #[embassy_executor::main]
 #[unsafe(export_name = "main")]
 async fn main(_spawner: Spawner) -> ! {
     // Configure the uncached memory region using the MMU.
-    mmu_l1_table_mut().update(UNCACHED_ADDR, SHAREABLE_DEVICE);
+    mmu_l1_table_mut()
+        .update(UNCACHED_ADDR, SHAREABLE_DEVICE)
+        .expect("configuring uncached memory section failed");
 
     // Enable PS-PL level shifters.
     configure_level_shifter(LevelShifterConfig::EnableAll);
@@ -121,6 +231,57 @@ async fn main(_spawner: Spawner) -> ! {
         rx_descr_ref.set_rx_buf_address(index, rx_buf.0.as_ptr() as u32);
     }
 
+    // Unwrap okay, this is a valid peripheral.
+    let eth_ll = EthernetLowLevel::new(dp.eth_0).unwrap();
+    let (clk_config, clk_error) = zynq7000_hal::eth::ClkConfig::calculate_for_rgmii(
+        clocks.io_clocks().ref_clk(),
+        zynq7000_hal::eth::Speed::Mbps1000,
+    );
+    info!(
+        "Calculated RGMII clock configuration: {:?}, error: {}",
+        clk_config, clk_error
+    );
+    // Unwrap okay, we use a standard clock config, and the clock config should never fail.
+    let eth_cfg = EthernetConfig::new(
+        clk_config,
+        zynq7000_hal::eth::calculate_mdc_clk_div(clocks.arm_clocks()).unwrap(),
+        MAC_ADDRESS,
+    );
+    // Configures all the physical pins for ethernet operation and sets up the
+    // ethernet peripheral.
+    let mut eth = zynq7000_hal::eth::Ethernet::new_with_mio(
+        eth_ll,
+        eth_cfg,
+        gpio_pins.mio.mio16,
+        gpio_pins.mio.mio21,
+        (
+            gpio_pins.mio.mio17,
+            gpio_pins.mio.mio18,
+            gpio_pins.mio.mio19,
+            gpio_pins.mio.mio20,
+        ),
+        gpio_pins.mio.mio22,
+        gpio_pins.mio.mio27,
+        (
+            gpio_pins.mio.mio23,
+            gpio_pins.mio.mio24,
+            gpio_pins.mio.mio25,
+            gpio_pins.mio.mio26,
+        ),
+        Some((gpio_pins.mio.mio52, gpio_pins.mio.mio53)),
+    );
+    eth.set_rx_buf_descriptor_base_address(rx_descr_ref.base_addr());
+    eth.set_tx_buf_descriptor_base_address(tx_descr_ref.base_addr());
+    let (mut phy, phy_rev) = Marvell88E1518Phy::new_autoprobe_addr(eth.mdio_mut()).unwrap();
+    info!("Detected Marvell 88E1518 PHY with revision number: {:?}", phy_rev);
+    phy.reset();
+    phy.restart_auto_negotiation();
+
+    // TODO:
+    //  1. PHY configuration.
+    //  2. Interrupt handler for ethernet RX and TX. Need to pass the buffers and descriptors
+    //     to the interrupt handler.
+    //
     info!("Boot mode: {:?}", boot_mode);
 
     let mut ticker = Ticker::every(Duration::from_millis(200));