improve debug impls

2025-10-08 15:03:20 +02:00
parent a7f5c24418
commit 209fc9532e
20 changed files with 344 additions and 155 deletions
--- a/tools/Cargo.lock
+++ b/tools/Cargo.lock
@@ -2,6 +2,15 @@
 # It is not intended for manual editing.
 version = 4

+[[package]]
+name = "aho-corasick"
+version = "1.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916"
+dependencies = [
+ "memchr",
+]
+
 [[package]]
 name = "anstream"
 version = "0.6.21"
@@ -149,6 +158,34 @@ dependencies = [
 "thiserror",
 ]

+[[package]]
+name = "critical-section"
+version = "1.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b"
+
+[[package]]
+name = "derive-mmio"
+version = "0.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "005a6dabf68a87a460d3cb9b8e2fd5de3f474fc34e8d9451f5a1b6db518da143"
+dependencies = [
+ "derive-mmio-macro",
+ "rustversion",
+]
+
+[[package]]
+name = "derive-mmio-macro"
+version = "0.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "584dc8e12e4aeb88000c2be8ef7db15657c817fba3e77999a24807d1efcdeefa"
+dependencies = [
+ "proc-macro-error2",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "heck"
 version = "0.5.0"
@@ -161,6 +198,12 @@ version = "1.70.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf"

+[[package]]
+name = "memchr"
+version = "2.7.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273"
+
 [[package]]
 name = "mmu-table-gen"
 version = "0.1.0"
@@ -190,12 +233,50 @@ dependencies = [
 "syn",
 ]

+[[package]]
+name = "once_cell"
+version = "1.21.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d"
+dependencies = [
+ "critical-section",
+ "portable-atomic",
+]
+
 [[package]]
 name = "once_cell_polyfill"
 version = "1.70.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "a4895175b425cb1f87721b59f0f286c2092bd4af812243672510e1ac53e2e0ad"

+[[package]]
+name = "portable-atomic"
+version = "1.11.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f84267b20a16ea918e43c6a88433c2d54fa145c92a811b5b047ccbe153674483"
+
+[[package]]
+name = "proc-macro-error-attr2"
+version = "2.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "96de42df36bb9bba5542fe9f1a054b8cc87e172759a1868aa05c1f3acc89dfc5"
+dependencies = [
+ "proc-macro2",
+ "quote",
+]
+
+[[package]]
+name = "proc-macro-error2"
+version = "2.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "11ec05c52be0a07b08061f7dd003e7d7092e0472bc731b4af7bb1ef876109802"
+dependencies = [
+ "proc-macro-error-attr2",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "proc-macro2"
 version = "1.0.101"
@@ -214,12 +295,47 @@ dependencies = [
 "proc-macro2",
 ]

+[[package]]
+name = "regex"
+version = "1.11.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8b5288124840bee7b386bc413c487869b360b2b4ec421ea56425128692f2a82c"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-automata",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-automata"
+version = "0.4.11"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "833eb9ce86d40ef33cb1306d8accf7bc8ec2bfea4355cbdebb3df68b40925cad"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-syntax"
+version = "0.8.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "caf4aa5b0f434c91fe5c7f1ecb6a5ece2130b02ad2a590589dda5146df959001"
+
 [[package]]
 name = "rustversion"
 version = "1.0.22"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b39cdef0fa800fc44525c84ccb54a029961a8215f9619753635a9c0d2538d46d"

+[[package]]
+name = "static_assertions"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a2eb9349b6444b326872e140eb1cf5e7c522154d69e7a0ffb0fb81c06b37543f"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"
@@ -349,6 +465,19 @@ version = "0.53.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d6bbff5f0aada427a1e5a6da5f1f98158182f26556f345ac9e04d36d0ebed650"

+[[package]]
+name = "zynq7000"
+version = "0.1.0"
+dependencies = [
+ "arbitrary-int 2.0.0",
+ "bitbybit",
+ "derive-mmio",
+ "once_cell",
+ "rustversion",
+ "static_assertions",
+ "thiserror",
+]
+
 [[package]]
 name = "zynq7000-boot-image"
 version = "0.1.0"
@@ -371,6 +500,8 @@ name = "zynq7000-ps7init-extract"
 version = "0.1.0"
 dependencies = [
 "clap",
+ "regex",
+ "zynq7000",
 ]

 [[package]]
--- a/tools/zynq7000-ps7init-extract/Cargo.toml
+++ b/tools/zynq7000-ps7init-extract/Cargo.toml
@@ -5,3 +5,5 @@ edition = "2024"

 [dependencies]
 clap = { version = "4", features = ["derive"] }
+zynq7000 = { path = "../../zynq/zynq7000" }
+regex = "1"
--- a/tools/zynq7000-ps7init-extract/src/main.rs
+++ b/tools/zynq7000-ps7init-extract/src/main.rs
@@ -1,6 +1,12 @@
-use std::{fs::File, path::Path};
+use std::{
+    fs::File,
+    io::{BufRead, BufWriter},
+    path::Path,
+};

 use clap::Parser as _;
+use std::io::Write as _;
+use zynq7000::ddrc::regs;

 #[derive(clap::Parser, Debug)]
 #[command(version, about)]
@@ -10,13 +16,78 @@ pub struct Cli {
    path: String,
 }

-fn main() {
+fn extract_hex_values(line: &str) -> Option<(u32, u32, u32)> {
+    let re = regex::Regex::new(r"0[xX]([0-9A-Fa-f]+)").unwrap();
+
+    let captures: Vec<u32> = re
+        .captures_iter(line)
+        .filter_map(|cap| u32::from_str_radix(&cap[1], 16).ok())
+        .collect();
+
+    if captures.len() == 3 {
+        Some((captures[0], captures[1], captures[2]))
+    } else {
+        None
+    }
+}
+
+fn main() -> std::io::Result<()> {
    let cli = Cli::parse();
    let ps7init_tcl = Path::new(&cli.path);
    if !ps7init_tcl.exists() {
        eprintln!("File not found: {}", ps7init_tcl.display());
        std::process::exit(1);
    }
+    let mut ddrc_config = None;
+    let mut two_rank_config = None;
+    let mut hpr_config = None;
+    for maybe_line in std::fs::read(ps7init_tcl).unwrap().lines() {
+        if let Ok(line) = maybe_line
+            && let Some((addr, _mask, value)) = extract_hex_values(&line)
+        {
+            match addr {
+                0xf800_6000 => ddrc_config = Some(regs::DdrcControl::new_with_raw_value(value)),
+                0xf800_6004 => {
+                    two_rank_config = Some(regs::TwoRankConfig::new_with_raw_value(value))
+                }
+                0xf800_6008 => {
+                    hpr_config = Some(regs::LprHprQueueControl::new_with_raw_value(value))
+                }
+                _ => (),
+            }
+        }
+    }
+
    let file_path = "ddr_config.rs";
    let file = File::create(file_path).expect("Failed to create file");
+    let mut writer = BufWriter::new(file);
+    writeln!(
+        writer,
+        "//! This file was auto-generated by the zynq7000-ps7init-extract program"
+    )?;
+    writeln!(writer, "//!")?;
+    writeln!(
+        writer,
+        "//! This configuration file contains static DDR configuration parameters extracted from the AMD ps7init.tcl file"
+    )?;
+    writeln!(writer, "use zynq7000::ddrc::regs;")?;
+
+    writeln!(
+        writer,
+        "pub const DDRC_CONFIG_ZEDBOARD_FULL_BUILDERS: DdrcConfigSet = DdrcConfigSet {{"
+    )?;
+    writeln!(
+        writer,
+        "    ctrl: regs::DdrcControl::new_with_raw_value({:#08x})",
+        ddrc_config.expect("DDR control unknown").raw_value()
+    )?;
+    writeln!(
+        writer,
+        "    ctrl: regs::TwoRankConfig::new_with_raw_value({:#08x})",
+        two_rank_config
+            .expect("two rank config unknown")
+            .raw_value()
+    )?;
+    writeln!(writer, "}}")?;
+    Ok(())
 }
--- a/zynq/zynq7000-hal/src/ddr/ll.rs
+++ b/zynq/zynq7000-hal/src/ddr/ll.rs
@@ -212,6 +212,7 @@ pub unsafe fn configure_iob(cfg_set: &DdriobConfigSet) {
 }

 /// Full static DDRC configuration set.
+#[derive(Debug)]
 pub struct DdrcConfigSet {
    pub ctrl: DdrcControl,
    pub two_rank: TwoRankConfig,
--- a/zynq/zynq7000/src/ddrc.rs
+++ b/zynq/zynq7000/src/ddrc.rs
@@ -16,7 +16,7 @@ pub mod regs {
        Reset = 0,
        Active = 1,
    }
-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DdrcControl {
        #[bit(16, rw)]
        disable_auto_refresh: bool,
@@ -36,7 +36,7 @@ pub mod regs {
        soft_reset: SoftReset,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct TwoRankConfig {
        #[bits(14..=18, rw)]
        addrmap_cs_bit0: u5,
@@ -49,7 +49,7 @@ pub mod regs {
    }

    /// Queue control for the low priority and high priority read queues.
-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct LprHprQueueControl {
        #[bits(22..=25, rw)]
        xact_run_length: u4,
@@ -59,7 +59,7 @@ pub mod regs {
        min_non_critical_x32: u11,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct WriteQueueControl {
        #[bits(15..=25, rw)]
        max_starve_x32: u11,
@@ -69,7 +69,7 @@ pub mod regs {
        min_non_critical_x32: u11,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramParamReg0 {
        /// Minimum time to wait after coming out of self refresh before doing anything. This must be
        /// bigger than all the constraints that exist.
@@ -84,7 +84,7 @@ pub mod regs {
        t_rc: u6,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramParamReg1 {
        #[bits(28..=31, rw)]
        t_cke: u4,
@@ -100,7 +100,7 @@ pub mod regs {
        wr2pre: u5,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramParamReg2 {
        #[bits(28..=31, rw)]
        t_rcd: u4,
@@ -120,11 +120,12 @@ pub mod regs {

    /// Weird naming.
    #[bitbybit::bitenum(u1, exhaustive = true)]
+    #[derive(Debug)]
    pub enum MobileSetting {
        Ddr2Ddr3 = 0,
        Lpddr2 = 1,
    }
-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramParamReg3 {
        #[bit(30, rw)]
        disable_pad_pd_feature: bool,
@@ -151,12 +152,13 @@ pub mod regs {
    }

    #[bitbybit::bitenum(u1, exhaustive = true)]
+    #[derive(Debug)]
    pub enum ModeRegisterType {
        Write = 0,
        Read = 1,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramParamReg4 {
        #[bit(27, rw)]
        mr_rdata_valid: bool,
@@ -176,7 +178,7 @@ pub mod regs {
        enable_2t_timing_mode: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramInitParam {
        #[bits(11..=13, rw)]
        t_mrd: u3,
@@ -186,7 +188,7 @@ pub mod regs {
        final_wait_x32: u7,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramEmr {
        #[bits(16..=31, rw)]
        emr3: u16,
@@ -194,7 +196,7 @@ pub mod regs {
        emr2: u16,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramEmrMr {
        #[bits(16..=31, rw)]
        emr: u16,
@@ -202,7 +204,7 @@ pub mod regs {
        mr: u16,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramBurst8ReadWrite {
        #[bits(0..=3, rw)]
        burst_rdwr: u4,
@@ -214,7 +216,7 @@ pub mod regs {
        burstchop: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DisableDq {
        #[bit(1, rw)]
        dis_dq: bool,
@@ -222,7 +224,7 @@ pub mod regs {
        force_low_pri_n: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramAddrMapBank {
        #[bits(16..=19, rw)]
        addrmap_bank_b6: u4,
@@ -236,7 +238,7 @@ pub mod regs {
        addrmap_bank_b0: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramAddrMapColumn {
        #[bits(28..=31, rw)]
        addrmap_col_b11: u4,
@@ -256,7 +258,7 @@ pub mod regs {
        addrmap_col_b2: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramAddrMapRow {
        #[bits(24..=27, rw)]
        addrmap_row_b15: u4,
@@ -274,7 +276,7 @@ pub mod regs {
        addrmap_row_b0: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DramOdt {
        #[bits(16..=17, rw)]
        phy_idle_local_odt: u2,
@@ -288,7 +290,7 @@ pub mod regs {
        rank0_rd_odt: u3,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyCmdTimeoutRdDataCpt {
        #[bits(28..=31, rw)]
        wrlvl_num_of_dq0: u4,
@@ -311,18 +313,19 @@ pub mod regs {
    }

    #[bitbybit::bitenum(u1, exhaustive = true)]
+    #[derive(Debug)]
    pub enum DllCalibSel {
        Periodic = 0,
        Manual = 1,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DllCalib {
        #[bit(16, rw)]
        sel: DllCalibSel,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct OdtDelayHold {
        #[bits(12..=15, rw)]
        wr_odt_hold: u4,
@@ -334,7 +337,7 @@ pub mod regs {
        rd_odt_delay: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CtrlReg1 {
        #[bit(12, rw)]
        selfref_enable: bool,
@@ -352,7 +355,7 @@ pub mod regs {
        pageclose: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CtrlReg2 {
        #[bit(17, rw)]
        go_2_critcal_enable: bool,
@@ -360,7 +363,7 @@ pub mod regs {
        go_2_critical_hysteresis: u8,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CtrlReg3 {
        #[bits(16..=25, rw)]
        dfi_t_wlmrd: u10,
@@ -370,7 +373,7 @@ pub mod regs {
        wrlvl_ww: u8,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CtrlReg4 {
        #[bits(8..=15, rw)]
        dfi_t_ctrlupd_interval_max_x1024: u8,
@@ -378,7 +381,7 @@ pub mod regs {
        dfi_t_ctrlupd_interval_min_x1024: u8,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CtrlReg5 {
        #[bits(20..=25, rw)]
        t_ckesr: u6,
@@ -394,7 +397,7 @@ pub mod regs {
        dfi_t_ctrl_delay: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CtrlReg6 {
        #[bits(16..=19, rw)]
        t_cksx: u4,
@@ -408,7 +411,7 @@ pub mod regs {
        t_ckpde: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CheTZq {
        #[bits(22..=31, rw)]
        t_zq_short_nop: u10,
@@ -422,7 +425,7 @@ pub mod regs {
        dis_auto_zq: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CheTZqShortInterval {
        #[bits(20..=27, rw)]
        dram_rstn_x1024: u8,
@@ -430,7 +433,7 @@ pub mod regs {
        t_zq_short_interval: u20,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DeepPowerdown {
        #[bits(1..=8, rw)]
        deep_powerdown_to_x1024: u8,
@@ -438,7 +441,7 @@ pub mod regs {
        enable: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct Reg2c {
        #[bit(28, rw)]
        dfi_rd_data_eye_train: bool,
@@ -456,13 +459,13 @@ pub mod regs {
        dfi_wrlvl_max_x1024: u12,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct Reg2d {
        #[bit(9, rw)]
        skip_ocd: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct DfiTiming {
        #[bits(15..=24, rw)]
        dfi_t_ctrlup_max: u10,
@@ -472,7 +475,7 @@ pub mod regs {
        dfi_t_rddata_enable: u5,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct CheEccControl {
        #[bit(1, rw)]
        clear_correctable_errors: bool,
@@ -481,12 +484,13 @@ pub mod regs {
    }

    #[bitbybit::bitenum(u3, exhaustive = false)]
+    #[derive(Debug)]
    pub enum EccMode {
        NoEcc = 0b000,
        SecDecOverOneBeat = 0b100,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct EccScrub {
        #[bit(3, rw)]
        disable_scrub: bool,
@@ -494,7 +498,7 @@ pub mod regs {
        ecc_mode: Option<EccMode>,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyReceiverEnable {
        #[bits(4..=7, rw)]
        phy_dif_off: u4,
@@ -502,7 +506,7 @@ pub mod regs {
        phy_dif_on: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyConfig {
        #[bits(24..=30, rw)]
        dq_offset: u7,
@@ -516,7 +520,7 @@ pub mod regs {
        data_slice_in_use: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyInitRatio {
        #[bits(10..=19, rw)]
        gatelvl_init_ratio: u10,
@@ -524,7 +528,7 @@ pub mod regs {
        wrlvl_init_ratio: u10,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyDqsConfig {
        #[bits(11..=19, rw)]
        dqs_slave_delay: u9,
@@ -534,7 +538,7 @@ pub mod regs {
        dqs_slave_ratio: u10,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyWriteEnableConfig {
        #[bits(12..=20, rw)]
        fifo_we_in_delay: u9,
@@ -544,7 +548,7 @@ pub mod regs {
        fifo_we_slave_ratio: u11,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct PhyWriteDataSlaveConfig {
        #[bits(11..=19, rw)]
        wr_data_slave_delay: u9,
@@ -554,7 +558,7 @@ pub mod regs {
        wr_data_slave_ratio: u10,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct Reg64 {
        #[bit(30, rw)]
        cmd_latency: bool,
@@ -574,7 +578,7 @@ pub mod regs {
        bl2: bool,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct Reg65 {
        #[bits(18..=19, rw)]
        ctrl_slave_delay: u2,
@@ -594,7 +598,7 @@ pub mod regs {
        wr_rl_delay: u5,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct AxiPriorityWritePort {
        #[bit(18, rw)]
        disable_page_match: bool,
@@ -606,7 +610,7 @@ pub mod regs {
        pri_wr_port: u10,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct AxiPriorityReadPort {
        #[bit(19, rw)]
        enable_hpr: bool,
@@ -620,7 +624,7 @@ pub mod regs {
        pri_rd_port_n: u10,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct ExclusiveAccessConfig {
        #[bits(9..=17, rw)]
        access_id1_port: u9,
@@ -629,12 +633,13 @@ pub mod regs {
    }

    #[bitbybit::bitenum(u1, exhaustive = true)]
+    #[derive(Debug)]
    pub enum LpddrBit {
        Ddr2Ddr3 = 0,
        Lpddr2 = 1,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct LpddrControl0 {
        #[bits(4..=11, rw)]
        mr4_margin: u8,
@@ -646,13 +651,13 @@ pub mod regs {
        lpddr2: LpddrBit,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct LpddrControl1 {
        #[bits(0..=31, rw)]
        mr4_read_interval: u32,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct LpddrControl2 {
        #[bits(12..=21, rw)]
        t_mrw: u10,
@@ -662,7 +667,7 @@ pub mod regs {
        min_stable_clock_x1: u4,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct LpddrControl3 {
        #[bits(8..=17, rw)]
        dev_zqinit_x32: u10,
@@ -702,7 +707,7 @@ pub mod regs {
        CommandsNotAccepted = 1,
    }

-    #[bitbybit::bitfield(u32, default = 0x0)]
+    #[bitbybit::bitfield(u32, default = 0x0, debug)]
    pub struct ModeStatus {
        #[bits(16..=20, r)]
        dbg_hpr_queue_depth: u5,
--- a/zynq/zynq7000/src/eth.rs
+++ b/zynq/zynq7000/src/eth.rs
@@ -82,8 +82,7 @@ impl MdcClockDivisor {
    }
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct NetworkConfig {
    #[bit(30, rw)]
    ignore_ipg_rx_error: bool,
@@ -141,8 +140,7 @@ pub struct NetworkConfig {
 }

 /// PHY management status information.
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct NetworkStatus {
    #[bit(6, r)]
    pfc_pri_pause_neg: bool,
@@ -215,8 +213,7 @@ impl DmaRxBufSize {
    }
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct DmaConfig {
    #[bit(24, rw)]
    discard_when_ahb_full: bool,
@@ -244,8 +241,7 @@ pub struct DmaConfig {
    burst_length: u5,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct TxStatus {
    #[bit(8, rw)]
    hresp_not_ok: bool,
@@ -276,8 +272,7 @@ impl TxStatus {
    }
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct RxStatus {
    #[bit(3, rw)]
    hresp_not_ok: bool,
@@ -295,8 +290,7 @@ impl RxStatus {
    }
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct InterruptStatus {
    #[bit(26, rw)]
    tsu_sec_incr: bool,
@@ -392,8 +386,7 @@ pub enum PhyOperation {
    Write = 0b01,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct PhyMaintenance {
    /// Must be 1 for Clause 22 operations.
    #[bit(30, rw)]
@@ -410,15 +403,13 @@ pub struct PhyMaintenance {
    data: u16,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct PauseQuantum {
    #[bits(0..=15, rw)]
    value: u16,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct MatchRegister {
    #[bit(31, rw)]
    copy_enable: bool,
--- a/zynq/zynq7000/src/gic.rs
+++ b/zynq/zynq7000/src/gic.rs
@@ -4,7 +4,7 @@ use arbitrary_int::{u3, u5, u10};
 use static_assertions::const_assert_eq;

 /// Distributor Control Register
-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DistributorControlRegister {
    #[bit(1, rw)]
    enable_non_secure: bool,
@@ -13,7 +13,7 @@ pub struct DistributorControlRegister {
 }

 /// Read only bit. This register only returns fixed constants.
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct TypeRegister {
    #[bits(11..=15, r)]
    lspi: u5,
@@ -127,7 +127,7 @@ impl GicDistributor {
 }

 /// CPU interface control register.
-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct InterfaceControl {
    #[bit(4, rw)]
    sbpr: bool,
@@ -142,15 +142,14 @@ pub struct InterfaceControl {
 }

 /// Priority Mask Register
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct PriorityRegister {
    #[bits(0..=7, rw)]
    priority: u8,
 }

 /// Interrupt acknowledge register.
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptSignalRegister {
    #[bits(10..=12, rw)]
    cpu_id: u3,
--- a/zynq/zynq7000/src/gpio.rs
+++ b/zynq/zynq7000/src/gpio.rs
@@ -1,6 +1,5 @@
 //! # GPIO register module.
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct MaskedOutput {
    #[bits(16..=31, w)]
    pub mask: u16,
--- a/zynq/zynq7000/src/gtc.rs
+++ b/zynq/zynq7000/src/gtc.rs
@@ -2,7 +2,7 @@

 pub const GTC_BASE_ADDR: usize = super::mpcore::MPCORE_BASE_ADDR + 0x0000_0200;

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct GtcControl {
    #[bits(8..=15, rw)]
    prescaler: u8,
@@ -16,7 +16,7 @@ pub struct GtcControl {
    enable: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptStatus {
    #[bit(0, rw)]
    event_flag: bool,
--- a/zynq/zynq7000/src/i2c.rs
+++ b/zynq/zynq7000/src/i2c.rs
@@ -18,7 +18,7 @@ pub enum Mode {
    Master = 0b1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct Control {
    /// Divides the input PCLK frequency by this value + 1
    #[bits(14..=15, rw)]
@@ -47,7 +47,7 @@ pub struct Control {
    dir: Direction,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Status {
    #[bit(8, r)]
    bus_active: bool,
@@ -65,19 +65,19 @@ pub struct Status {
    rx_rw: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Address {
    #[bits(0..=9, rw)]
    addr: u10,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Fifo {
    #[bits(0..=7, rw)]
    data: u8,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptStatus {
    #[bit(9, rw)]
    arbitration_lost: bool,
@@ -99,7 +99,7 @@ pub struct InterruptStatus {
    complete: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptMask {
    #[bit(9, r)]
    arbitration_lost: bool,
@@ -143,14 +143,14 @@ pub struct InterruptControl {
    complete: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Timeout {
    /// Reset value: 0x1F.
    #[bits(0..=7, rw)]
    timeout: u8,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct TransferSize {
    #[bits(0..=7, rw)]
    size: u8,
--- a/zynq/zynq7000/src/l2_cache.rs
+++ b/zynq/zynq7000/src/l2_cache.rs
@@ -9,15 +9,13 @@ pub struct LockdownRegisters {
    instruction: u32,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct CacheSync {
    #[bit(0, r)]
    busy: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DebugControl {
    #[bit(2, rw)]
    spniden: bool,
@@ -27,8 +25,7 @@ pub struct DebugControl {
    disable_cache_linefill: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct CacheId {
    #[bits(24..=31, r)]
    implementer: u8,
@@ -86,7 +83,7 @@ pub enum Associativity {
    _16Way = 1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct AuxControl {
    #[bit(30, rw)]
    early_bresp_enable: bool,
@@ -125,7 +122,7 @@ pub struct AuxControl {
    full_line_zero_enable: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 #[derive(Debug, PartialEq, Eq)]
 pub struct LatencyConfig {
    /// Latency is the numerical value + 1 cycles.
@@ -139,8 +136,7 @@ pub struct LatencyConfig {
    setup_latency: u3,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptStatus {
    #[bit(8, r)]
    dec_error_l3: bool,
--- a/zynq/zynq7000/src/priv_tim.rs
+++ b/zynq/zynq7000/src/priv_tim.rs
@@ -2,7 +2,7 @@

 pub const CPU_PRIV_TIM_BASE_ADDR: usize = super::mpcore::MPCORE_BASE_ADDR + 0x0000_0600;

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct Control {
    #[bits(8..=15, rw)]
    prescaler: u8,
@@ -14,7 +14,7 @@ pub struct Control {
    enable: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct InterruptStatus {
    /// Cleared by writing a one.
    #[bit(0, rw)]
--- a/zynq/zynq7000/src/qspi.rs
+++ b/zynq/zynq7000/src/qspi.rs
@@ -48,7 +48,9 @@ impl BaudRateDivisor {
    }
 }

+// TODO: Use bitbybit debug support as soon as support for write fields has been implemented.
 #[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
 pub struct Config {
    #[bit(31, rw)]
    interface_mode: InterfaceMode,
@@ -79,7 +81,7 @@ pub struct Config {
    mode_select: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptStatus {
    /// Write-to-clear bit.
    #[bit(6, rw)]
@@ -113,7 +115,7 @@ pub struct InterruptControl {
    rx_overrun: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptMask {
    #[bit(6, r)]
    tx_underflow: bool,
@@ -129,14 +131,14 @@ pub struct InterruptMask {
    rx_overrun: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct SpiEnable {
    #[bit(0, rw)]
    enable: bool,
 }

 /// All the delays are in SPI reference block or external clock cycles.
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Delay {
    /// Length of the master mode chip select output de-asserts between words when CPHA = 0.
    #[bits(24..=31, rw)]
@@ -159,7 +161,7 @@ pub struct Gpio {
    write_protect_n: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct LoopbackMasterClockDelay {
    /// Use internal loopback master clock for read data capturing when the baud rate divisor
    /// is 2.
@@ -182,7 +184,7 @@ pub enum InstructionCode {
    FastReadQuadIo = 0xEB,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct LinearQspiConfig {
    #[bit(31, rw)]
    enable_linear_mode: bool,
@@ -210,7 +212,7 @@ pub struct LinearQspiConfig {
    instruction_code: Option<InstructionCode>,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct LinearQspiStatus {
    #[bit(2, rw)]
    data_fsm_error: bool,
--- a/zynq/zynq7000/src/slcr/ddriob.rs
+++ b/zynq/zynq7000/src/slcr/ddriob.rs
@@ -1,6 +1,7 @@
 use arbitrary_int::{u2, u3};

 #[bitbybit::bitenum(u4, exhaustive = false)]
+#[derive(Debug)]
 pub enum VRefSel {
    /// VREF = 0.6 V
    Lpddr2 = 0b0001,
@@ -12,7 +13,7 @@ pub enum VRefSel {
    Ddr2 = 0b1000,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct DdrControl {
    /// Enables VRP/VRN.
    #[bit(9, rw)]
@@ -27,7 +28,7 @@ pub struct DdrControl {
    vref_int_en: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x00)]
+#[bitbybit::bitfield(u32, default = 0x00, debug)]
 pub struct DciControl {
    #[bit(20, rw)]
    update_control: bool,
@@ -48,7 +49,7 @@ pub struct DciControl {
    reset: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct DciStatus {
    #[bit(13, rw)]
    done: bool,
@@ -83,7 +84,7 @@ pub enum DciType {
    DciTermination = 0b11,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DdriobConfig {
    #[bit(11, rw)]
    pullup_enable: bool,
--- a/zynq/zynq7000/src/slcr/mio.rs
+++ b/zynq/zynq7000/src/slcr/mio.rs
@@ -4,12 +4,14 @@
 use arbitrary_int::{u2, u3};

 #[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug)]
 pub enum Speed {
    SlowCmosEdge = 0b0,
    FastCmosEdge = 0b1,
 }

 #[bitbybit::bitenum(u3)]
+#[derive(Debug)]
 pub enum IoType {
    LvCmos18 = 0b001,
    LvCmos25 = 0b010,
@@ -17,8 +19,8 @@ pub enum IoType {
    Hstl = 0b100,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
+#[derive(PartialEq, Eq)]
 pub struct Config {
    #[bit(13, rw)]
    disable_hstl_rcvr: bool,
--- a/zynq/zynq7000/src/slcr/mod.rs
+++ b/zynq/zynq7000/src/slcr/mod.rs
@@ -17,6 +17,7 @@ pub mod mio;
 pub mod reset;

 #[bitbybit::bitenum(u3, exhaustive = false)]
+#[derive(Debug)]
 pub enum VrefSel {
    Disabled = 0b000,
    Vref0_9V = 0b001,
@@ -84,7 +85,7 @@ pub enum LevelShifterConfig {
    EnableAll = 0xF,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct LevelShifterRegister {
    #[bits(0..=3, rw)]
    user_lvl_shftr_en: Option<LevelShifterConfig>,
--- a/zynq/zynq7000/src/slcr/reset.rs
+++ b/zynq/zynq7000/src/slcr/reset.rs
@@ -1,7 +1,6 @@
 use super::{RESET_BLOCK_OFFSET, SLCR_BASE_ADDR};

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DualClockReset {
    /// Peripheral 1 AMBA software reset.
    #[bit(1, rw)]
@@ -11,8 +10,7 @@ pub struct DualClockReset {
    periph0_cpu1x_rst: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DualRefAndClockReset {
    /// Periperal 1 Reference software reset.
    #[bit(3, rw)]
@@ -28,15 +26,13 @@ pub struct DualRefAndClockReset {
    periph0_cpu1x_rst: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct GpioClockReset {
    #[bit(0, rw)]
    gpio_cpu1x_rst: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct EthernetReset {
    #[bit(5, rw)]
    gem1_ref_rst: bool,
@@ -52,8 +48,7 @@ pub struct EthernetReset {
    gem0_cpu1x_rst: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct QspiResetControl {
    #[bit(2, rw)]
    qspi_ref_reset: bool,
--- a/zynq/zynq7000/src/spi.rs
+++ b/zynq/zynq7000/src/spi.rs
@@ -33,6 +33,7 @@ impl BaudDivSel {
    }
 }

+// TODO: Use bitbybit debug support as soon as it was added.
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
 pub struct Config {
@@ -67,7 +68,7 @@ pub struct Config {
    master_ern: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 #[derive(Debug)]
 pub struct InterruptStatus {
    #[bit(6, rw)]
@@ -107,8 +108,7 @@ pub struct InterruptControl {
    rx_ovr: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptMask {
    #[bit(6, r)]
    tx_underflow: bool,
@@ -163,8 +163,7 @@ impl FifoRead {
 }

 /// The numbers specified in the register fields are always specified in number of
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DelayControl {
    /// Number of cycles the chip select is de-asserted between words when CPHA = 0
    #[bits(24..=31, rw)]
--- a/zynq/zynq7000/src/ttc.rs
+++ b/zynq/zynq7000/src/ttc.rs
@@ -13,7 +13,7 @@ pub enum ClockSource {
    External = 0b1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct ClockControl {
    /// When this bit is set and the external clock is selected, the counter clocks on the
    /// negative edge of the external clock input.
@@ -27,15 +27,15 @@ pub struct ClockControl {
    prescale_enable: bool,
 }

-#[derive(Debug)]
 #[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug)]
 pub enum Mode {
    Overflow = 0b0,
    Interval = 0b1,
 }

-#[derive(Debug, Default)]
 #[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug, Default)]
 pub enum WavePolarity {
    /// The waveform output goes from high to low on a match 0 interrupt and returns high on
    /// overflow or interval interrupt.
@@ -46,14 +46,14 @@ pub enum WavePolarity {
    LowToHighOnMatch1 = 0b1,
 }

-#[derive(Debug)]
 #[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug)]
 pub enum WaveEnable {
    Enable = 0b0,
    Disable = 0b1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct CounterControl {
    #[bit(6, rw)]
    wave_polarity: WavePolarity,
@@ -76,19 +76,19 @@ pub struct CounterControl {
    disable: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Counter {
    #[bits(0..=15, r)]
    count: u16,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct RwValue {
    #[bits(0..=15, rw)]
    value: u16,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptStatus {
    /// Even timer overflow interrupt.
    #[bit(5, r)]
@@ -105,7 +105,7 @@ pub struct InterruptStatus {
    interval: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct InterruptControl {
    /// Even timer overflow interrupt.
    #[bit(5, rw)]
@@ -122,7 +122,7 @@ pub struct InterruptControl {
    interval: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct EventControl {
    /// E_Ov bit. When set to 0, the event timer is disabled and set to 0 when an event timer
    /// register overflow occurs. Otherwise, continue counting on overflow.
@@ -136,7 +136,7 @@ pub struct EventControl {
    enable: bool,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct EventCount {
    #[bits(0..=15, r)]
    count: u16,
--- a/zynq/zynq7000/src/uart.rs
+++ b/zynq/zynq7000/src/uart.rs
@@ -55,8 +55,7 @@ pub enum ChMode {
    RemoteLoopback = 0b11,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Control {
    /// Stop transmitter break.
    #[bit(8, rw)]
@@ -87,8 +86,7 @@ pub struct Control {
    rx_rst: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct Mode {
    #[bits(8..=9, rw)]
    chmode: ChMode,
@@ -103,35 +101,32 @@ pub struct Mode {
    clksel: ClockSelect,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0, debug)]
 pub struct Baudgen {
    #[bits(0..=15, rw)]
    cd: u16,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0, debug)]
 pub struct BaudRateDivisor {
    #[bits(0..=7, rw)]
    bdiv: u8,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Fifo {
    #[bits(0..=7, rw)]
    fifo: u8,
 }

 #[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug)]
 pub enum Ttrig {
    LessThanTTrig = 0b0,
    GreaterEqualTTrig = 0b1,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct Status {
    #[bit(14, r)]
    tx_near_full: bool,
@@ -230,8 +225,7 @@ pub struct InterruptMask {
    rx_trg: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct InterruptStatus {
    #[bit(12, rw)]
    tx_over: bool,