Ethernet and smoltcp/embassy-net support

examples/embassy/Cargo.toml

@@ -11,7 +11,9 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-cortex-ar = "0.2"
+# cortex-ar = "0.2"
+# cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", features = ["critical-section-single-core"] }
+cortex-ar = { version = "0.2", path = "../../../../Rust/cortex-ar/cortex-ar", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
@@ -25,11 +27,17 @@ embedded-hal = "1"
 fugit = "0.3"
 log = "0.4"
 
-embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = [
+# embassy-executor = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", features = [
+  # "arch-cortex-ar",
+  # "executor-thread",
+  # "task-arena-size-65536"
+# ]}
+embassy-executor = { path = "../../../../Rust/embassy/embassy-executor", features = [
   "arch-cortex-ar",
   "executor-thread",
 ]}
-embassy-time = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", version = "0.4", features = ["tick-hz-1_000_000"] }
+# embassy-time = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.4", features = ["tick-hz-1_000_000"] }
+embassy-time = { path = "../../../../Rust/embassy/embassy-time", version = "0.4", features = ["tick-hz-1_000_000"] }
 
 [profile.release]
 codegen-units = 1

examples/simple/Cargo.toml

@@ -9,7 +9,9 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
 license = "MIT OR Apache-2.0"
 
 [dependencies]
-cortex-ar = "0.2"
+# cortex-ar = "0.2"
+# cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
+cortex-ar = { version = "0.2", path = "../../../../Rust/cortex-ar/cortex-ar", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }

examples/simple/src/main.rs

@@ -57,8 +57,8 @@ pub fn main() -> ! {
     }
 }
 
-#[unsafe(no_mangle)]
-pub extern "C" fn _irq_handler() {}
+#[zynq7000_rt::irq]
+pub fn irq_handler() {}
 
 #[unsafe(no_mangle)]
 pub extern "C" fn _abort_handler() {

examples/zedboard/Cargo.toml

@@ -11,13 +11,16 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-cortex-ar = "0.2"
+# cortex-ar = "0.2"
+# cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", features = ["critical-section-single-core"] }
+cortex-ar = { version = "0.2", path = "../../../../Rust/cortex-ar/cortex-ar", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
 zynq7000-embassy = { path = "../../zynq7000-embassy" }
 l3gd20 = { git = "https://github.com/us-irs/l3gd20.git", branch = "add-async-if" }
 embedded-io = "0.6"
+bitbybit = "1.3"
 arbitrary-int = "1.3"
 embedded-io-async = "0.6"
 critical-section = "1"
@@ -27,12 +30,20 @@ embedded-hal = "1"
 embedded-hal-async = "1"
 fugit = "0.3"
 log = "0.4"
+rand = { version = "0.9", default-features = false, features = ["small_rng"] }
 
-embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = [
+# embassy-executor = { git = "https://github.com/us-irs/embassy", path = "../embassy/embassy-executor", branch = "local-cortex-ar", features = [
+# "arch-cortex-ar",
+# "executor-thread",
+# ]}
+embassy-executor = { path = "../../../../Rust/embassy/embassy-executor", features = [
   "arch-cortex-ar",
   "executor-thread",
 ]}
-embassy-time = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", version = "0.4", features = ["tick-hz-1_000_000"] }
+# embassy-time = { git = "https://github.com/us-irs/embassy", branch = "local-cortex-ar", version = "0.4", features = ["tick-hz-1_000_000"] }
+embassy-time = { path = "../../../../Rust/embassy/embassy-time", version = "0.4", features = ["tick-hz-1_000_000"] }
+embassy-net = { path = "../../../../Rust/embassy/embassy-net", version = "0.7", features = ["dhcpv4", "packet-trace", "medium-ethernet", "icmp", "tcp", "udp"] }
+embassy-sync = { path = "../../../../Rust/embassy/embassy-sync", version = "0.7" }
 heapless = "0.8"
 axi-uartlite = { git = "https://egit.irs.uni-stuttgart.de/rust/axi-uartlite.git" }
 axi-uart16550 = { git = "https://egit.irs.uni-stuttgart.de/rust/axi-uart16550.git" }

examples/zedboard/src/bin/ethernet.rs

@@ -0,0 +1,490 @@
+#![no_std]
+#![no_main]
+
+use core::{
+    cell::UnsafeCell, mem::MaybeUninit, net::Ipv4Addr, panic::PanicInfo, sync::atomic::AtomicBool,
+};
+use cortex_ar::asm::nop;
+use embassy_executor::Spawner;
+use embassy_net::{Ipv4Cidr, StaticConfigV4};
+use embassy_time::{Duration, Ticker, Timer};
+use embedded_hal::digital::StatefulOutputPin;
+use embedded_io::Write;
+use log::{debug, error, info};
+use rand::{RngCore, SeedableRng};
+use zedboard::{
+    phy_marvell::{LatchingLinkStatus, MARVELL_88E1518_OUI},
+    PS_CLOCK_FREQUENCY,
+};
+use zynq7000_hal::{
+    clocks::Clocks,
+    configure_level_shifter,
+    eth::{
+        embassy_net::InterruptResult, AlignedBuffer, ClkDivCollection, EthernetConfig,
+        EthernetLowLevel,
+    },
+    gic::{GicConfigurator, GicInterruptHelper, Interrupt},
+    gpio::{GpioPins, Output, PinState},
+    gtc::Gtc,
+    uart::{ClkConfigRaw, Uart, UartConfig},
+    BootMode,
+};
+
+use zynq7000::{slcr::LevelShifterConfig, PsPeripherals};
+use zynq7000_rt::{self as _, mmu::section_attrs::SHAREABLE_DEVICE, mmu_l1_table_mut};
+
+const INIT_STRING: &str = "-- Zynq 7000 Zedboard Ethernet Example --\n\r";
+// Unicast address with OUI of the Marvell 88E1518 PHY.
+const MAC_ADDRESS: [u8; 6] = [
+    0x00,
+    ((MARVELL_88E1518_OUI >> 8) & 0xff) as u8,
+    (MARVELL_88E1518_OUI & 0xff) as u8,
+    0x00,
+    0x00,
+    0x01,
+];
+
+/// See memory.x file. 1 MB starting at this address will be configured as uncached memory using the
+/// MMU.
+const UNCACHED_ADDR: u32 = 0x4000000;
+
+const NUM_RX_SLOTS: usize = 16;
+const NUM_TX_SLOTS: usize = 16;
+
+static RX_DESCR_TAKEN: AtomicBool = AtomicBool::new(false);
+static TX_DESCR_TAKEN: AtomicBool = AtomicBool::new(false);
+
+#[repr(transparent)]
+pub struct RxDescriptor(
+    pub UnsafeCell<MaybeUninit<[zynq7000_hal::eth::rx_descr::Descriptor; NUM_RX_SLOTS]>>,
+);
+
+unsafe impl Sync for RxDescriptor {}
+
+impl RxDescriptor {
+    /// Initializes the RX descriptors and returns a mutable reference to them.
+    pub fn take(
+        &self,
+    ) -> Option<&'static mut [zynq7000_hal::eth::rx_descr::Descriptor; NUM_RX_SLOTS]> {
+        if RX_DESCR_TAKEN.swap(true, core::sync::atomic::Ordering::SeqCst) {
+            return None; // Already taken, return None
+        }
+        let descr = unsafe { &mut *self.0.get() };
+        descr.write([const { zynq7000_hal::eth::rx_descr::Descriptor::new() }; NUM_RX_SLOTS]);
+        Some(unsafe { descr.assume_init_mut() })
+    }
+}
+
+#[unsafe(link_section = ".uncached")]
+static RX_DESCRIPTORS: RxDescriptor = RxDescriptor(UnsafeCell::new(MaybeUninit::uninit()));
+
+#[repr(transparent)]
+pub struct TxDescriptor(
+    pub UnsafeCell<MaybeUninit<[zynq7000_hal::eth::tx_descr::Descriptor; NUM_TX_SLOTS]>>,
+);
+
+unsafe impl Sync for TxDescriptor {}
+
+impl TxDescriptor {
+    /// Initializes the TX descriptors and returns a mutable reference to them.
+    pub fn take(
+        &self,
+    ) -> Option<&'static mut [zynq7000_hal::eth::tx_descr::Descriptor; NUM_TX_SLOTS]> {
+        if TX_DESCR_TAKEN.swap(true, core::sync::atomic::Ordering::SeqCst) {
+            return None; // Already taken, return None
+        }
+        let descr = unsafe { &mut *self.0.get() };
+        descr.write([const { zynq7000_hal::eth::tx_descr::Descriptor::new() }; NUM_TX_SLOTS]);
+        Some(unsafe { descr.assume_init_mut() })
+    }
+}
+
+#[unsafe(link_section = ".uncached")]
+static TX_DESCRIPTORS: TxDescriptor = TxDescriptor(UnsafeCell::new(MaybeUninit::uninit()));
+
+static ETH_RX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_RX_SLOTS]> =
+    static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_RX_SLOTS]);
+static ETH_TX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_TX_SLOTS]> =
+    static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_TX_SLOTS]);
+
+static ETH_ERR_QUEUE: embassy_sync::channel::Channel<
+    embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex,
+    InterruptResult,
+    8,
+> = embassy_sync::channel::Channel::new();
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum IpMode {
+    LinkDown,
+    AutoNegotiating,
+    AwaitingIpConfig,
+    StackReady,
+}
+
+/// Entry point (not called like a normal main function)
+#[unsafe(no_mangle)]
+pub extern "C" fn boot_core(cpu_id: u32) -> ! {
+    if cpu_id != 0 {
+        panic!("unexpected CPU ID {}", cpu_id);
+    }
+    main();
+}
+
+#[embassy_executor::task]
+async fn embassy_net_task(
+    mut runner: embassy_net::Runner<'static, zynq7000_hal::eth::embassy_net::Driver>,
+) -> ! {
+    runner.run().await
+}
+
+#[embassy_executor::task]
+async fn led_task(mut mio_led: Output) -> ! {
+    let mut ticker = Ticker::every(Duration::from_millis(200));
+    loop {
+        mio_led.toggle().unwrap();
+        ticker.next().await; // Wait for the next cycle of the ticker
+    }
+}
+
+#[embassy_executor::main]
+#[unsafe(export_name = "main")]
+async fn main(spawner: Spawner) -> ! {
+    // Configure the uncached memory region using the MMU.
+    mmu_l1_table_mut()
+        .update(UNCACHED_ADDR, SHAREABLE_DEVICE)
+        .expect("configuring uncached memory section failed");
+
+    // Enable PS-PL level shifters.
+    configure_level_shifter(LevelShifterConfig::EnableAll);
+    let dp = PsPeripherals::take().unwrap();
+    // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
+    let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
+    // Set up the global interrupt controller.
+    let mut gic = GicConfigurator::new_with_init(dp.gicc, dp.gicd);
+    gic.enable_all_interrupts();
+    gic.set_all_spi_interrupt_targets_cpu0();
+    gic.enable();
+    unsafe {
+        gic.enable_interrupts();
+    }
+    let mut gpio_pins = GpioPins::new(dp.gpio);
+
+    // Set up global timer counter and embassy time driver.
+    let gtc = Gtc::new(dp.gtc, clocks.arm_clocks());
+    zynq7000_embassy::init(clocks.arm_clocks(), gtc);
+
+    // Set up the UART, we are logging with it.
+    let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200)
+        .unwrap()
+        .0;
+    let mut uart = Uart::new_with_mio(
+        dp.uart_1,
+        UartConfig::new_with_clk_config(uart_clk_config),
+        (gpio_pins.mio.mio48, gpio_pins.mio.mio49),
+    )
+    .unwrap();
+    uart.write_all(INIT_STRING.as_bytes()).unwrap();
+    // Safety: We are not multi-threaded yet.
+    unsafe {
+        zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
+            uart,
+            log::LevelFilter::Trace,
+            false,
+        )
+    };
+
+    let boot_mode = BootMode::new();
+    info!("Boot mode: {:?}", boot_mode);
+
+    let rx_bufs = ETH_RX_BUFS.take();
+    let tx_bufs = ETH_TX_BUFS.take();
+
+    let rx_descr = RX_DESCRIPTORS.take().unwrap();
+    let tx_descr = TX_DESCRIPTORS.take().unwrap();
+    // Unwraps okay, list length is not 0
+    let mut rx_descr_ref =
+        zynq7000_hal::eth::rx_descr::DescriptorList::new(rx_descr.as_mut_slice()).unwrap();
+    // Create an unsafe copy for error handling.
+    // let rx_descr_copy_for_error_handling = unsafe { rx_descr_ref.clone_unchecked() };
+    let mut tx_descr_ref =
+        zynq7000_hal::eth::tx_descr::DescriptorList::new(tx_descr.as_mut_slice());
+    rx_descr_ref.init_with_aligned_bufs(rx_bufs.as_slice());
+    tx_descr_ref.init_or_reset();
+
+    // Unwrap okay, this is a valid peripheral.
+    let eth_ll = EthernetLowLevel::new(dp.eth_0).unwrap();
+    let mod_id = eth_ll.regs.read_module_id();
+    info!("Ethernet Module ID: {mod_id:?}");
+    assert_eq!(mod_id, 0x20118);
+
+    let (clk_divs, clk_errors) =
+        ClkDivCollection::calculate_for_rgmii_and_io_clock(clocks.io_clocks());
+    debug!(
+        "Calculated RGMII clock configuration: {:?}, errors (missmatch from ideal rate in hertz): {:?}",
+        clk_divs, clk_errors
+    );
+    // Unwrap okay, we use a standard clock config, and the clock config should never fail.
+    let eth_cfg = EthernetConfig::new(
+        zynq7000_hal::eth::ClkConfig::new(clk_divs.cfg_1000_mbps),
+        zynq7000_hal::eth::calculate_mdc_clk_div(clocks.arm_clocks()).unwrap(),
+        MAC_ADDRESS,
+    );
+    // Configures all the physical pins for ethernet operation and sets up the
+    // ethernet peripheral.
+    let mut eth = zynq7000_hal::eth::Ethernet::new_with_mio(
+        eth_ll,
+        eth_cfg,
+        gpio_pins.mio.mio16,
+        gpio_pins.mio.mio21,
+        (
+            gpio_pins.mio.mio17,
+            gpio_pins.mio.mio18,
+            gpio_pins.mio.mio19,
+            gpio_pins.mio.mio20,
+        ),
+        gpio_pins.mio.mio22,
+        gpio_pins.mio.mio27,
+        (
+            gpio_pins.mio.mio23,
+            gpio_pins.mio.mio24,
+            gpio_pins.mio.mio25,
+            gpio_pins.mio.mio26,
+        ),
+        Some((gpio_pins.mio.mio52, gpio_pins.mio.mio53)),
+    );
+
+    eth.set_rx_buf_descriptor_base_address(rx_descr_ref.base_addr());
+    eth.set_tx_buf_descriptor_base_address(tx_descr_ref.base_addr());
+    eth.start();
+    let (mut phy, phy_rev) =
+        zedboard::phy_marvell::Marvell88E1518Phy::new_autoprobe_addr(eth.mdio_mut())
+            .expect("could not auto-detect phy");
+    info!(
+        "Detected Marvell 88E1518 PHY with revision number: {:?}",
+        phy_rev
+    );
+    phy.reset();
+    phy.restart_auto_negotiation();
+
+    let driver = zynq7000_hal::eth::embassy_net::Driver::new(
+        &eth,
+        MAC_ADDRESS,
+        zynq7000_hal::eth::embassy_net::DescriptorsAndBuffers::new(
+            rx_descr_ref,
+            rx_bufs,
+            tx_descr_ref,
+            tx_bufs,
+        )
+        .unwrap(),
+    );
+    //let config = embassy_net::Config::dhcpv4(Default::default());
+    let config = embassy_net::Config::ipv4_static(StaticConfigV4 {
+        address: Ipv4Cidr::new(Ipv4Addr::new(192, 168, 179, 25), 24),
+        gateway: None,
+        dns_servers: Default::default(),
+    });
+    static RESOURCES: static_cell::StaticCell<embassy_net::StackResources<3>> =
+        static_cell::StaticCell::new();
+    let mut rng = rand::rngs::SmallRng::seed_from_u64(1);
+    let (stack, runner) = embassy_net::new(
+        driver,
+        config,
+        RESOURCES.init(embassy_net::StackResources::new()),
+        rng.next_u64(),
+    );
+    spawner.spawn(embassy_net_task(runner)).unwrap();
+
+    let mut mio_led = Output::new_for_mio(gpio_pins.mio.mio7, PinState::Low);
+
+    let mut _emio_leds: [Output; 8] = [
+        Output::new_for_emio(gpio_pins.emio.take(0).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(1).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(2).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(3).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(4).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(5).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(6).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(7).unwrap(), PinState::Low),
+    ];
+    let mut ip_mode = IpMode::LinkDown;
+    let mut transmitted_frames = 0;
+    let mut received_frames = 0;
+    let receiver = ETH_ERR_QUEUE.receiver();
+    loop {
+        while let Ok(msg) = receiver.try_receive() {
+            info!("Received interrupt result: {msg:?}");
+        }
+        let sent_frames_since_last = eth.ll().regs.statistics().read_tx_count();
+        if sent_frames_since_last > 0 {
+            transmitted_frames += sent_frames_since_last;
+            info!("Frame sent count: {transmitted_frames}");
+        }
+        let received_frames_since_last = eth.ll().regs.statistics().read_rx_count();
+        if received_frames_since_last > 0 {
+            received_frames += received_frames_since_last;
+            info!("Frame received count: {received_frames}");
+        }
+
+        match ip_mode {
+            // Assuming that auto-negotiation is performed automatically.
+            IpMode::LinkDown => {
+                mio_led.set_low();
+                zynq7000_hal::eth::embassy_net::update_link_state(
+                    embassy_net::driver::LinkState::Down,
+                );
+                ip_mode = IpMode::AutoNegotiating;
+            }
+            IpMode::AutoNegotiating => {
+                let status = phy.read_copper_status();
+                if status.auto_negotiation_complete() {
+                    let extended_status = phy.read_copper_specific_status_register_1();
+                    info!(
+                        "Auto-negotiation complete. Setting speed {:?} and duplex {:?}",
+                        extended_status.speed().as_zynq7000_eth_speed().unwrap(),
+                        extended_status.duplex().as_zynq7000_eth_duplex()
+                    );
+                    eth.configure_clock_and_speed_duplex(
+                        // If this has the reserved bits, what do we even do? For this example app,
+                        // I am going to assume this never happens..
+                        extended_status.speed().as_zynq7000_eth_speed().unwrap(),
+                        extended_status.duplex().as_zynq7000_eth_duplex(),
+                        &clk_divs,
+                    );
+                    zynq7000_hal::eth::embassy_net::update_link_state(
+                        embassy_net::driver::LinkState::Up,
+                    );
+                    ip_mode = IpMode::AwaitingIpConfig;
+                } else {
+                    Timer::after_millis(100).await;
+                }
+            }
+            IpMode::AwaitingIpConfig => {
+                if stack.is_config_up() {
+                    let network_config = stack.config_v4();
+                    info!("Network configuration is up. config: {network_config:?}!",);
+                    ip_mode = IpMode::StackReady;
+                    mio_led.set_high();
+                } else {
+                    Timer::after_millis(100).await;
+                }
+            }
+            IpMode::StackReady => {
+                // Then we can use it!
+                let status = phy.read_copper_status();
+                if status.copper_link_status() == LatchingLinkStatus::DownSinceLastRead {
+                    ip_mode = IpMode::LinkDown;
+                    continue;
+                }
+                Timer::after_millis(100).await;
+            }
+        }
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _irq_handler() {
+    let mut gic_helper = GicInterruptHelper::new();
+    let irq_info = gic_helper.acknowledge_interrupt();
+    match irq_info.interrupt() {
+        Interrupt::Sgi(_) => (),
+        Interrupt::Ppi(ppi_interrupt) => {
+            if ppi_interrupt == zynq7000_hal::gic::PpiInterrupt::GlobalTimer {
+                unsafe {
+                    zynq7000_embassy::on_interrupt();
+                }
+            }
+        }
+        Interrupt::Spi(spi_interrupt) => {
+            if spi_interrupt == zynq7000_hal::gic::SpiInterrupt::Eth0 {
+                let result = zynq7000_hal::eth::embassy_net::on_interrupt(
+                    zynq7000_hal::eth::EthernetId::Eth0,
+                );
+                if result.has_errors() {
+                    ETH_ERR_QUEUE.try_send(result).ok();
+                }
+            }
+        }
+        Interrupt::Invalid(_) => (),
+        Interrupt::Spurious => (),
+    }
+    gic_helper.end_of_interrupt(irq_info);
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _abort_handler() {
+    loop {
+        nop();
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _undefined_handler() {
+    loop {
+        nop();
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _prefetch_handler() {
+    loop {
+        nop();
+    }
+}
+
+/// Panic handler
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    error!("Panic: {info:?}");
+    loop {}
+}
+
+/*
+pub fn udp_tcp_test() {
+    let mut rx_buffer = [0; MTU];
+    let mut reception_buf = [0; MTU];
+    let mut tx_buffer = [0; MTU];
+    // For UDP, we can use a fixed size array.
+    let mut rx_meta: [icmp::PacketMetadata; 8] = [icmp::PacketMetadata::EMPTY; 8];
+    let mut tx_meta: [icmp::PacketMetadata; 8] = [icmp::PacketMetadata::EMPTY; 8];
+    let mut rx_meta: [udp::PacketMetadata; 8] = [udp::PacketMetadata::EMPTY; 8];
+    let mut tx_meta: [udp::PacketMetadata; 8] = [udp::PacketMetadata::EMPTY; 8];
+    // Now what? maybe UDP Server?
+    let mut socket = UdpSocket::new(
+        stack,
+        &mut rx_meta,
+        &mut rx_buffer,
+        &mut tx_meta,
+        &mut tx_buffer,
+    );
+
+    //socket.set_timeout(Some(embassy_time::Duration::from_secs(10)));
+
+    // You need to start a server on the host machine, for example: `nc -ul 9000`
+    let remote_endpoint = (Ipv4Addr::new(192, 168, 178, 105), 9000);
+    info!("connecting...");
+    socket.bind(0).unwrap();
+    let port = socket.endpoint().port;
+    //let r = socket.(remote_endpoint).await;
+    if let Err(e) = r {
+        info!("connect error: {e:?}");
+        Timer::after_secs(1).await;
+        continue;
+    }
+    info!("connected to port {port}!");
+    let mut sent_once = true;
+    loop {
+        if sent_once {
+            let r = socket.send_to(b"Hello\n", remote_endpoint).await;
+            if let Err(e) = r {
+                info!("write error: {e:?}");
+                break;
+            }
+            sent_once = false;
+        }
+        let received = socket.recv_from(&mut reception_buf).await;
+        log::info!("received: {received:?}");
+
+        Timer::after_secs(1).await;
+    }
+}
+*/

examples/zedboard/src/lib.rs

@@ -1,5 +1,6 @@
 #![no_std]
 use zynq7000_hal::time::Hertz;
+pub mod phy_marvell;
 
 // Define the clock frequency as a constant
-pub const PS_CLOCK_FREQUENCY: Hertz = Hertz::from_raw(33_333_300);
+pub const PS_CLOCK_FREQUENCY: Hertz = Hertz::from_raw(33_333_333);

examples/zedboard/src/phy_marvell.rs

@@ -0,0 +1,246 @@
+use arbitrary_int::{u2, u4, u5};
+
+#[derive(Clone, Debug)]
+pub struct PhyIdentifier {
+    pub oui: u32,
+    pub model: u8,
+    pub rev: u8,
+}
+
+// Organizational Unique Identifier for Marvell 88E1518 PHY
+pub const MARVELL_88E1518_OUI: u32 = 0x005043;
+pub const MARVELL_88E1518_MODELL_NUMBER: u8 = 0b011101;
+
+#[bitbybit::bitenum(u5, exhaustive = false)]
+pub enum MarvellRegistersPage0 {
+    CopperControl = 0,
+    CopperStatus = 1,
+    IdReg1 = 2,
+    IdReg2 = 3,
+    CopperSpecificStatus = 17,
+    PageSel = 22,
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperControlRegister {
+    #[bit(15, rw)]
+    copper_reset: bool,
+    #[bit(14, rw)]
+    loopback: bool,
+    #[bit(12, rw)]
+    auto_negotiation_enable: bool,
+    #[bit(11, rw)]
+    power_down: bool,
+    #[bit(10, rw)]
+    isolate: bool,
+    #[bit(9, rw)]
+    restart_auto_negotiation: bool,
+    /// 1: Full-duplex, 0: Half-duplex
+    #[bit(8, rw)]
+    copper_duplex_mode: bool,
+    #[bits([13, 6], rw)]
+    speed_selection: u2,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum LatchingLinkStatus {
+    Up = 1,
+    DownSinceLastRead = 0,
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperStatusRegister {
+    /// Always 0, the 100BASE-T4 protocol is not available on Marvell 88E15XX.
+    #[bit(15, r)]
+    p_100_base_t4: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(14, r)]
+    p_100_base_x_full_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(13, r)]
+    p_100_base_x_half_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(12, r)]
+    p_10_base_t_full_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(11, r)]
+    p_10_base_t_half_duplex: bool,
+    /// Always 0 for Marvell 88E15XX
+    #[bit(10, r)]
+    p_100_base_t2_full_duplex: bool,
+    /// Always 0 for Marvell 88E15XX
+    #[bit(9, r)]
+    p_100_base_t2_half_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(8, r)]
+    extended_status: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(6, r)]
+    mf_preamble_suppression: bool,
+    #[bit(5, r)]
+    auto_negotiation_complete: bool,
+    // Latching high register bit.
+    #[bit(4, r)]
+    copper_remote_fault: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(3, r)]
+    auto_negotation_ability: bool,
+    // Latching low register bit. For the current link status, this register should be read back
+    // to back, or the link real time register (17_0.10) should be read
+    #[bit(2, r)]
+    copper_link_status: LatchingLinkStatus,
+    // Latching high register bit.
+    #[bit(1, r)]
+    jabber_detect: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(0, r)]
+    extended_capabilities: bool,
+}
+
+#[bitbybit::bitenum(u2, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum PhySpeedBits {
+    Reserved = 0b11,
+    Mbps1000 = 0b10,
+    Mbps100 = 0b01,
+    Mbps10 = 0b00,
+}
+
+impl PhySpeedBits {
+    #[inline]
+    pub fn as_zynq7000_eth_speed(&self) -> Option<zynq7000_hal::eth::Speed> {
+        match self {
+            PhySpeedBits::Reserved => None,
+            PhySpeedBits::Mbps1000 => Some(zynq7000_hal::eth::Speed::Mbps1000),
+            PhySpeedBits::Mbps100 => Some(zynq7000_hal::eth::Speed::Mbps100),
+            PhySpeedBits::Mbps10 => Some(zynq7000_hal::eth::Speed::Mbps10),
+        }
+    }
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum PhyDuplexBit {
+    Full = 1,
+    Half = 0,
+}
+
+impl PhyDuplexBit {
+    #[inline]
+    pub fn as_zynq7000_eth_duplex(&self) -> zynq7000_hal::eth::Duplex {
+        match self {
+            PhyDuplexBit::Full => zynq7000_hal::eth::Duplex::Full,
+            PhyDuplexBit::Half => zynq7000_hal::eth::Duplex::Half,
+        }
+    }
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperSpecificStatusRegister {
+    #[bits(14..=15, r)]
+    speed: PhySpeedBits,
+    #[bit(13, r)]
+    duplex: PhyDuplexBit,
+    /// Latching high register bit.
+    #[bit(12, r)]
+    page_received: bool,
+    /// This is 1 when auto-negotiation is not enabled.
+    #[bit(11, r)]
+    speed_and_duplex_resolved: bool,
+    /// This is the real-time link status.
+    #[bit(10, r)]
+    copper_link: bool,
+    #[bit(9, r)]
+    transmit_pause_enabled: bool,
+    #[bit(8, r)]
+    received_pause_enabled: bool,
+    #[bit(6, r)]
+    mdi_crossover_status: bool,
+    #[bit(4, r)]
+    copper_energy_detect_status: bool,
+    #[bit(3, r)]
+    global_link_status: bool,
+    #[bit(1, r)]
+    polarity: bool,
+    #[bit(0, r)]
+    jabber: bool,
+}
+
+pub struct Marvell88E1518Phy {
+    mdio: zynq7000_hal::eth::mdio::Mdio,
+    addr: u5,
+}
+
+impl Marvell88E1518Phy {
+    pub fn new_autoprobe_addr(mdio: &mut zynq7000_hal::eth::mdio::Mdio) -> Option<(Self, u4)> {
+        for addr in 0..32 {
+            let phy_id_1 =
+                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg1.raw_value());
+            let phy_id_2 =
+                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg2.raw_value());
+            // PHY ID 1 contains bits 3 to 18 of the OUI in the goofy IEEE ordering scheme,
+            // which corresponds to bit \[21:6\] of the OUI.
+            // PHY ID 2 contains bits 19 to 24 which correspond to bits \[5:0\] of the OUI.
+            let oui = ((phy_id_1 as u32) << 6) | ((phy_id_2 >> 10) & 0b111111) as u32;
+            let model_number = ((phy_id_2 >> 4) & 0b111111) as u8;
+            let revision_number = u4::new((phy_id_2 & 0b1111) as u8);
+            if oui == MARVELL_88E1518_OUI && model_number == MARVELL_88E1518_MODELL_NUMBER {
+                return Some((
+                    Self {
+                        mdio: unsafe { mdio.clone() },
+                        addr: u5::new(addr),
+                    },
+                    revision_number,
+                ));
+            }
+        }
+        None
+    }
+
+    pub fn new(mdio: zynq7000_hal::eth::mdio::Mdio, addr: u5) -> Self {
+        Self { mdio, addr }
+    }
+
+    pub fn reset(&mut self) {
+        let mut ctrl = CopperControlRegister::new_with_raw_value(
+            self.mdio
+                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
+        );
+        ctrl.set_copper_reset(true);
+        self.mdio.write_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperControl.raw_value(),
+            ctrl.raw_value(),
+        );
+    }
+
+    pub fn restart_auto_negotiation(&mut self) {
+        let mut ctrl = CopperControlRegister::new_with_raw_value(
+            self.mdio
+                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
+        );
+        ctrl.set_auto_negotiation_enable(true);
+        ctrl.set_restart_auto_negotiation(true);
+        self.mdio.write_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperControl.raw_value(),
+            ctrl.raw_value(),
+        );
+    }
+
+    pub fn read_copper_status(&mut self) -> CopperStatusRegister {
+        let raw_value = self
+            .mdio
+            .read_blocking(self.addr, MarvellRegistersPage0::CopperStatus.raw_value());
+        CopperStatusRegister::new_with_raw_value(raw_value)
+    }
+
+    pub fn read_copper_specific_status_register_1(&mut self) -> CopperSpecificStatusRegister {
+        let raw_value = self.mdio.read_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperSpecificStatus.raw_value(),
+        );
+        CopperSpecificStatusRegister::new_with_raw_value(raw_value)
+    }
+}