Async SPI working

zynq7000/src/spi.rs

@@ -65,9 +65,9 @@ pub struct Config {
     master_ern: bool,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct Status {
+pub struct InterruptStatus {
     #[bit(6, rw)]
     tx_underflow: bool,
     #[bit(5, rw)]
@@ -77,7 +77,7 @@ pub struct Status {
     #[bit(3, rw)]
     tx_full: bool,
     #[bit(2, rw)]
-    tx_trig: bool,
+    tx_not_full: bool,
     #[bit(1, rw)]
     mode_fault: bool,
     /// Receiver overflow interrupt.
@@ -85,9 +85,9 @@ pub struct Status {
     rx_ovr: bool,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct InterruptRegWriteOnly {
+pub struct InterruptControl {
     #[bit(6, w)]
     tx_underflow: bool,
     #[bit(5, w)]
@@ -107,7 +107,7 @@ pub struct InterruptRegWriteOnly {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct InterruptRegReadOnly {
+pub struct InterruptMask {
     #[bit(6, r)]
     tx_underflow: bool,
     #[bit(5, r)]
@@ -162,16 +162,17 @@ pub struct DelayControl {
 #[repr(C)]
 pub struct Spi {
     cr: Config,
-    sr: Status,
+    #[mmio(PureRead, Write)]
+    isr: InterruptStatus,
     /// Interrupt Enable Register.
     #[mmio(Write)]
-    ier: InterruptRegWriteOnly,
+    ier: InterruptControl,
     /// Interrupt Disable Register.
     #[mmio(Write)]
-    idr: InterruptRegWriteOnly,
+    idr: InterruptControl,
     /// Interrupt Mask Register.
     #[mmio(PureRead)]
-    imr: InterruptRegReadOnly,
+    imr: InterruptMask,
     enable: u32,
     delay_control: DelayControl,
     #[mmio(Write)]