clean up a bit

zynq7000/Cargo.toml

@@ -12,6 +12,8 @@ categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
 derive-mmio = "0.2"
+bitbybit = "1.3"
+arbitrary-int = "1.3"
 # cortex-r
 # defmt = { version = "0.3", optional = true }
 # critical-section = { version = "1", optional = true }

zynq7000/src/lib.rs

@@ -1,73 +1,84 @@
 //! Rust peripheral acess crate to the AMD Zynq 7000 SoCs
 #![no_std]
 
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct MaskedOutput {
+    #[bits(16..=31, w)]
+    pub mask: u16,
+    #[bits(0..=15, rw)]
+    pub output: u16,
+}
+
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Gpio {
     /// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
-    xgpiops_data_lsw_offset: u32,
+    masked_out_0_lsw: MaskedOutput,
     /// Maskable output data (GPIO bank 0, MIO, upper 16 bits)
-    xgpiops_data_msw_offset: u32,
+    masked_out_0_msw: MaskedOutput,
     /// Maskable output data (GPIO bank 1, MIO, lower 16 bits)
-    mask_data_1_lsw: u32,
+    masked_out_1_lsw: MaskedOutput,
     /// Maskable output data (GPIO bank 1, MIO, upper 16 bits)
-    mask_data_1_msw: u32,
+    masked_out_1_msw: MaskedOutput,
     /// Maskable output data (GPIO bank 2, EMIO, lower 16 bits)
-    mask_data_2_lsw: u32,
+    masked_out_2_lsw: MaskedOutput,
     /// Maskable output data (GPIO bank 2, EMIO, upper 16 bits)
-    mask_data_2_msw: u32,
+    masked_out_2_msw: MaskedOutput,
     /// Maskable output data (GPIO bank 3, EMIO, lower 16 bits)
-    mask_data_3_lsw: u32,
+    masked_out_3_lsw: MaskedOutput,
     /// Maskable output data (GPIO bank 3, EMIO, upper 16 bits)
-    mask_data_3_msw: u32,
+    masked_out_3_msw: MaskedOutput,
+
     _reserved_0: [u32; 8],
+
     /// Output data (GPIO bank 0, MIO)
-    xgpiops_data_offset: u32,
+    out_0: u32,
     /// Output data (GPIO bank 1, MIO)
-    data_1: u32,
+    out_1: u32,
     /// Output data (GPIO bank 2, EMIO)
-    data_2: u32,
+    out_2: u32,
     /// Output data (GPIO bank 3, EMIO)
-    data_3: u32,
+    out_3: u32,
 
     _reserved_1: [u32; 4],
 
     /// Input data (GPIO bank 0, MIO)
-    data_0_ro: u32,
+    in_0: u32,
     /// Input data (GPIO bank 1, MIO)
-    data_1_ro: u32,
+    in_1: u32,
     /// Input data (GPIO bank 2, EMIO)
-    data_2_ro: u32,
+    in_2: u32,
     /// Input data (GPIO bank 3, EMIO)
-    data_3_ro: u32,
+    in_3: u32,
 
     _reserved_2: [u32; 101],
 
     /// Direction mode (GPIO bank 0, MIO)
-    xgpiops_dirm_offset: u32,
+    dirm_0: u32,
     /// Output enable (GPIO bank 0, MIO)
-    xgpiops_outen_offset: u32,
+    out_en_0: u32,
     /// Interrupt mask status (GPIO bank 0, MIO)
-    xgpiops_intmask_offset: u32,
+    int_mask_0: u32,
     /// Interrupt enable/unmask (GPIO bank 0, MIO)
-    xgpiops_inten_offset: u32,
+    int_en_0: u32,
     /// Interrupt disable/mask (GPIO bank 0, MIO)
-    xgpiops_intdis_offset: u32,
+    int_dis_0: u32,
     /// Interrupt status (GPIO bank 0, MIO)
-    xgpiops_intsts_offset: u32,
+    int_sts_0: u32,
     /// Interrupt type (GPIO bank 0, MIO)
-    xgpiops_inttype_offset: u32,
+    int_type_0: u32,
     /// Interrupt polarity (GPIO bank 0, MIO)
-    xgpiops_intpol_offset: u32,
+    int_pol_0: u32,
     /// Interrupt any edge sensitivity (GPIO bank 0, MIO)
-    xgpiops_intany_offset: u32,
+    int_any_0: u32,
 
     _reserved_3: [u32; 8],
 
     /// Direction mode (GPIO bank 1, MIO)
     dirm_1: u32,
     /// Output enable (GPIO bank 1, MIO)
-    outen_1: u32,
+    out_en_1: u32,
     /// Interrupt mask status (GPIO bank 1, MIO)
     int_mask_1: u32,
     /// Interrupt enable/unmask (GPIO bank 1, MIO)