clean up runners
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This commit is contained in:
8
justfile
8
justfile
@@ -35,3 +35,11 @@ docs-zynq:
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bootgen:
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bootgen:
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bootgen -arch zynq -image boot.bif -o boot.bin -w on
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bootgen -arch zynq -image boot.bif -o boot.bin -w on
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echo "Generated boot.bin at zynq-boot-image/staging"
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echo "Generated boot.bin at zynq-boot-image/staging"
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[no-cd]
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run binary:
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# Run the initialization script. It needs to be run inside the justfile directory.
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python3 {{justfile_directory()}}/scripts/zynq7000-init.py
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# Run the GDB debugger in GUI mode.
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gdb-multiarch -q -x {{justfile_directory()}}/zynq/gdb.gdb {{binary}} -tui
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@@ -1,20 +0,0 @@
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#!/bin/bash
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# Exit if no arguments are provided
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if [ "$#" -eq 0 ]; then
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echo "Error: No arguments provided."
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echo "Usage: run.sh <binary>"
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exit 1
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fi
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# Get the absolute path to the `scripts/` directory
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SCRIPT_DIR="$(cd -- "$(dirname -- "$0")" && pwd)"
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# Get the absolute path to the project root
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ROOT_DIR="$(cd "$SCRIPT_DIR/.." && pwd)"
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# Run the initialization script
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"$SCRIPT_DIR/zynq7000-init.py"
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# Run the GDB debugger in GUI mode.
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gdb-multiarch -q -x gdb.gdb "$@" -tui
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@@ -1,3 +0,0 @@
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#!/bin/bash
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cargo +stable test --target $(rustc -vV | grep host | cut -d ' ' -f2) -p zynq7000-hal
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cargo +stable test --target $(rustc -vV | grep host | cut -d ' ' -f2) -p zynq7000
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@@ -121,7 +121,9 @@ def main():
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bitstream = args.bit
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bitstream = args.bit
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init_tcl = args.init_tcl
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init_tcl = args.init_tcl
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xsct_script = Path(TCL_SCRIPT_NAME)
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# Get the script's directory
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script_dir = Path(__file__).resolve().parent
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xsct_script = script_dir / TCL_SCRIPT_NAME
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if not xsct_script.exists():
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if not xsct_script.exists():
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xsct_script = Path(os.path.join(SCRIPTS_DIR, TCL_SCRIPT_NAME))
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xsct_script = Path(os.path.join(SCRIPTS_DIR, TCL_SCRIPT_NAME))
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@@ -1,4 +1,6 @@
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[target.armv7a-none-eabihf]
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[target.armv7a-none-eabihf]
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runner = "just run"
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rustflags = [
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rustflags = [
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"-Ctarget-cpu=cortex-a9",
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"-Ctarget-cpu=cortex-a9",
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"-Ctarget-feature=+vfp3",
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"-Ctarget-feature=+vfp3",
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@@ -25,10 +25,6 @@ use zynq7000_hal::{
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};
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};
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use zynq7000_rt as _;
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use zynq7000_rt as _;
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use crate::ddr_cfg::DDRIOB_CONFIG_SET_ZEDBOARD;
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pub mod ddr_cfg;
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// PS clock input frequency.
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// PS clock input frequency.
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const PS_CLK: Hertz = Hertz::from_raw(33_333_333);
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const PS_CLK: Hertz = Hertz::from_raw(33_333_333);
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