start non-blocking SPI impl
This commit is contained in:
parent
7cfb8adcd0
commit
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GPG Key ID:
A649FB78196E3849
@ -129,7 +129,7 @@ async fn main(_spawner: Spawner) -> ! {
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assert_eq!(mod_id, spi::MODULE_ID);
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assert!(spi.sclk() <= Hertz::from_raw(10_000_000));
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let min_delay = (spi.sclk().raw() * 5) / 1_000_000_000;
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spi.configure_delays(
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spi.inner().configure_delays(
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DelayControl::builder()
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.with_inter_word_cs_deassert(0)
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.with_between_cs_assertion(0)
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@ -20,6 +20,7 @@ num_enum = { version = "0.7", default-features = false }
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embedded-hal-nb = "1"
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embedded-io = "0.6"
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embedded-hal = "1"
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embedded-hal-async = "1"
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delegate = "0.13"
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paste = "1"
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nb = "1"
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242
zynq7000-hal/src/spi/asynch.rs
Normal file
242
zynq7000-hal/src/spi/asynch.rs
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@ -0,0 +1,242 @@
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use core::{cell::RefCell, convert::Infallible, sync::atomic::AtomicBool};
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use critical_section::Mutex;
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use embassy_sync::waitqueue::AtomicWaker;
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use raw_slice::{RawBufSlice, RawBufSliceMut};
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use zynq7000::spi::InterruptStatus;
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use super::{Spi, SpiId, SpiLowLevel, FIFO_DEPTH};
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static WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
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static TRANSFER_CONTEXTS: [Mutex<RefCell<TransferContext>>; 2] =
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[const { Mutex::new(RefCell::new(TransferContext::new())) }; 2];
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// Completion flag. Kept outside of the context structure as an atomic to avoid
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// critical section.
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static DONE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
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pub fn on_interrupt(peripheral: SpiId) {
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let mut spi = unsafe { SpiLowLevel::steal(peripheral) };
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let idx = peripheral as usize;
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let imr = spi.read_imr();
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// IRQ is not related.
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if !imr.tx_trig() && !imr.tx_full() && !imr.tx_underflow() && !imr.rx_ovr() && !imr.rx_full() {
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return;
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}
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// Prevent spurious interrupts from messing with out logic here.
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spi.disable_interrupts();
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let isr = spi.read_isr();
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spi.clear_interrupts();
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let mut context = critical_section::with(|cs| {
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let context_ref = TRANSFER_CONTEXTS[idx].borrow(cs);
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*context_ref.borrow()
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});
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// No transfer active.
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if context.transfer_type.is_none() {
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return;
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}
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let transfer_type = context.transfer_type.unwrap();
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match transfer_type {
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TransferType::Read => {
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on_interrupt_read(idx, &mut context, &mut spi, isr);
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}
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TransferType::Write => todo!(),
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TransferType::Transfer => todo!(),
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TransferType::TransferInPlace => todo!(),
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}
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}
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fn on_interrupt_read(
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idx: usize,
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context: &mut TransferContext,
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spi: &mut SpiLowLevel,
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mut isr: InterruptStatus,
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) {
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let read_slice = unsafe { context.rx_slice.get_mut().unwrap() };
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let read_len = read_slice.len();
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// Read data from RX FIFO first.
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if isr.rx_full() {
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while context.rx_progress < read_slice.len() {
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read_slice[context.rx_progress] = spi.read_fifo_unchecked();
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context.rx_progress += 1;
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}
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} else if isr.rx_not_empty() {
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let trigger = spi.read_rx_not_empty_threshold();
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// Read data from RX FIFO first.
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while context.rx_progress < read_len && context.rx_progress < trigger as usize {
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read_slice[context.rx_progress] = spi.read_fifo_unchecked();
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context.rx_progress += 1;
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}
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}
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// The FIFO still needs to be pumped.
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if context.tx_progress < read_len {
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// Write dummy data to TX FIFO.
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while context.tx_progress < read_slice.len() && !isr.tx_full() {
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spi.write_fifo_unchecked(0);
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context.tx_progress += 1;
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isr = spi.read_isr();
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}
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}
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if context.rx_progress == context.tx_progress && context.rx_progress == read_len {
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// Write back updated context structure.
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critical_section::with(|cs| {
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let context_ref = TRANSFER_CONTEXTS[idx].borrow(cs);
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*context_ref.borrow_mut() = *context;
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});
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spi.set_rx_fifo_trigger(1).unwrap();
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spi.set_tx_fifo_trigger(1).unwrap();
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// Interrupts were already disabled and cleared.
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DONE[idx].store(true, core::sync::atomic::Ordering::Relaxed);
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WAKERS[idx].wake();
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} else {
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let new_trig_level = core::cmp::min(FIFO_DEPTH, read_len - context.rx_progress);
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spi.set_rx_fifo_trigger(new_trig_level as u32).unwrap();
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// Re-enable interrupts with the new RX FIFO trigger level.
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spi.enable_interrupts();
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}
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}
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#[derive(Debug, Clone, Copy)]
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pub enum TransferType {
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Read,
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Write,
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Transfer,
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TransferInPlace,
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}
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#[derive(Default, Debug, Copy, Clone)]
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pub struct TransferContext {
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transfer_type: Option<TransferType>,
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tx_progress: usize,
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rx_progress: usize,
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tx_slice: RawBufSlice,
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rx_slice: RawBufSliceMut,
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}
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#[allow(clippy::new_without_default)]
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impl TransferContext {
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pub const fn new() -> Self {
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Self {
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transfer_type: None,
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tx_progress: 0,
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rx_progress: 0,
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tx_slice: RawBufSlice::new_nulled(),
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rx_slice: RawBufSliceMut::new_nulled(),
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}
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}
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}
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pub struct SpiFuture {
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id: super::SpiId,
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}
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impl Future for SpiFuture {
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type Output = ();
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fn poll(
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self: core::pin::Pin<&mut Self>,
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cx: &mut core::task::Context<'_>,
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) -> core::task::Poll<Self::Output> {
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WAKERS[self.id as usize].register(cx.waker());
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if DONE[self.id as usize].swap(false, core::sync::atomic::Ordering::Relaxed) {
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critical_section::with(|cs| {
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let mut ctx = TRANSFER_CONTEXTS[self.id as usize].borrow(cs).borrow_mut();
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*ctx = TransferContext::default();
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});
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return core::task::Poll::Ready(());
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}
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core::task::Poll::Pending
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}
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}
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impl SpiFuture {
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async fn new_for_read(spi: &mut Spi, spi_id: SpiId, words: &mut [u8]) -> Self {
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if words.is_empty() {
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panic!("words length unexpectedly 0");
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}
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let idx = spi_id as usize;
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DONE[idx].store(false, core::sync::atomic::Ordering::Relaxed);
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spi.inner.disable_interrupts();
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let write_idx = core::cmp::min(super::FIFO_DEPTH, words.len());
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// Send dummy bytes.
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(0..write_idx).for_each(|_| {
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spi.inner.write_fifo_unchecked(0);
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});
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// This should never fail because it is never larger than the FIFO depth.
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spi.inner.set_rx_fifo_trigger(write_idx as u32).unwrap();
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// We want to fill the TX FIFO before it is completely empty. I am not sure whether
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// the default value of 1 ensures this because the TMR says that this interrupt is
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// triggered when the FIFO has less than threshold entries.
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if write_idx < super::FIFO_DEPTH {
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spi.inner.set_tx_fifo_trigger(2).unwrap();
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}
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// We assume that the slave select configuration was already performed, but we take
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// care of issuing a start if necessary.
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spi.issue_manual_start_for_manual_cfg();
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critical_section::with(|cs| {
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let context_ref = TRANSFER_CONTEXTS[idx].borrow(cs);
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let mut context = context_ref.borrow_mut();
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context.transfer_type = Some(TransferType::Read);
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unsafe {
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context.rx_slice.set(words);
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}
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context.tx_slice.set_null();
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context.tx_progress = write_idx;
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context.rx_progress = 0;
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spi.inner.clear_interrupts();
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spi.inner.enable_interrupts();
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});
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Self { id: spi_id }
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}
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}
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pub struct SpiAsync(pub Spi);
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impl SpiAsync {
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async fn read(&mut self, words: &mut [u8]) {
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if words.is_empty() {
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return;
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}
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let id = self.0.inner.id;
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let spi_fut = SpiFuture::new_for_read(&mut self.0, id, words);
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spi_fut.await;
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}
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async fn write(&mut self, words: &[u8]) {}
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async fn transfer(&mut self, read: &mut [u8], write: &[u8]) {}
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async fn transfer_in_place(&mut self, words: &mut [u8]) {}
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}
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impl embedded_hal_async::spi::ErrorType for SpiAsync {
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type Error = Infallible;
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}
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impl embedded_hal_async::spi::SpiBus for SpiAsync {
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async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
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self.read(words).await;
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Ok(())
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}
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async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.write(words).await;
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Ok(())
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}
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async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
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self.transfer(read, write).await;
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Ok(())
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}
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async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
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self.transfer_in_place(words).await;
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Ok(())
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}
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async fn flush(&mut self) -> Result<(), Self::Error> {
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Ok(())
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}
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}
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@ -13,18 +13,22 @@ use crate::gpio::{
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};
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use crate::{clocks::IoClocks, slcr::Slcr, time::Hertz};
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use arbitrary_int::{Number, u3, u4, u6};
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use arbitrary_int::{u3, u4, u6, Number};
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use embedded_hal::delay::DelayNs;
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pub use embedded_hal::spi::Mode;
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use embedded_hal::spi::{MODE_0, MODE_1, MODE_2, MODE_3, SpiBus as _};
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use embedded_hal::spi::{SpiBus as _, MODE_0, MODE_1, MODE_2, MODE_3};
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use zynq7000::slcr::reset::DualRefAndClockReset;
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use zynq7000::spi::{
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BaudDivSelect, DelayControl, FifoWrite, MmioSpi, SPI_0_BASE_ADDR, SPI_1_BASE_ADDR,
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BaudDivSelect, DelayControl, FifoWrite, InterruptControl, InterruptMask, InterruptStatus,
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MmioSpi, SPI_0_BASE_ADDR, SPI_1_BASE_ADDR,
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};
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pub const FIFO_DEPTH: usize = 128;
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pub const MODULE_ID: u32 = 0x90106;
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pub mod asynch;
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pub use asynch::*;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum SpiId {
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Spi0,
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@ -403,9 +407,181 @@ impl Config {
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}
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}
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pub struct SpiLowLevel {
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id: SpiId,
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regs: zynq7000::spi::MmioSpi<'static>,
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}
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impl SpiLowLevel {
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/// Steal the SPI low level helper.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub unsafe fn steal(id: SpiId) -> Self {
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let regs = unsafe {
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match id {
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SpiId::Spi0 => zynq7000::spi::Spi::new_mmio_fixed_0(),
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SpiId::Spi1 => zynq7000::spi::Spi::new_mmio_fixed_1(),
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}
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};
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Self { id, regs }
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}
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/// Select the peripheral chip select line.
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///
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/// This needs to be done before starting a transfer to select the correct peripheral chip
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/// select line.
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///
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/// The decoder bits logic is is based
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/// [on online documentation](https://www.realdigital.org/doc/3eb4f7a05e5003f2e0e6858a27a679bb?utm_source=chatgpt.com)
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/// because the TRM does not specify how decoding really works. This also only works if
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/// the external decoding was enabled via the [Config::enable_external_decoding] option.
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#[inline]
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pub fn select_hw_cs(&mut self, chip_select: ChipSelect) {
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self.regs.modify_cr(|mut val| {
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val.set_cs_raw(chip_select.raw_reg());
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val
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});
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}
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/// Re-configures the mode register.
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#[inline]
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pub fn configure_mode(&mut self, mode: Mode) {
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let (cpol, cpha) = match mode {
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MODE_0 => (false, false),
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MODE_1 => (false, true),
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MODE_2 => (true, false),
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MODE_3 => (true, true),
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};
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self.regs.modify_cr(|mut val| {
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val.set_cpha(cpha);
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val.set_cpha(cpol);
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val
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});
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}
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/// Re-configures the delay control register.
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#[inline]
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pub fn configure_delays(&mut self, config: DelayControl) {
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self.regs.write_delay_control(config)
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}
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/// No peripheral slave selection.
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#[inline]
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pub fn no_hw_cs(&mut self) {
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self.select_hw_cs(ChipSelect::None);
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}
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#[inline(always)]
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pub fn write_fifo_unchecked(&mut self, data: u8) {
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self.regs
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.write_txd(FifoWrite::new_with_raw_value(data as u32));
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}
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#[inline(always)]
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pub fn read_fifo_unchecked(&mut self) -> u8 {
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self.regs.read_rxd().data()
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}
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#[inline]
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pub fn issue_manual_start(&mut self) {
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self.regs.modify_cr(|mut val| {
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val.set_manual_start(true);
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val
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});
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}
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#[inline]
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pub fn read_isr(&self) -> InterruptStatus {
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self.regs.read_isr()
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}
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#[inline]
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pub fn read_imr(&self) -> InterruptMask {
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self.regs.read_imr()
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}
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#[inline]
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pub fn read_rx_not_empty_threshold(&self) -> u32 {
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self.regs.read_rx_trig()
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}
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#[inline]
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pub fn set_rx_fifo_trigger(&mut self, trigger: u32) -> Result<(), InvalidTriggerError> {
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if trigger > FIFO_DEPTH as u32 {
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return Err(InvalidTriggerError(trigger as usize));
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}
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self.regs.write_rx_trig(trigger.value());
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Ok(())
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}
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#[inline]
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pub fn set_tx_fifo_trigger(&mut self, trigger: u32) -> Result<(), InvalidTriggerError> {
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if trigger > FIFO_DEPTH as u32 {
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return Err(InvalidTriggerError(trigger as usize));
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}
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self.regs.write_tx_trig(trigger.value());
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Ok(())
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}
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/// This disables all interrupts relevant for non-blocking interrupt driven SPI operation
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/// in SPI master mode.
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#[inline]
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pub fn disable_interrupts(&mut self) {
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self.regs.write_idr(
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InterruptControl::builder()
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.with_tx_underflow(true)
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.with_rx_full(true)
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.with_rx_not_empty(true)
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.with_tx_full(false)
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.with_tx_trig(true)
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.with_mode_fault(false)
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.with_rx_ovr(true)
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.build(),
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);
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}
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/// This enables all interrupts relevant for non-blocking interrupt driven SPI operation
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/// in SPI master mode.
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#[inline]
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pub fn enable_interrupts(&mut self) {
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self.regs.write_ier(
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InterruptControl::builder()
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.with_tx_underflow(true)
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.with_rx_full(true)
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.with_rx_not_empty(true)
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.with_tx_full(false)
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.with_tx_trig(true)
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.with_mode_fault(false)
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.with_rx_ovr(true)
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.build(),
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);
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}
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/// This clears all interrupts relevant for non-blocking interrupt driven SPI operation
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/// in SPI master mode.
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#[inline]
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pub fn clear_interrupts(&mut self) {
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self.regs.write_isr(
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InterruptStatus::builder()
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.with_tx_underflow(true)
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.with_rx_full(true)
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.with_rx_not_empty(true)
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.with_tx_full(false)
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.with_tx_not_full(true)
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.with_mode_fault(false)
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.with_rx_ovr(true)
|
||||
.build(),
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
/// Blocking Driver for the PS SPI peripheral in master mode.
|
||||
pub struct Spi {
|
||||
regs: zynq7000::spi::MmioSpi<'static>,
|
||||
inner: SpiLowLevel,
|
||||
sclk: Hertz,
|
||||
config: Config,
|
||||
outstanding_rx: bool,
|
||||
@ -415,6 +591,10 @@ pub struct Spi {
|
||||
#[error("invalid SPI ID")]
|
||||
pub struct InvalidPsSpiError;
|
||||
|
||||
#[derive(Debug, thiserror::Error)]
|
||||
#[error("invalid trigger value {0}")]
|
||||
pub struct InvalidTriggerError(pub usize);
|
||||
|
||||
// TODO: Add and handle MUX config check.
|
||||
#[derive(Debug, thiserror::Error)]
|
||||
pub enum SpiConstructionError {
|
||||
@ -640,101 +820,43 @@ impl Spi {
|
||||
regs.write_enable(1);
|
||||
let sclk = clocks.spi_clk() / config.baud_div.div_value() as u32;
|
||||
Self {
|
||||
regs,
|
||||
inner: SpiLowLevel { regs, id },
|
||||
sclk,
|
||||
config,
|
||||
outstanding_rx: false,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn issue_manual_start_for_manual_cfg(&mut self) {
|
||||
if self.config.ss_config == SlaveSelectConfig::AutoWithManualStart
|
||||
|| self.config.ss_config == SlaveSelectConfig::ManualWithManualStart
|
||||
{
|
||||
self.inner.issue_manual_start();
|
||||
}
|
||||
}
|
||||
|
||||
/// Retrieve SCLK clock frequency currently configured for this SPI.
|
||||
#[inline]
|
||||
pub const fn sclk(&self) -> Hertz {
|
||||
self.sclk
|
||||
}
|
||||
|
||||
/// Retrieve inner low-level helper.
|
||||
#[inline]
|
||||
pub fn regs(&mut self) -> &mut MmioSpi<'static> {
|
||||
&mut self.regs
|
||||
}
|
||||
|
||||
/// Select the peripheral chip select line.
|
||||
///
|
||||
/// This needs to be done before starting a transfer to select the correct peripheral chip
|
||||
/// select line.
|
||||
///
|
||||
/// The decoder bits logic is is based
|
||||
/// [on online documentation](https://www.realdigital.org/doc/3eb4f7a05e5003f2e0e6858a27a679bb?utm_source=chatgpt.com)
|
||||
/// because the TRM does not specify how decoding really works. This also only works if
|
||||
/// the external decoding was enabled via the [Config::enable_external_decoding] option.
|
||||
#[inline]
|
||||
pub fn select_hw_cs(&mut self, chip_select: ChipSelect) {
|
||||
self.regs.modify_cr(|mut val| {
|
||||
val.set_cs_raw(chip_select.raw_reg());
|
||||
val
|
||||
});
|
||||
}
|
||||
|
||||
/// Re-configures the mode register.
|
||||
#[inline]
|
||||
pub fn configure_mode(&mut self, mode: Mode) {
|
||||
let (cpol, cpha) = match mode {
|
||||
MODE_0 => (false, false),
|
||||
MODE_1 => (false, true),
|
||||
MODE_2 => (true, false),
|
||||
MODE_3 => (true, true),
|
||||
};
|
||||
self.regs.modify_cr(|mut val| {
|
||||
val.set_cpha(cpha);
|
||||
val.set_cpha(cpol);
|
||||
val
|
||||
});
|
||||
}
|
||||
|
||||
/// Re-configures the delay control register.
|
||||
#[inline]
|
||||
pub fn configure_delays(&mut self, config: DelayControl) {
|
||||
self.regs.write_delay_control(config)
|
||||
}
|
||||
|
||||
/// No peripheral slave selection.
|
||||
#[inline]
|
||||
pub fn no_hw_cs(&mut self) {
|
||||
self.select_hw_cs(ChipSelect::None);
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn write_fifo_unchecked(&mut self, data: u8) {
|
||||
self.regs
|
||||
.write_txd(FifoWrite::new_with_raw_value(data as u32));
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
pub fn read_fifo_unchecked(&mut self) -> u8 {
|
||||
self.regs.read_rxd().data()
|
||||
pub const fn inner(&mut self) -> &mut SpiLowLevel {
|
||||
&mut self.inner
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn issue_manual_start(&mut self) {
|
||||
self.regs.modify_cr(|mut val| {
|
||||
val.set_manual_start(true);
|
||||
val
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn issue_manual_start_for_manual_cfg(&mut self) {
|
||||
if self.config.ss_config == SlaveSelectConfig::AutoWithManualStart
|
||||
|| self.config.ss_config == SlaveSelectConfig::ManualWithManualStart
|
||||
{
|
||||
self.issue_manual_start();
|
||||
}
|
||||
pub fn regs(&mut self) -> &mut MmioSpi<'static> {
|
||||
&mut self.inner.regs
|
||||
}
|
||||
|
||||
fn initial_fifo_fill(&mut self, words: &[u8]) -> usize {
|
||||
let write_len = core::cmp::min(FIFO_DEPTH, words.len());
|
||||
(0..write_len).for_each(|idx| {
|
||||
self.write_fifo_unchecked(words[idx]);
|
||||
self.inner.write_fifo_unchecked(words[idx]);
|
||||
});
|
||||
write_len
|
||||
}
|
||||
@ -744,7 +866,7 @@ impl Spi {
|
||||
// implementation for now.
|
||||
self.flush().unwrap();
|
||||
// Write this to 1 in any case to allow polling, defensive programming.
|
||||
self.regs.write_rx_trig(1);
|
||||
self.inner.regs.write_rx_trig(1);
|
||||
|
||||
// Fill the FIFO with initial data.
|
||||
let written = self.initial_fifo_fill(words);
|
||||
@ -769,12 +891,12 @@ impl embedded_hal::spi::SpiBus for Spi {
|
||||
// implementation for now.
|
||||
self.flush()?;
|
||||
// Write this to 1 in any case to allow polling, defensive programming.
|
||||
self.regs.write_rx_trig(1);
|
||||
self.regs().write_rx_trig(1);
|
||||
|
||||
let mut write_idx = core::cmp::min(FIFO_DEPTH, words.len());
|
||||
// Send dummy bytes.
|
||||
(0..write_idx).for_each(|_| {
|
||||
self.write_fifo_unchecked(0);
|
||||
self.inner.write_fifo_unchecked(0);
|
||||
});
|
||||
|
||||
// We assume that the slave select configuration was already performed, but we take
|
||||
@ -783,14 +905,14 @@ impl embedded_hal::spi::SpiBus for Spi {
|
||||
|
||||
let mut read_idx = 0;
|
||||
while read_idx < words.len() {
|
||||
let status = self.regs.read_sr();
|
||||
let status = self.regs().read_isr();
|
||||
if status.rx_not_empty() {
|
||||
words[read_idx] = self.read_fifo_unchecked();
|
||||
words[read_idx] = self.inner.read_fifo_unchecked();
|
||||
read_idx += 1;
|
||||
}
|
||||
// Continue pumping the FIFO if necesary and possible.
|
||||
if write_idx < words.len() && !status.tx_full() {
|
||||
self.write_fifo_unchecked(0);
|
||||
self.inner.write_fifo_unchecked(0);
|
||||
write_idx += 1;
|
||||
}
|
||||
}
|
||||
@ -806,21 +928,21 @@ impl embedded_hal::spi::SpiBus for Spi {
|
||||
let mut read_idx = 0;
|
||||
|
||||
while written < words.len() {
|
||||
let status = self.regs.read_sr();
|
||||
let status = self.regs().read_isr();
|
||||
// We empty the FIFO to prevent it filling up completely, as long as we have to write
|
||||
// bytes
|
||||
if status.rx_not_empty() {
|
||||
self.read_fifo_unchecked();
|
||||
self.inner.read_fifo_unchecked();
|
||||
read_idx += 1;
|
||||
}
|
||||
if !status.tx_full() {
|
||||
self.write_fifo_unchecked(words[written]);
|
||||
self.inner.write_fifo_unchecked(words[written]);
|
||||
written += 1;
|
||||
}
|
||||
}
|
||||
// We exit once all bytes have been written, so some bytes to read might be outstanding.
|
||||
// We use the FIFO trigger mechanism to determine when we can read all the remaining bytes.
|
||||
self.regs.write_rx_trig((words.len() - read_idx) as u32);
|
||||
self.regs().write_rx_trig((words.len() - read_idx) as u32);
|
||||
self.outstanding_rx = true;
|
||||
Ok(())
|
||||
}
|
||||
@ -835,14 +957,14 @@ impl embedded_hal::spi::SpiBus for Spi {
|
||||
let mut writes_finished = write_idx == write.len();
|
||||
let mut reads_finished = false;
|
||||
while !writes_finished || !reads_finished {
|
||||
let status = self.regs.read_sr();
|
||||
let status = self.regs().read_isr();
|
||||
if status.rx_not_empty() && !reads_finished {
|
||||
read[read_idx] = self.read_fifo_unchecked();
|
||||
read[read_idx] = self.inner.read_fifo_unchecked();
|
||||
read_idx += 1;
|
||||
}
|
||||
|
||||
if !status.tx_full() && !writes_finished {
|
||||
self.write_fifo_unchecked(write[write_idx]);
|
||||
self.inner.write_fifo_unchecked(write[write_idx]);
|
||||
write_idx += 1;
|
||||
}
|
||||
writes_finished = write_idx == write.len();
|
||||
@ -862,14 +984,14 @@ impl embedded_hal::spi::SpiBus for Spi {
|
||||
let mut writes_finished = write_idx == words.len();
|
||||
let mut reads_finished = false;
|
||||
while !writes_finished || !reads_finished {
|
||||
let status = self.regs.read_sr();
|
||||
let status = self.inner.read_isr();
|
||||
if status.rx_not_empty() && !reads_finished {
|
||||
words[read_idx] = self.read_fifo_unchecked();
|
||||
words[read_idx] = self.inner.read_fifo_unchecked();
|
||||
read_idx += 1;
|
||||
}
|
||||
|
||||
if !status.tx_full() && !writes_finished {
|
||||
self.write_fifo_unchecked(words[write_idx]);
|
||||
self.inner.write_fifo_unchecked(words[write_idx]);
|
||||
write_idx += 1;
|
||||
}
|
||||
writes_finished = write_idx == words.len();
|
||||
@ -879,16 +1001,17 @@ impl embedded_hal::spi::SpiBus for Spi {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Blocking flush implementation.
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
if !self.outstanding_rx {
|
||||
return Ok(());
|
||||
}
|
||||
let rx_trig = self.regs.read_rx_trig();
|
||||
while !self.regs.read_sr().rx_not_empty() {}
|
||||
let rx_trig = self.inner.read_rx_not_empty_threshold();
|
||||
while !self.inner.read_isr().rx_not_empty() {}
|
||||
(0..rx_trig).for_each(|_| {
|
||||
self.regs.read_rxd();
|
||||
self.inner.read_fifo_unchecked();
|
||||
});
|
||||
self.regs.write_rx_trig(1);
|
||||
self.inner.set_rx_fifo_trigger(1).unwrap();
|
||||
self.outstanding_rx = false;
|
||||
Ok(())
|
||||
}
|
||||
@ -919,7 +1042,7 @@ impl<Delay: DelayNs> embedded_hal::spi::SpiDevice for SpiWithHwCs<Delay> {
|
||||
&mut self,
|
||||
operations: &mut [embedded_hal::spi::Operation<'_, u8>],
|
||||
) -> Result<(), Self::Error> {
|
||||
self.spi.select_hw_cs(self.cs);
|
||||
self.spi.inner.select_hw_cs(self.cs);
|
||||
for op in operations {
|
||||
match op {
|
||||
embedded_hal::spi::Operation::Read(items) => {
|
||||
@ -940,7 +1063,7 @@ impl<Delay: DelayNs> embedded_hal::spi::SpiDevice for SpiWithHwCs<Delay> {
|
||||
}
|
||||
}
|
||||
self.spi.flush()?;
|
||||
self.spi.no_hw_cs();
|
||||
self.spi.inner.no_hw_cs();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
@ -6,6 +6,14 @@ use raw_slice::RawBufSlice;
|
||||
|
||||
use crate::uart::{FIFO_DEPTH, Tx, UartId};
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum TransferType {
|
||||
Read,
|
||||
Write,
|
||||
Transfer,
|
||||
TransferInPlace
|
||||
}
|
||||
|
||||
static UART_TX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
|
||||
static TX_CONTEXTS: [Mutex<RefCell<TxContext>>; 2] =
|
||||
[const { Mutex::new(RefCell::new(TxContext::new())) }; 2];
|
||||
@ -49,8 +57,8 @@ pub fn on_interrupt_tx(peripheral: UartId) {
|
||||
// Transfer is done.
|
||||
TX_DONE[idx].store(true, core::sync::atomic::Ordering::Relaxed);
|
||||
tx_with_irq.disable_interrupts();
|
||||
UART_TX_WAKERS[idx].wake();
|
||||
tx_with_irq.clear_interrupts();
|
||||
UART_TX_WAKERS[idx].wake();
|
||||
return;
|
||||
}
|
||||
// Safety: We documented that the user provided slice must outlive the future, so we convert
|
||||
@ -94,7 +102,7 @@ impl TxContext {
|
||||
}
|
||||
|
||||
pub struct TxFuture {
|
||||
uart_idx: UartId,
|
||||
id: UartId,
|
||||
}
|
||||
|
||||
impl TxFuture {
|
||||
@ -124,7 +132,7 @@ impl TxFuture {
|
||||
tx_with_irq.enable_interrupts();
|
||||
|
||||
Self {
|
||||
uart_idx: tx_with_irq.uart_idx(),
|
||||
id: tx_with_irq.uart_idx(),
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -136,10 +144,10 @@ impl Future for TxFuture {
|
||||
self: core::pin::Pin<&mut Self>,
|
||||
cx: &mut core::task::Context<'_>,
|
||||
) -> core::task::Poll<Self::Output> {
|
||||
UART_TX_WAKERS[self.uart_idx as usize].register(cx.waker());
|
||||
if TX_DONE[self.uart_idx as usize].swap(false, core::sync::atomic::Ordering::Relaxed) {
|
||||
UART_TX_WAKERS[self.id as usize].register(cx.waker());
|
||||
if TX_DONE[self.id as usize].swap(false, core::sync::atomic::Ordering::Relaxed) {
|
||||
let progress = critical_section::with(|cs| {
|
||||
let mut ctx = TX_CONTEXTS[self.uart_idx as usize].borrow(cs).borrow_mut();
|
||||
let mut ctx = TX_CONTEXTS[self.id as usize].borrow(cs).borrow_mut();
|
||||
ctx.slice.set_null();
|
||||
ctx.progress
|
||||
});
|
||||
@ -151,7 +159,7 @@ impl Future for TxFuture {
|
||||
|
||||
impl Drop for TxFuture {
|
||||
fn drop(&mut self) {
|
||||
let mut tx = unsafe { Tx::steal(self.uart_idx) };
|
||||
let mut tx = unsafe { Tx::steal(self.id) };
|
||||
tx.disable_interrupts();
|
||||
}
|
||||
}
|
||||
|
||||
@ -65,9 +65,9 @@ pub struct Config {
|
||||
master_ern: bool,
|
||||
}
|
||||
|
||||
#[bitbybit::bitfield(u32)]
|
||||
#[bitbybit::bitfield(u32, default = 0x0)]
|
||||
#[derive(Debug)]
|
||||
pub struct Status {
|
||||
pub struct InterruptStatus {
|
||||
#[bit(6, rw)]
|
||||
tx_underflow: bool,
|
||||
#[bit(5, rw)]
|
||||
@ -77,7 +77,7 @@ pub struct Status {
|
||||
#[bit(3, rw)]
|
||||
tx_full: bool,
|
||||
#[bit(2, rw)]
|
||||
tx_trig: bool,
|
||||
tx_not_full: bool,
|
||||
#[bit(1, rw)]
|
||||
mode_fault: bool,
|
||||
/// Receiver overflow interrupt.
|
||||
@ -85,9 +85,9 @@ pub struct Status {
|
||||
rx_ovr: bool,
|
||||
}
|
||||
|
||||
#[bitbybit::bitfield(u32)]
|
||||
#[bitbybit::bitfield(u32, default = 0x0)]
|
||||
#[derive(Debug)]
|
||||
pub struct InterruptRegWriteOnly {
|
||||
pub struct InterruptControl {
|
||||
#[bit(6, w)]
|
||||
tx_underflow: bool,
|
||||
#[bit(5, w)]
|
||||
@ -107,7 +107,7 @@ pub struct InterruptRegWriteOnly {
|
||||
|
||||
#[bitbybit::bitfield(u32)]
|
||||
#[derive(Debug)]
|
||||
pub struct InterruptRegReadOnly {
|
||||
pub struct InterruptMask {
|
||||
#[bit(6, r)]
|
||||
tx_underflow: bool,
|
||||
#[bit(5, r)]
|
||||
@ -162,16 +162,17 @@ pub struct DelayControl {
|
||||
#[repr(C)]
|
||||
pub struct Spi {
|
||||
cr: Config,
|
||||
sr: Status,
|
||||
#[mmio(PureRead, Write)]
|
||||
isr: InterruptStatus,
|
||||
/// Interrupt Enable Register.
|
||||
#[mmio(Write)]
|
||||
ier: InterruptRegWriteOnly,
|
||||
ier: InterruptControl,
|
||||
/// Interrupt Disable Register.
|
||||
#[mmio(Write)]
|
||||
idr: InterruptRegWriteOnly,
|
||||
idr: InterruptControl,
|
||||
/// Interrupt Mask Register.
|
||||
#[mmio(PureRead)]
|
||||
imr: InterruptRegReadOnly,
|
||||
imr: InterruptMask,
|
||||
enable: u32,
|
||||
delay_control: DelayControl,
|
||||
#[mmio(Write)]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user