something wrong with the offset

zynq7000/src/slcr.rs

@@ -0,0 +1,237 @@
+//! System Level Control Registers (slcr)
+
+const SLCR_BASE_ADDR: usize = 0xF8000000;
+const CLOCK_CONTROL_OFFSET: usize = 0x100;
+const RESET_BLOCK_OFFSET: usize = 0x200;
+
+#[derive(derive_mmio::Mmio)]
+#[repr(C)]
+pub struct FpgaClkCtrl {
+    clk_ctrl: u32,
+    thr_ctrl: u32,
+    thr_cnt: u32,
+    thr_status: u32,
+}
+
+static_assertions::const_assert_eq!(core::mem::size_of::<FpgaClkCtrl>(), 0x10);
+
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct ResetControl {
+    /// PS Software reset control
+    pss: u32,
+    ddr: u32,
+    /// Central interconnect reset control
+    topsw: u32,
+    dmac: u32,
+    usb: u32,
+    gem: u32,
+    sdio: u32,
+    spi: u32,
+    can: u32,
+    i2c: u32,
+    uart: u32,
+    gpio: u32,
+    lqspi: u32,
+    smc: u32,
+    ocm: u32,
+    _gap0: u32,
+    fpga: u32,
+    a9_cpu: u32,
+    _gap1: u32,
+    rs_awdt: u32,
+}
+
+impl ResetControl {
+    pub fn new_mmio_fixed() -> MmioResetControl<'static> {
+        MmioResetControl {
+            ptr: (SLCR_BASE_ADDR + RESET_BLOCK_OFFSET) as *mut ResetControl,
+            phantom: core::marker::PhantomData,
+        }
+    }
+
+    fn new_mmio(block: *mut ResetControl) -> MmioResetControl<'static> {
+        MmioResetControl {
+            ptr: block,
+            phantom: core::marker::PhantomData,
+        }
+    }
+}
+
+static_assertions::const_assert_eq!(core::mem::size_of::<ResetControl>(), 0x50);
+
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct ClockControl {
+    arm_pll: u32,
+    ddr_pll: u32,
+    io_pll: u32,
+    pll_status: u32,
+    arm_pll_cfg: u32,
+    ddr_pll_cfg: u32,
+    io_pll_cfg: u32,
+    _gap0: u32,
+    arm_clk_ctrl: u32,
+    ddr_clk_ctrl: u32,
+    dci_clk_ctrl: u32,
+    /// AMBA peripheral clock control
+    aper_clk_ctrl: u32,
+    usb_0_clk_ctrl: u32,
+    usb_1_clk_ctrl: u32,
+    gem_0_rclk_ctrl: u32,
+    gem_1_rclk_ctrl: u32,
+    gem_0_clk_ctrl: u32,
+    gem_1_clk_ctrl: u32,
+    smc_clk_ctrl: u32,
+    lqspi_clk_ctrl: u32,
+    sdio_clk_ctrl: u32,
+    uart_clk_ctrl: u32,
+    spi_clk_ctrl: u32,
+    can_clk_ctrl: u32,
+    can_mioclk_ctrl: u32,
+    dbg_clk_ctrl: u32,
+    pcap_clk_ctrl: u32,
+    topsw_clk_ctrl: u32,
+    #[mmio(inner)]
+    fpga_0_clk_ctrl: FpgaClkCtrl,
+    #[mmio(inner)]
+    fpga_1_clk_ctrl: FpgaClkCtrl,
+    #[mmio(inner)]
+    fpga_2_clk_ctrl: FpgaClkCtrl,
+    #[mmio(inner)]
+    fpga_3_clk_ctrl: FpgaClkCtrl,
+    _gap1: [u32; 5],
+    clk_621_true: u32,
+}
+
+impl ClockControl {
+    pub fn new_mmio_fixed() -> MmioClockControl<'static> {
+        MmioClockControl {
+            ptr: (SLCR_BASE_ADDR + CLOCK_CONTROL_OFFSET) as *mut ClockControl,
+            phantom: core::marker::PhantomData,
+        }
+    }
+
+    fn new_mmio(clk_ctrl: *mut ClockControl) -> MmioClockControl<'static> {
+        MmioClockControl {
+            ptr: clk_ctrl,
+            phantom: core::marker::PhantomData,
+        }
+    }
+}
+
+static_assertions::const_assert_eq!(core::mem::size_of::<ClockControl>(), 0xC8);
+
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct Slcr {
+    /// Secure configuration lock.
+    scl: u32,
+    /// SLCR write protection lock
+    lock: u32,
+    /// SLCR write protection unlock
+    unlock: u32,
+    /// SLCR write protection status
+    lock_status: u32,
+
+    _gap0: [u32; 60],
+
+    #[mmio(inner)]
+    clk_ctrl: ClockControl,
+
+    _gap1: [u32; 14],
+
+    #[mmio(inner)]
+    reset_ctrl: ResetControl,
+
+    _gap2: [u32; 2],
+
+    reboot_status: u32,
+    boot_mode: u32,
+
+    _gap3: [u32; 40],
+
+    apu_ctrl: u32,
+    wdt_clk_set: u32,
+
+    _gap4: [u32; 78],
+
+    tz_dma_ns: u32,
+    tz_dma_irq_ns: u32,
+    tz_dma_periph_ns: u32,
+
+    _gap5: [u32; 57],
+
+    pss_idcode: u32,
+
+    _gap6: [u32; 51],
+
+    ddr_urgent: u32,
+    _gap7: [u32; 2],
+    ddr_cal_start: u32,
+    _gap8: u32,
+    ddr_ref_start: u32,
+    ddr_cmd_status: u32,
+    ddr_urgent_sel: u32,
+    ddr_dfi_status: u32,
+
+    _gap9: [u32; 56],
+
+    mio_pins: [u32; 54],
+
+    _gap10: [u32; 11],
+
+    mio_loopback: u32,
+    _gap11: u32,
+    mio_mst_tri_0: u32,
+    mio_mst_tri_1: u32,
+    _gap12: [u32; 8],
+    sd_0_wp_cd_sel: u32,
+    sd_1_wp_cd_sel: u32,
+
+    _gap13: [u32; 51],
+
+    lvl_shftr_en: u32,
+
+    _gap14: [u32; 4],
+
+    ocm_cfg: u32,
+
+    _gap15: [u32; 66],
+
+    reserved: u32,
+
+    _gap16: [u32; 56],
+
+    gpiob_ctrl: u32,
+    gpiob_cfg_cmos18: u32,
+    gpiob_cfg_cmos25: u32,
+    gpiob_cfg_cmos33: u32,
+    _gap17: u32,
+    gpiob_cfg_hstl: u32,
+    gpiob_drvr_bias_ctrl: u32,
+
+    _gap18: [u32; 9],
+
+    ddriob_addr0: u32,
+    ddriob_addr1: u32,
+    ddriob_data0: u32,
+    ddriob_data1: u32,
+    ddriob_diff0: u32,
+    ddriob_diff1: u32,
+    ddriob_clock: u32,
+    ddriob_drive_slew_addr: u32,
+    ddriob_drive_slew_data: u32,
+    ddriob_drive_slew_diff: u32,
+    ddriob_drive_slew_clock: u32,
+    ddriob_ddr_ctrl: u32,
+    ddriob_dci_ctrl: u32,
+    ddriob_dci_status: u32,
+}
+
+//static_assertions::const_assert_eq!(core::mem::size_of::<Slcr>(), 0xB78);
+
+pub type SystemLevelControlRegisters = Slcr;