l2 cache init now done in user app

zynq7000/src/l2_cache.rs

@@ -1,4 +1,4 @@
-use arbitrary_int::{u4, u6};
+use arbitrary_int::{u2, u3, u4, u6};
 
 pub const L2C_BASE_ADDR: usize = 0xF8F0_2000;
 
@@ -40,6 +40,153 @@ pub struct CacheId {
     rtl_release: u6,
 }
 
+#[repr(transparent)]
+pub struct Control(u32);
+
+impl Control {
+    pub fn new_enabled() -> Self {
+        Self(0x1)
+    }
+
+    pub fn new_disabled() -> Self {
+        Self(0x0)
+    }
+
+    #[inline(always)]
+    pub fn enabled(&mut self) -> bool {
+        self.0 == 0x1
+    }
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+pub enum ReplacementPolicy {
+    PseudoRandomWithLfsr = 0,
+    RoundRobin = 1,
+}
+
+#[bitbybit::bitenum(u3, exhaustive = true)]
+#[derive(Default, Debug)]
+pub enum WaySize {
+    __Reserved0 = 0b000,
+    _16kB = 0b001,
+    _32kB = 0b010,
+    #[default]
+    _64kB = 0b011,
+    _128kB = 0b100,
+    _256kB = 0b101,
+    _512kB = 0b110,
+    __Reserved1 = 0b111,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Default, Debug)]
+pub enum Associativity {
+    #[default]
+    _8Way = 0,
+    _16Way = 1,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+pub struct AuxControl {
+    #[bit(30, rw)]
+    early_bresp_enable: bool,
+    #[bit(29, rw)]
+    isntruction_prefetch_enable: bool,
+    #[bit(28, rw)]
+    data_prefetch_enable: bool,
+    #[bit(27, rw)]
+    nonsec_interrupt_access_control: bool,
+    #[bit(26, rw)]
+    nonsec_lockdown_enable: bool,
+    #[bit(25, rw)]
+    cache_replace_policy: ReplacementPolicy,
+    #[bits(23..=24, rw)]
+    force_write_alloc: u2,
+    #[bit(22, rw)]
+    shared_attr_override: bool,
+    #[bit(21, rw)]
+    parity_enable: bool,
+    #[bit(20, rw)]
+    event_monitor_bus_enable: bool,
+    #[bits(17..=19, rw)]
+    way_size: WaySize,
+    #[bit(16, rw)]
+    associativity: Associativity,
+    #[bit(13, rw)]
+    shared_attribute_invalidate: bool,
+    #[bit(12, rw)]
+    exclusive_cache_config: bool,
+    #[bit(11, rw)]
+    store_buff_device_limitation_enable: bool,
+    #[bit(10, rw)]
+    high_priority_so_dev_reads: bool,
+    /// Disabled by default.
+    #[bit(0, rw)]
+    full_line_zero_enable: bool,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug, PartialEq, Eq)]
+pub struct LatencyConfig {
+    /// Latency is the numerical value + 1 cycles.
+    #[bits(8..=10, rw)]
+    write_access_latency: u3,
+    /// Latency is the numerical value + 1 cycles.
+    #[bits(4..=6, rw)]
+    read_access_latency: u3,
+    /// Latency is the numerical value + 1 cycles.
+    #[bits(0..=2, rw)]
+    setup_latency: u3,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct InterruptStatus {
+    #[bit(8, r)]
+    dec_error_l3: bool,
+    #[bit(7, r)]
+    slave_error_l3: bool,
+    #[bit(6, r)]
+    error_data_ram_read: bool,
+    #[bit(5, r)]
+    error_tag_ram_read: bool,
+    #[bit(4, r)]
+    error_data_ram_write: bool,
+    #[bit(3, r)]
+    error_tag_ram_write: bool,
+    #[bit(2, r)]
+    parity_error_data_ram_read: bool,
+    #[bit(1, r)]
+    parity_error_tag_ram_read: bool,
+    /// ECNTR
+    #[bit(0, r)]
+    event_counter_overflow_increment: bool,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct InterruptControl {
+    #[bit(8, w)]
+    dec_error_l3: bool,
+    #[bit(7, w)]
+    slave_error_l3: bool,
+    #[bit(6, w)]
+    error_data_ram_read: bool,
+    #[bit(5, w)]
+    error_tag_ram_read: bool,
+    #[bit(4, w)]
+    error_data_ram_write: bool,
+    #[bit(3, w)]
+    error_tag_ram_write: bool,
+    #[bit(2, w)]
+    parity_error_data_ram_read: bool,
+    #[bit(1, w)]
+    parity_error_tag_ram_read: bool,
+    /// ECNTR
+    #[bit(0, w)]
+    event_counter_overflow_increment: bool,
+}
+
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct L2Cache {
@@ -50,10 +197,10 @@ pub struct L2Cache {
 
     _reserved: [u32; 0x3E],
 
-    control: u32,
-    aux_control: u32,
-    tag_ram_control: u32,
-    data_ram_control: u32,
+    control: Control,
+    aux_control: AuxControl,
+    tag_ram_latency: LatencyConfig,
+    data_ram_latency: LatencyConfig,
 
     _reserved2: [u32; 0x3C],
 
@@ -64,11 +211,11 @@ pub struct L2Cache {
     event_counter_0: u32,
     interrupt_mask: u32,
     #[mmio(PureRead)]
-    interrupt_mask_status: u32,
+    interrupt_mask_status: InterruptStatus,
     #[mmio(PureRead)]
-    interrupt_raw_status: u32,
+    interrupt_raw_status: InterruptStatus,
     #[mmio(Write)]
-    interrupt_clear: u32,
+    interrupt_clear: InterruptControl,
 
     _reserved3: [u32; 0x143],
 

zynq7000/src/lib.rs

@@ -39,6 +39,7 @@ static PERIPHERALS_TAKEN: AtomicBool = AtomicBool::new(false);
 pub struct PsPeripherals {
     pub gicc: gic::MmioGicc<'static>,
     pub gicd: gic::MmioGicd<'static>,
+    pub l2c: l2_cache::MmioL2Cache<'static>,
     pub uart_0: uart::MmioUart<'static>,
     pub uart_1: uart::MmioUart<'static>,
     pub spi_0: spi::MmioSpi<'static>,
@@ -74,6 +75,7 @@ impl PsPeripherals {
             Self {
                 gicc: gic::Gicc::new_mmio_fixed(),
                 gicd: gic::Gicd::new_mmio_fixed(),
+                l2c: l2_cache::L2Cache::new_mmio_fixed(),
                 uart_0: uart::Uart::new_mmio_fixed_0(),
                 uart_1: uart::Uart::new_mmio_fixed_1(),
                 gtc: gtc::Gtc::new_mmio_fixed(),