getting closer
This commit is contained in:
@ -28,11 +28,7 @@ core::arch::global_asm!(
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.set EFUSEStatus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
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/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
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.if SIM_MODE == 1
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.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
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.else
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.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
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.endif
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.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
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@ -46,6 +42,8 @@ core::arch::global_asm!(
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.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
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.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
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.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
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.section .text.startup
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.align 0
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@ -110,19 +108,6 @@ initialize:
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bic r0, r0, #0x1 /* clear bit 0 */
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mcr p15, 0, r0, c1, c0, 0 /* write value back */
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#ifdef SHAREABLE_DDR
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/* Mark the entire DDR memory as shareable */
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ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
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ldr r0, =TblBase /* MMU Table address in memory */
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ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
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shareable_loop:
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str r2, [r0] /* write the entry to MMU table */
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add r0, r0, #0x4 /* next entry in the table */
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add r2, r2, #0x100000 /* next section */
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subs r3, r3, #1
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bge shareable_loop /* loop till 1G is covered */
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#endif
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mrs r0, cpsr /* get the current PSR */
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mvn r1, #0x1f /* set up the irq stack pointer */
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and r2, r1, r0
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@ -175,6 +160,8 @@ shareable_loop:
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msr cpsr, r2
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ldr r13,=SYS_stack /* SYS stack pointer */
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bl init_mmu_table
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/*set scu enable bit in scu*/
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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@ -184,8 +171,8 @@ shareable_loop:
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/* enable MMU and cache */
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ldr r0,=TblBase /* Load MMU translation table base */
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orr r0, r0, #0x5B /* Outer-cacheable, WB */
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mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
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/* orr r0, r0, #0x5B Outer-cacheable, WB */
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mcr p15, 0, r0, c2, c0, 0 /* TTB0 */
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mvn r0,#0 /* Load MMU domains -- all ones=manager */
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mcr p15,0,r0,c3,c0,0
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@ -1 +1,341 @@
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//! The overview of translation table memory attributes is described below.
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//!
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//!| | Memory Range | Definition in Translation Table |
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//!|-----------------------|-------------------------|-----------------------------------|
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//!| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
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//!| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
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//!| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
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//!| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
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//!| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
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//!| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
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//!| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
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//!| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
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//!| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
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//!| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
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//!| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
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//!| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
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//!| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
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//!
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//! For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB,
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//! region after DDR and before PL is marked as undefined/reserved in translation
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//! table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
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//! 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
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//! of 1 MB, it is not possible to define separate regions for them. For region
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//! 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
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//! granual size, it is not possible to define separate region for it.
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pub const OFFSET_DDR: usize = 0;
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pub const OFFSET_DDR_ALL_ACCESSIBLE: usize = 0x10_0000;
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pub const OFFSET_FPGA_SLAVE_0: usize = 0x4000_0000;
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pub const OFFSET_FPGA_SLAVE_1_START: usize = 0x8000_0000;
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pub const OFFSET_FPGA_SLAVE_1_END: usize = 0xC000_0000;
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pub const OFFSET_IO_PERIPHERALS_START: usize = 0xE000_0000;
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pub const OFFSET_IO_PERIPHERALS_END: usize = 0xE030_0000;
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pub const OFFSET_NAND_MEMORY: usize = 0xE100_0000;
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pub const OFFSET_NOR_MEMORY: usize = 0xE200_0000;
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pub const OFFSET_SRAM_MEMORY: usize = 0xE400_0000;
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pub const OFFSET_SMC_MEMORIES_END: usize = 0xE600_0000;
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/// 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
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/// 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
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/// 1MB, it is not possible to define separate regions for them.
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pub const OFFSET_AMBA_APB_START: usize = 0xF800_0000;
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pub const OFFSET_AMBA_APB_END: usize = 0xF900_0000;
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pub const OFFSET_QSPI_XIP_START: usize = 0xFC00_0000;
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pub const OFFSET_QSPI_XIP_END: usize = 0xFE00_0000;
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/// 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
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/// 1MB, it is not possible to define separate region for it
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pub const OFFSET_OCM_MAPPED_HIGH_START: usize = 0xFFF0_0000;
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pub const OFFSET_OCM_MAPPED_HIGH_END: u64 = 0x1_0000_0000;
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pub const MAX_DDR_SIZE: usize = 0x4000_0000;
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pub const ONE_MB: usize = 0x10_0000;
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/// First 1 MB of DDR has special treatment, access is dependant on SCU/OCM state.
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/// Refer to Zynq TRM UG585 p.106 for more details.
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pub const SEGMENTS_DDR_FULL_ACCESSIBLE: usize = (MAX_DDR_SIZE - ONE_MB) / ONE_MB;
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pub const SEGMENTS_FPGA_SLAVE: usize = (OFFSET_FPGA_SLAVE_1_START - OFFSET_FPGA_SLAVE_0) / ONE_MB;
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pub const SEGMENTS_UNASSIGNED_0: usize =
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(OFFSET_IO_PERIPHERALS_START - OFFSET_FPGA_SLAVE_1_END) / ONE_MB;
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pub const SEGMENTS_IO_PERIPHS: usize =
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(OFFSET_IO_PERIPHERALS_END - OFFSET_IO_PERIPHERALS_START) / ONE_MB;
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pub const SEGMENTS_NAND: usize = (OFFSET_NOR_MEMORY - OFFSET_NAND_MEMORY) / ONE_MB;
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pub const SEGMENTS_NOR: usize = (OFFSET_SRAM_MEMORY - OFFSET_NOR_MEMORY) / ONE_MB;
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pub const SEGMENTS_SRAM: usize = (OFFSET_SMC_MEMORIES_END - OFFSET_SRAM_MEMORY) / ONE_MB;
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pub const SEGMENTS_UNASSIGNED_1: usize = (OFFSET_AMBA_APB_START - OFFSET_SMC_MEMORIES_END) / ONE_MB;
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pub const SEGMENTS_AMBA_APB: usize = (OFFSET_AMBA_APB_END - OFFSET_AMBA_APB_START) / ONE_MB;
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pub const SEGMENTS_UNASSIGNED_2: usize = (OFFSET_QSPI_XIP_START - OFFSET_AMBA_APB_END) / ONE_MB;
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pub const SEGMENTS_QSPI_XIP: usize = (OFFSET_QSPI_XIP_END - OFFSET_QSPI_XIP_START) / ONE_MB;
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pub const SEGMENTS_UNASSIGNED_3: usize =
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(OFFSET_OCM_MAPPED_HIGH_START - OFFSET_QSPI_XIP_END) / ONE_MB;
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pub const SEGMENTS_OCM_MAPPED_HIGH: usize = ((OFFSET_OCM_MAPPED_HIGH_END
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- OFFSET_OCM_MAPPED_HIGH_START as u64)
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/ ONE_MB as u64) as usize;
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum AccessPermissions {
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PermissionFault = 0b000,
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PrivilegedOnly = 0b001,
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NoUserWrite = 0b010,
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FullAccess = 0b011,
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_Reserved1 = 0b100,
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PrivilegedReadOnly = 0b101,
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ReadOnly = 0b110,
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_Reserved2 = 0b111,
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}
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impl AccessPermissions {
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const fn ap(&self) -> u8 {
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(*self as u8) & 0b11
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}
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const fn apx(&self) -> bool {
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(*self as u8) > (AccessPermissions::FullAccess as u8)
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}
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum L1EntryType {
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/// Access generates an abort exception. Indicates an unmapped virtual address.
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Fault = 0b00,
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/// Entry points to a L2 translation table, allowing 1 MB of memory to be further divided
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PageTable = 0b01,
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/// Maps a 1 MB region to a physical address.
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Section = 0b10,
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/// Special 1MB section entry which requires 16 entries in the translation table.
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Supersection = 0b11,
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}
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/// 1 MB section translation entry, mapping a 1 MB region to a physical address.
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#[derive(Debug, Copy, Clone)]
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pub struct L1Section(u32);
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pub struct SectionAttributes {
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/// NG bit
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non_global: bool,
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/// Implementation defined bit.
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p_bit: bool,
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shareable: bool,
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/// AP bits
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access: AccessPermissions,
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/// Type EXtension bits. See Zynq 7000 TRM
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type_extensions: u8,
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domain: u8,
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/// xN bit.
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execute_never: bool,
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/// C bit
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cacheable: bool,
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/// B bit
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bufferable: bool,
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}
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impl L1Section {
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/// The physical base address. The uppermost 12 bits define which 1 MB of virtual address
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/// space are being accessed. They will be stored in the L1 section table. This address
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/// MUST be aligned to 1 MB. This code will panic if this is not the case.
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pub const fn new(phys_base: u32, section_attrs: SectionAttributes) -> Self {
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// Must be aligned to 1 MB
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if phys_base & 0x000F_FFFF != 0 {
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panic!("physical base address for L1 section must be aligned to 1 MB");
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}
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let higher_bits = phys_base >> 20;
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let raw = (higher_bits << 20)
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| ((section_attrs.non_global as u32) << 17)
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| ((section_attrs.shareable as u32) << 16)
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| ((section_attrs.access.apx() as u32) << 15)
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| ((section_attrs.type_extensions as u32) << 12)
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| ((section_attrs.access.ap() as u32) << 10)
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| ((section_attrs.p_bit as u32) << 9)
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| ((section_attrs.domain as u32) << 5)
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| ((section_attrs.execute_never as u32) << 4)
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| ((section_attrs.cacheable as u32) << 3)
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| ((section_attrs.bufferable as u32) << 2)
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| L1EntryType::Section as u32;
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L1Section(raw)
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}
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}
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const SECTION_ATTRS_DDR: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: true,
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access: AccessPermissions::FullAccess,
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type_extensions: 0b101,
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// Manager domain
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domain: 0b1111,
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execute_never: false,
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cacheable: false,
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bufferable: true,
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};
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const SECTION_ATTRS_FPGA_SLAVES: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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// Strongly ordered
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type_extensions: 0b000,
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domain: 0b0000,
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execute_never: false,
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cacheable: false,
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bufferable: false,
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};
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const SECTION_ATTRS_SHAREABLE_DEVICE: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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type_extensions: 0b000,
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domain: 0b0000,
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execute_never: false,
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cacheable: false,
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bufferable: true,
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};
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const SECTION_ATTRS_SRAM: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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type_extensions: 0b000,
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domain: 0b0000,
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execute_never: false,
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cacheable: true,
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bufferable: true,
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};
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const SECTION_ATTRS_QSPI_XIP: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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type_extensions: 0b000,
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domain: 0b0000,
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execute_never: false,
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cacheable: true,
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bufferable: false,
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};
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const SECTION_ATTRS_OCM_MAPPED_HIGH: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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type_extensions: 0b100,
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domain: 0b0000,
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execute_never: false,
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cacheable: true,
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bufferable: true,
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};
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const SECTION_ATTRS_UNASSIGNED_RESERVED: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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type_extensions: 0b000,
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domain: 0b0000,
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execute_never: false,
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cacheable: false,
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bufferable: false,
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};
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const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
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#[repr(C, align(16384))]
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pub struct L1Table([u32; NUM_L1_PAGE_TABLE_ENTRIES]);
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/// MMU Level 1 Page table.
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///
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/// 4096 entries, each covering 1MB
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///
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static mut MMU_L1_PAGE_TABLE: L1Table = L1Table([0; NUM_L1_PAGE_TABLE_ENTRIES]);
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#[unsafe(no_mangle)]
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pub unsafe extern "C" fn init_mmu_table() {
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let mut offset = 0;
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let mut addr = 0;
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unsafe {
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// The first entry (1 MB) is related to special DDR memory. See p.101 of the TMR.
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// We set is separtely to accomodate for future changes.
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MMU_L1_PAGE_TABLE.0[0] = L1Section::new(addr, SECTION_ATTRS_DDR).0;
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_DDR_FULL_ACCESSIBLE] {
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*entry = L1Section::new(addr, SECTION_ATTRS_DDR).0;
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addr += ONE_MB as u32;
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}
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offset += SEGMENTS_DDR_FULL_ACCESSIBLE;
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// 2 FPGA slaves.
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_FPGA_SLAVE * 2] {
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*entry = L1Section::new(addr, SECTION_ATTRS_FPGA_SLAVES).0;
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addr += ONE_MB as u32;
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}
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offset += 2 * SEGMENTS_FPGA_SLAVE;
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|
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_0] {
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*entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
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addr += ONE_MB as u32;
|
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}
|
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offset += SEGMENTS_UNASSIGNED_0;
|
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|
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_IO_PERIPHS] {
|
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*entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
|
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addr += ONE_MB as u32;
|
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}
|
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offset += SEGMENTS_IO_PERIPHS;
|
||||
|
||||
for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_NAND] {
|
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*entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
|
||||
addr += ONE_MB as u32;
|
||||
}
|
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offset += SEGMENTS_NAND;
|
||||
|
||||
for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_NOR] {
|
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*entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
|
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addr += ONE_MB as u32;
|
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}
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offset += SEGMENTS_NOR;
|
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|
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_SRAM] {
|
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*entry = L1Section::new(addr, SECTION_ATTRS_SRAM).0;
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addr += ONE_MB as u32;
|
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}
|
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offset += SEGMENTS_SRAM;
|
||||
|
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_1] {
|
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*entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
|
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addr += ONE_MB as u32;
|
||||
}
|
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offset += SEGMENTS_UNASSIGNED_1;
|
||||
|
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for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_AMBA_APB] {
|
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*entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
|
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addr += ONE_MB as u32;
|
||||
}
|
||||
offset += SEGMENTS_AMBA_APB;
|
||||
|
||||
for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_2] {
|
||||
*entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
|
||||
addr += ONE_MB as u32;
|
||||
}
|
||||
offset += SEGMENTS_UNASSIGNED_2;
|
||||
|
||||
for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_QSPI_XIP] {
|
||||
*entry = L1Section::new(addr, SECTION_ATTRS_QSPI_XIP).0;
|
||||
addr += ONE_MB as u32;
|
||||
}
|
||||
offset += SEGMENTS_QSPI_XIP;
|
||||
|
||||
for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_3] {
|
||||
*entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
|
||||
addr += ONE_MB as u32;
|
||||
}
|
||||
offset += SEGMENTS_UNASSIGNED_3;
|
||||
|
||||
for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_OCM_MAPPED_HIGH] {
|
||||
*entry = L1Section::new(addr, SECTION_ATTRS_OCM_MAPPED_HIGH).0;
|
||||
addr += ONE_MB as u32;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user