first PAC experiments

zynq7000-rt/Cargo.toml

@@ -1,7 +1,14 @@
 [package]
 name = "zynq7000-rt"
 version = "0.1.0"
+authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2024"
+description = "Run-time support for the Zynq7000 family of SoCs for running bare-metal applications"
+homepage = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
+repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
+license = "MIT OR Apache-2.0"
+keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
+categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
 cortex-a-rt = { path = "../../cortex-r-a/cortex-a-rt", optional = true, features = ["vfp-dp"] }
@@ -9,4 +16,11 @@ cortex-r-a = { path = "../../cortex-r-a/cortex-r-a" }
 
 [features]
 default = ["rt"]
+tools = []
 rt = ["dep:cortex-a-rt"]
+
+[[bin]]
+name = "table-gen"
+path = "src/bin/table-gen.rs"
+# Prevents default build
+required-features = ["tools"]

zynq7000-rt/README.md

@@ -0,0 +1,15 @@
+Zynq7000 Run-Time Support
+========
+
+Startup code and minimal runtime for the AMD Zynq7000 SoC.
+
+## Re-Generating the MMU table
+
+The MMU table is a static flat map of 4096 entries for each 1 MB in the memory map.
+It was generated using the `table-gen` binary tool.
+
+You can re-run the tool using
+
+```sh
+cargo +stable --target <hostTarget> run --bin table-gen --no-default-features --features tools
+```

zynq7000-rt/src/bin/table-gen.rs

@@ -1,9 +1,8 @@
 use std::fs::File;
 use std::io::Write;
 use std::process::Command;
-
-use zynq7000_rt::mmu::ONE_MB;
 pub use zynq7000_rt::mmu::segments::*;
+use zynq7000_rt::mmu::ONE_MB;
 
 fn main() {
     let file_path = "src/mmu_table.rs";

zynq7000-rt/src/lib.rs

@@ -5,6 +5,7 @@
 #![no_std]
 
 pub mod mmu;
+#[cfg(feature = "rt")]
 mod mmu_table;
 #[cfg(feature = "rt")]
 pub mod rt;

zynq7000-rt/src/mmu.rs

@@ -165,6 +165,7 @@ pub mod section_attrs {
 pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
 
 #[repr(C, align(16384))]
+#[cfg(feature = "rt")]
 pub struct L1Table(pub(crate) [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
 
 /// Load the MMU translation table base address into the MMU.