consistency changes, workflow fix

.github/workflows/ci.yml

@@ -11,7 +11,7 @@ jobs:
         with:
           components: rust-src
       # Copy config file for rustflags and to build core/alloc.
-      - run: cp .cargo/def-config.toml .cargo/config.toml
+      - run: cp .cargo/config.toml.template .cargo/config.toml
       - run: cargo check --target armv7a-none-eabihf -p zynq7000
       - run: cargo check --target armv7a-none-eabihf -p zynq7000-rt
 
@@ -43,5 +43,5 @@ jobs:
         with:
           components: clippy, rust-src
       # Copy config file for rustflags and to build core/alloc.
-      - run: cp .cargo/def-config.toml .cargo/config.toml
+      - run: cp .cargo/config.toml.template .cargo/config.toml
       - run: cargo clippy --target armv7a-none-eabihf -- -D warnings

Cargo.toml

@@ -2,21 +2,24 @@
 resolver = "3"
 members = [
   "zynq7000-rt",
+  "zynq7000-mmu",
   "zynq7000",
   "zynq7000-hal",
   "zynq7000-embassy",
+  "zynq7000-boot-image",
+
   "examples/simple",
   "examples/embassy",
   "examples/zedboard",
-  "zynq-mmu",
+
   "zedboard-fsbl",
   "zedboard-bsp",
-  "zynq-boot-image",
+  "zedboard-qspi-flasher",
-  "zedboard-qspi-flasher", "zynq-ps7init-extract",
 ]
 
 exclude = [
   "zynq-boot-image/tester",
+  "zynq7000-ps7init-extract",
 ]
 
 # cargo build/run --release

zedboard-fsbl/Cargo.toml

@@ -13,8 +13,8 @@ cortex-ar = "0.3"
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
+zynq7000-boot-image = { path = "../zynq7000-boot-image" }
 zedboard-bsp = { path = "../zedboard-bsp" }
-zynq-boot-image = { path = "../zynq-boot-image" }
 embedded-io = "0.7"
 embedded-hal = "1"
 fugit = "0.3"

zedboard-fsbl/src/main.rs

@@ -8,7 +8,7 @@ use cortex_ar::asm::nop;
 use embedded_io::Write as _;
 use log::{error, info};
 use zedboard_bsp::qspi_spansion::{self, QspiSpansionS25Fl256SLinearMode};
-use zynq_boot_image::DestinationDevice;
+use zynq7000_boot_image::DestinationDevice;
 use zynq7000_hal::priv_tim;
 use zynq7000_hal::{
     BootMode,
@@ -185,7 +185,7 @@ fn qspi_boot(mut qspi: QspiSpansionS25Fl256SLinearMode, _priv_tim: priv_tim::Cpu
     let mut boot_header_slice = unsafe {
         core::slice::from_raw_parts_mut(
             boot_bin_base_addr as *mut u8,
-            zynq_boot_image::FIXED_BOOT_HEADER_SIZE,
+            zynq7000_boot_image::FIXED_BOOT_HEADER_SIZE,
         )
     };
     let read_guard = qspi.read_guard();
@@ -194,12 +194,12 @@ fn qspi_boot(mut qspi: QspiSpansionS25Fl256SLinearMode, _priv_tim: priv_tim::Cpu
         core::ptr::copy_nonoverlapping(
             QspiSpansionS25Fl256SLinearMode::BASE_ADDR as *mut u8,
             boot_header_slice.as_mut_ptr(),
-            zynq_boot_image::FIXED_BOOT_HEADER_SIZE,
+            zynq7000_boot_image::FIXED_BOOT_HEADER_SIZE,
         );
     }
     drop(read_guard);
 
-    let boot_header = zynq_boot_image::BootHeader::new(boot_header_slice).unwrap();
+    let boot_header = zynq7000_boot_image::BootHeader::new(boot_header_slice).unwrap();
     let fsbl_offset = boot_header.source_offset();
     boot_header_slice =
         unsafe { core::slice::from_raw_parts_mut(boot_bin_base_addr as *mut u8, fsbl_offset) };
@@ -208,15 +208,15 @@ fn qspi_boot(mut qspi: QspiSpansionS25Fl256SLinearMode, _priv_tim: priv_tim::Cpu
     let read_guard = qspi.read_guard();
     unsafe {
         core::ptr::copy_nonoverlapping(
-            (QspiSpansionS25Fl256SLinearMode::BASE_ADDR + zynq_boot_image::FIXED_BOOT_HEADER_SIZE)
+            (QspiSpansionS25Fl256SLinearMode::BASE_ADDR
-                as *mut u8,
+                + zynq7000_boot_image::FIXED_BOOT_HEADER_SIZE) as *mut u8,
-            boot_header_slice[zynq_boot_image::FIXED_BOOT_HEADER_SIZE..].as_mut_ptr(),
+            boot_header_slice[zynq7000_boot_image::FIXED_BOOT_HEADER_SIZE..].as_mut_ptr(),
-            fsbl_offset - zynq_boot_image::FIXED_BOOT_HEADER_SIZE,
+            fsbl_offset - zynq7000_boot_image::FIXED_BOOT_HEADER_SIZE,
         );
     }
     drop(read_guard);
 
-    let boot_header = zynq_boot_image::BootHeader::new_unchecked(boot_header_slice);
+    let boot_header = zynq7000_boot_image::BootHeader::new_unchecked(boot_header_slice);
 
     let mut name_buf: [u8; 256] = [0; 256];
     let mut opt_jump_addr = None;

zedboard-qspi-flasher/Cargo.toml

@@ -8,7 +8,7 @@ cortex-ar = { version = "0.3" }
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
-zynq-boot-image = { path = "../zynq-boot-image" }
+zynq7000-boot-image = { path = "../zynq7000-boot-image" }
 zedboard-bsp = { path = "../zedboard-bsp" }
 embedded-io = "0.7"
 embedded-hal = "1"

zedboard-qspi-flasher/src/main.rs

@@ -9,7 +9,7 @@ use embedded_hal::{delay::DelayNs as _, digital::StatefulOutputPin as _};
 use embedded_io::Write as _;
 use log::{error, info};
 use zedboard_bsp::qspi_spansion;
-use zynq_boot_image::BootHeader;
+use zynq7000_boot_image::BootHeader;
 use zynq7000_hal::{
     BootMode, LevelShifterConfig, clocks, gpio, prelude::*, priv_tim, qspi, time::Hertz, uart,
 };

zynq7000-boot-image/Cargo.toml

@@ -1,5 +1,5 @@
 [package]
-name = "zynq-boot-image"
+name = "zynq7000-boot-image"
 version = "0.1.0"
 edition = "2024"
 

zynq7000-hal/Cargo.toml

@@ -13,7 +13,7 @@ categories = ["embedded", "no-std", "hardware-support"]
 [dependencies]
 cortex-ar = { version = "0.3" }
 zynq7000 = { path = "../zynq7000" }
-zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
+zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1.0" }
 
 static_assertions = "1.1"
 bitbybit = "1.4"

zynq7000-mmu/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
-name = "zynq-mmu"
+name = "zynq7000-mmu"
-description = "Zynq MMU structures"
+description = "Zynq7000 MMU structures"
 version = "0.1.0"
 edition = "2024"
 

zynq7000-ps7init-extract/Cargo.toml

@@ -1,5 +1,5 @@
 [package]
-name = "zynq-ps7init-extract"
+name = "zynq7000-ps7init-extract"
 version = "0.1.0"
 edition = "2024"
 

zynq7000-rt/Cargo.toml

@@ -14,11 +14,11 @@ categories = ["embedded", "no-std", "hardware-support"]
 cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
 cortex-ar = { version = "0.3" }
 arbitrary-int = "2"
-zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
+zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1.0" }
 
 [features]
 default = ["rt"]
-tools = ["zynq-mmu/tools"]
+tools = ["zynq7000-mmu/tools"]
 rt = ["dep:cortex-a-rt"]
 
 [[bin]]

zynq7000-rt/src/bin/table-gen.rs

@@ -56,7 +56,7 @@ fn main() {
 
     writeln!(buf_writer, "use crate::mmu::section_attrs;").unwrap();
     writeln!(buf_writer, "use cortex_ar::mmu::L1Section;").unwrap();
-    writeln!(buf_writer, "use zynq_mmu::L1Table;").unwrap();
+    writeln!(buf_writer, "use zynq7000_mmu::L1Table;").unwrap();
     writeln!(buf_writer, "").unwrap();
 
     writeln!(buf_writer, "/// MMU Level 1 Page table.").unwrap();

zynq7000-rt/src/lib.rs

@@ -12,7 +12,7 @@
 pub use cortex_a_rt::*;
 
 #[cfg(feature = "rt")]
-use zynq_mmu::L1TableWrapper;
+use zynq7000_mmu::L1TableWrapper;
 
 pub mod mmu;
 #[cfg(feature = "rt")]

zynq7000-rt/src/mmu_table.rs

@@ -1,7 +1,7 @@
 //! This file was auto-generated by table-gen.rs
 use crate::mmu::section_attrs;
 use cortex_ar::mmu::L1Section;
-use zynq_mmu::L1Table;
+use zynq7000_mmu::L1Table;
 
 /// MMU Level 1 Page table.
 ///