rust/zynq7000-rs
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start adding GIC and GTP driver

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This commit is contained in:
Robin Müller
2025-03-04 07:55:48 +01:00
parent 7279c96f03
commit ae6e78e93b
10 changed files with 459 additions and 26 deletions
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11
zynq7000/src/pac/gic.rs
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@ -1,9 +1,9 @@
pub use crate::pac::mpcore::{GICC_BASE_ADDR, GICD_BASE_ADDR};
use arbitrary_int::{u10, u3, u5};
use arbitrary_int::{u3, u5, u10};
use static_assertions::const_assert_eq;
/// Distributor Control Register
#[bitbybit::bitfield(u32)]
#[bitbybit::bitfield(u32, default = 0x0)]
pub struct Dcr {
#[bit(1, rw)]
enable_non_secure: bool,
@ -75,7 +75,10 @@ pub struct Gicd {
pub ipr: [u32; 0x18],
_reserved_11: [u32; 0xE8],
/// Interrupt Processor Targes Registers
pub iptr: [u32; 0x18],
pub iptr_sgi: [u32; 0x4],
// TODO: Mark those read-only as soon as that works for arrays.
pub iptr_ppi: [u32; 0x4],
pub iptr_spi: [u32; 0x10],
// Those are split in the ARM documentation for some reason..
_reserved_12: [u32; 0xE8],
/// Interrupt Configuration Registers
@ -125,7 +128,7 @@ impl Gicd {
}
/// CPU interface control register.
#[bitbybit::bitfield(u32)]
#[bitbybit::bitfield(u32, default = 0x0)]
pub struct Icr {
#[bit(4, rw)]
sbpr: bool,