rename register blocks

zynq/zynq7000-hal/src/ddr/ll.rs

@@ -1,6 +1,6 @@
 //! Low-level DDR configuration module.
 use arbitrary_int::{prelude::*, u2, u3, u6};
-use zynq7000::ddrc::{MmioDdrController, regs::*};
+use zynq7000::ddrc::{MmioRegisters, regs::*};
 use zynq7000::slcr::{clocks::DciClockControl, ddriob::DdriobConfig};
 
 use crate::{clocks::DdrClocks, time::Hertz};
@@ -272,7 +272,7 @@ pub struct DdrcConfigSet {
 ///
 /// It does NOT take care of taking the DDR controller out of reset and polling for DDR
 /// configuration completion.
-pub fn configure_ddr_config(ddrc: &mut MmioDdrController<'static>, cfg_set: &DdrcConfigSet) {
+pub fn configure_ddr_config(ddrc: &mut MmioRegisters<'static>, cfg_set: &DdrcConfigSet) {
     ddrc.write_ddrc_ctrl(cfg_set.ctrl);
     // Write all configuration registers.
     ddrc.write_two_rank_cfg(cfg_set.two_rank);

zynq/zynq7000-hal/src/ddr/mod.rs

@@ -4,7 +4,7 @@
 //!
 //! - [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::u6;
-use zynq7000::ddrc::MmioDdrController;
+use zynq7000::ddrc::MmioRegisters;
 
 use crate::{
     BootMode,
@@ -48,7 +48,7 @@ impl DdrClockSetupConfig {
 /// This function consumes the DDRC register block once and thus provides a safe interface for DDR
 /// initialization.
 pub fn configure_ddr_for_ddr3(
-    mut ddrc_regs: MmioDdrController<'static>,
+    mut ddrc_regs: MmioRegisters<'static>,
     boot_mode: BootMode,
     clk_setup_cfg: DdrClockSetupConfig,
     ddriob_cfg: &DdriobConfigSet,