Ethernet and smoltcp/embassy-net support

examples/zedboard/src/bin/ethernet.rs

@@ -0,0 +1,299 @@
+#![no_std]
+#![no_main]
+
+use core::{mem::MaybeUninit, panic::PanicInfo};
+use cortex_ar::asm::nop;
+use embassy_executor::Spawner;
+use embassy_time::{Duration, Ticker};
+use embedded_hal::digital::StatefulOutputPin;
+use embedded_io::Write;
+use log::{error, info};
+use rand::{RngCore, SeedableRng};
+use zedboard::PS_CLOCK_FREQUENCY;
+use zynq7000_hal::{
+    BootMode,
+    clocks::Clocks,
+    configure_level_shifter,
+    eth::{AlignedBuffer, EthernetConfig, EthernetLowLevel},
+    gic::{GicConfigurator, GicInterruptHelper, Interrupt},
+    gpio::{GpioPins, Output, PinState},
+    gtc::Gtc,
+    uart::{ClkConfigRaw, Uart, UartConfig},
+};
+
+use zynq7000::{PsPeripherals, slcr::LevelShifterConfig};
+use zynq7000_rt::{self as _, mmu::section_attrs::SHAREABLE_DEVICE, mmu_l1_table_mut};
+
+const INIT_STRING: &str = "-- Zynq 7000 Zedboard Ethernet Example --\n\r";
+const MAC_ADDRESS: [u8; 6] = [0x01, 0x02, 0x03, 0x04, 0x05, 0x06];
+
+#[unsafe(link_section = ".uncached")]
+static RX_DESCRIPTORS: static_cell::ConstStaticCell<
+    MaybeUninit<[zynq7000_hal::eth::rx_descr::Descriptor; 32]>,
+> = static_cell::ConstStaticCell::new(MaybeUninit::uninit());
+
+#[unsafe(link_section = ".uncached")]
+static TX_DESCRIPTORS: static_cell::ConstStaticCell<
+    MaybeUninit<[zynq7000_hal::eth::tx_descr::Descriptor; 32]>,
+> = static_cell::ConstStaticCell::new(MaybeUninit::uninit());
+
+const NUM_RX_BUFS: usize = 32;
+const NUM_TX_BUFS: usize = 32;
+
+static ETH_RX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_RX_BUFS]> =
+    static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_RX_BUFS]);
+static ETH_TX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_TX_BUFS]> =
+    static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_TX_BUFS]);
+
+/// See memory.x file. 1 MB starting at this address will be configured as uncached memory using the
+/// MMU.
+const UNCACHED_ADDR: u32 = 0x4000000;
+
+/// Entry point (not called like a normal main function)
+#[unsafe(no_mangle)]
+pub extern "C" fn boot_core(cpu_id: u32) -> ! {
+    if cpu_id != 0 {
+        panic!("unexpected CPU ID {}", cpu_id);
+    }
+    main();
+}
+
+#[embassy_executor::task]
+async fn net_task(
+    mut runner: embassy_net::Runner<'static, zynq7000_hal::eth::embassy_net::Driver>,
+) -> ! {
+    runner.run().await
+}
+
+#[embassy_executor::main]
+#[unsafe(export_name = "main")]
+async fn main(spawner: Spawner) -> ! {
+    // Configure the uncached memory region using the MMU.
+    mmu_l1_table_mut()
+        .update(UNCACHED_ADDR, SHAREABLE_DEVICE)
+        .expect("configuring uncached memory section failed");
+
+    // Enable PS-PL level shifters.
+    configure_level_shifter(LevelShifterConfig::EnableAll);
+    let dp = PsPeripherals::take().unwrap();
+    // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
+    let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
+    // Set up the global interrupt controller.
+    let mut gic = GicConfigurator::new_with_init(dp.gicc, dp.gicd);
+    gic.enable_all_interrupts();
+    gic.set_all_spi_interrupt_targets_cpu0();
+    gic.enable();
+    unsafe {
+        gic.enable_interrupts();
+    }
+    let mut gpio_pins = GpioPins::new(dp.gpio);
+
+    // Set up global timer counter and embassy time driver.
+    let gtc = Gtc::new(dp.gtc, clocks.arm_clocks());
+    zynq7000_embassy::init(clocks.arm_clocks(), gtc);
+
+    // Set up the UART, we are logging with it.
+    let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200)
+        .unwrap()
+        .0;
+    let mut uart = Uart::new_with_mio(
+        dp.uart_1,
+        UartConfig::new_with_clk_config(uart_clk_config),
+        (gpio_pins.mio.mio48, gpio_pins.mio.mio49),
+    )
+    .unwrap();
+    uart.write_all(INIT_STRING.as_bytes()).unwrap();
+    // Safety: We are not multi-threaded yet.
+    unsafe {
+        zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
+            uart,
+            log::LevelFilter::Trace,
+            false,
+        )
+    };
+
+    let boot_mode = BootMode::new();
+    info!("Boot mode: {:?}", boot_mode);
+
+    let rx_bufs = ETH_RX_BUFS.take();
+    let tx_bufs = ETH_TX_BUFS.take();
+
+    let rx_descr = RX_DESCRIPTORS.take();
+    let tx_descr = TX_DESCRIPTORS.take();
+    rx_descr.write([const { zynq7000_hal::eth::rx_descr::Descriptor::new() }; 32]);
+    tx_descr.write([const { zynq7000_hal::eth::tx_descr::Descriptor::new() }; 32]);
+    let rx_descr_init = unsafe { rx_descr.assume_init_mut() };
+    let tx_descr_init = unsafe { tx_descr.assume_init_mut() };
+    // Unwraps okay, list length is not 0
+    let mut rx_descr_ref =
+        zynq7000_hal::eth::rx_descr::DescriptorList::new(rx_descr_init.as_mut_slice()).unwrap();
+    // Create an unsafe copy for error handling.
+    // let rx_descr_copy_for_error_handling = unsafe { rx_descr_ref.clone_unchecked() };
+    let mut tx_descr_ref =
+        zynq7000_hal::eth::tx_descr::DescriptorList::new(tx_descr_init.as_mut_slice());
+    rx_descr_ref.init_with_aligned_bufs(rx_bufs.as_slice());
+    tx_descr_ref.init_or_reset();
+
+    // Unwrap okay, this is a valid peripheral.
+    let eth_ll = EthernetLowLevel::new(dp.eth_0).unwrap();
+    let (clk_config, clk_error) = zynq7000_hal::eth::ClkConfig::calculate_for_rgmii(
+        clocks.io_clocks().ref_clk(),
+        zynq7000_hal::eth::Speed::Mbps1000,
+    );
+    info!(
+        "Calculated RGMII clock configuration: {:?}, error: {}",
+        clk_config, clk_error
+    );
+    // Unwrap okay, we use a standard clock config, and the clock config should never fail.
+    let eth_cfg = EthernetConfig::new(
+        clk_config,
+        zynq7000_hal::eth::calculate_mdc_clk_div(clocks.arm_clocks()).unwrap(),
+        MAC_ADDRESS,
+    );
+    // Configures all the physical pins for ethernet operation and sets up the
+    // ethernet peripheral.
+    let mut eth = zynq7000_hal::eth::Ethernet::new_with_mio(
+        eth_ll,
+        eth_cfg,
+        gpio_pins.mio.mio16,
+        gpio_pins.mio.mio21,
+        (
+            gpio_pins.mio.mio17,
+            gpio_pins.mio.mio18,
+            gpio_pins.mio.mio19,
+            gpio_pins.mio.mio20,
+        ),
+        gpio_pins.mio.mio22,
+        gpio_pins.mio.mio27,
+        (
+            gpio_pins.mio.mio23,
+            gpio_pins.mio.mio24,
+            gpio_pins.mio.mio25,
+            gpio_pins.mio.mio26,
+        ),
+        Some((gpio_pins.mio.mio52, gpio_pins.mio.mio53)),
+    );
+    eth.set_rx_buf_descriptor_base_address(rx_descr_ref.base_addr());
+    eth.set_tx_buf_descriptor_base_address(tx_descr_ref.base_addr());
+    let (mut phy, phy_rev) =
+        zedboard::phy_marvell::Marvell88E1518Phy::new_autoprobe_addr(eth.mdio_mut()).unwrap();
+    info!(
+        "Detected Marvell 88E1518 PHY with revision number: {:?}",
+        phy_rev
+    );
+    phy.reset();
+    phy.restart_auto_negotiation();
+
+    // TODO:
+    //  1. PHY configuration.
+    //  2. Interrupt handler for ethernet RX and TX. Need to pass the buffers and descriptors
+    //     to the interrupt handler.
+    //  3. Create embassy-net driver and schedule it.
+    //
+    let bufs = zynq7000_hal::eth::embassy_net::DescriptorsAndBuffers::new(
+        rx_descr_ref,
+        rx_bufs,
+        tx_descr_ref,
+        tx_bufs,
+    )
+    .unwrap();
+    let driver = zynq7000_hal::eth::embassy_net::Driver::new(&eth, MAC_ADDRESS, bufs);
+    let config = embassy_net::Config::dhcpv4(Default::default());
+    static RESOURCES: static_cell::StaticCell<embassy_net::StackResources<3>> =
+        static_cell::StaticCell::new();
+    let mut rng = rand::rngs::SmallRng::seed_from_u64(1);
+    let (stack, runner) = embassy_net::new(
+        driver,
+        config,
+        RESOURCES.init(embassy_net::StackResources::new()),
+        rng.next_u64(),
+    );
+    spawner.spawn(net_task(runner)).unwrap();
+
+    stack.wait_config_up().await;
+    let network_config = stack.config_v4();
+    info!(
+        "Network configuration is up: DHCP config: {:?}!",
+        network_config
+    );
+
+    let mut ticker = Ticker::every(Duration::from_millis(200));
+
+    let mut mio_led = Output::new_for_mio(gpio_pins.mio.mio7, PinState::Low);
+    let mut emio_leds: [Output; 8] = [
+        Output::new_for_emio(gpio_pins.emio.take(0).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(1).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(2).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(3).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(4).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(5).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(6).unwrap(), PinState::Low),
+        Output::new_for_emio(gpio_pins.emio.take(7).unwrap(), PinState::Low),
+    ];
+    loop {
+        mio_led.toggle().unwrap();
+
+        // Create a wave pattern for emio_leds
+        for led in emio_leds.iter_mut() {
+            led.toggle().unwrap();
+            ticker.next().await; // Wait for the next ticker for each toggle
+        }
+
+        ticker.next().await; // Wait for the next cycle of the ticker
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _irq_handler() {
+    let mut gic_helper = GicInterruptHelper::new();
+    let irq_info = gic_helper.acknowledge_interrupt();
+    match irq_info.interrupt() {
+        Interrupt::Sgi(_) => (),
+        Interrupt::Ppi(ppi_interrupt) => {
+            if ppi_interrupt == zynq7000_hal::gic::PpiInterrupt::GlobalTimer {
+                unsafe {
+                    zynq7000_embassy::on_interrupt();
+                }
+            }
+        }
+        Interrupt::Spi(spi_interrupt) => {
+            if spi_interrupt == zynq7000_hal::gic::SpiInterrupt::Eth0 {
+                let result = zynq7000_hal::eth::embassy_net::on_interrupt(
+                    zynq7000_hal::eth::EthernetId::Eth0,
+                );
+                // TODO: Send the result structure back to the main thread.
+            }
+        }
+        Interrupt::Invalid(_) => (),
+        Interrupt::Spurious => (),
+    }
+    gic_helper.end_of_interrupt(irq_info);
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _abort_handler() {
+    loop {
+        nop();
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _undefined_handler() {
+    loop {
+        nop();
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn _prefetch_handler() {
+    loop {
+        nop();
+    }
+}
+
+/// Panic handler
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    error!("Panic: {info:?}");
+    loop {}
+}

examples/zedboard/src/lib.rs

@@ -1,5 +1,6 @@
 #![no_std]
 use zynq7000_hal::time::Hertz;
+pub mod phy_marvell;
 
 // Define the clock frequency as a constant
 pub const PS_CLOCK_FREQUENCY: Hertz = Hertz::from_raw(33_333_300);

examples/zedboard/src/phy_marvell.rs

@@ -0,0 +1,217 @@
+use arbitrary_int::{u2, u4, u5};
+
+#[derive(Clone, Debug)]
+pub struct PhyIdentifier {
+    pub oui: u32,
+    pub model: u8,
+    pub rev: u8,
+}
+
+// Organizational Unique Identifier for Marvell 88E1518 PHY
+const MARVELL_88E1518_OUI: u32 = 0x005043;
+const MARVELL_88E1518_MODELL_NUMBER: u8 = 0b011101;
+
+#[bitbybit::bitenum(u5, exhaustive = false)]
+pub enum MarvellRegistersPage0 {
+    CopperControl = 0,
+    CopperStatus = 1,
+    IdReg1 = 2,
+    IdReg2 = 3,
+    CopperSpecificStatus = 17,
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperControlRegister {
+    #[bit(15, rw)]
+    copper_reset: bool,
+    #[bit(14, rw)]
+    loopback: bool,
+    #[bit(12, rw)]
+    auto_negotiation_enable: bool,
+    #[bit(11, rw)]
+    power_down: bool,
+    #[bit(10, rw)]
+    isolate: bool,
+    #[bit(9, rw)]
+    restart_auto_negotiation: bool,
+    /// 1: Full-duplex, 0: Half-duplex
+    #[bit(8, rw)]
+    copper_duplex_mode: bool,
+    #[bits([13, 6], rw)]
+    speed_selection: u2,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+pub enum LatchingLinkStatus {
+    Up = 1,
+    DownSinceLastRead = 0,
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperStatusRegister {
+    /// Always 0, the 100BASE-T4 protocol is not available on Marvell 88E15XX.
+    #[bit(15, r)]
+    p_100_base_t4: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(14, r)]
+    p_100_base_x_full_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(13, r)]
+    p_100_base_x_half_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(12, r)]
+    p_10_base_t_full_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(11, r)]
+    p_10_base_t_half_duplex: bool,
+    /// Always 0 for Marvell 88E15XX
+    #[bit(10, r)]
+    p_100_base_t2_full_duplex: bool,
+    /// Always 0 for Marvell 88E15XX
+    #[bit(9, r)]
+    p_100_base_t2_half_duplex: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(8, r)]
+    extended_status: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(6, r)]
+    mf_preamble_suppression: bool,
+    #[bit(5, r)]
+    auto_negotiation_complete: bool,
+    // Latching high register bit.
+    #[bit(4, r)]
+    copper_remote_fault: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(3, r)]
+    auto_negotation_ability: bool,
+    // Latching low register bit. For the current link status, this register should be read back
+    // to back, or the link real time register (17_0.10) should be read
+    #[bit(2, r)]
+    copper_link_status: LatchingLinkStatus,
+    // Latching high register bit.
+    #[bit(1, r)]
+    jabber_detect: bool,
+    /// Always 1 for Marvell 88E15XX
+    #[bit(0, r)]
+    extended_capabilities: bool,
+}
+
+#[bitbybit::bitenum(u2, exhaustive = true)]
+pub enum PhySpeedBits {
+    Reserved = 0b11,
+    Mbps1000 = 0b10,
+    Mbps100 = 0b01,
+    Mbps10 = 0b00,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+pub enum PhyDuplexBit {
+    Full = 1,
+    Half = 0,
+}
+
+#[bitbybit::bitfield(u16)]
+pub struct CopperSpecificStatusRegister {
+    #[bits(14..=15, r)]
+    speed: PhySpeedBits,
+    #[bit(13, r)]
+    duplex: PhyDuplexBit,
+    /// Latching high register bit.
+    #[bit(12, r)]
+    page_received: bool,
+    /// This is 1 when auto-negotiation is not enabled.
+    #[bit(11, r)]
+    speed_and_duplex_resolved: bool,
+    /// This is the real-time link status.
+    #[bit(10, r)]
+    copper_link: bool,
+    #[bit(9, r)]
+    transmit_pause_enabled: bool,
+    #[bit(8, r)]
+    received_pause_enabled: bool,
+    #[bit(6, r)]
+    mdi_crossover_status: bool,
+    #[bit(4, r)]
+    copper_energy_detect_status: bool,
+    #[bit(3, r)]
+    global_link_status: bool,
+    #[bit(1, r)]
+    polarity: bool,
+    #[bit(0, r)]
+    jabber: bool,
+}
+
+pub struct Marvell88E1518Phy {
+    mdio: zynq7000_hal::eth::mdio::Mdio,
+    addr: u5,
+}
+
+impl Marvell88E1518Phy {
+    pub fn new_autoprobe_addr(mdio: &mut zynq7000_hal::eth::mdio::Mdio) -> Option<(Self, u4)> {
+        for addr in 0..32 {
+            let phy_id_1 =
+                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg1.raw_value());
+            let phy_id_2 =
+                mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg2.raw_value());
+            let oui = (((phy_id_2 as u32) >> 10) << 19) | ((phy_id_1 as u32) << 3);
+            let model_number = ((phy_id_2 >> 4) & 0b111111) as u8;
+            let revision_number = u4::new((phy_id_2 & 0b1111) as u8);
+            if oui == MARVELL_88E1518_OUI && model_number == MARVELL_88E1518_MODELL_NUMBER {
+                return Some((
+                    Self {
+                        mdio: unsafe { mdio.clone() },
+                        addr: u5::new(addr),
+                    },
+                    revision_number,
+                ));
+            }
+        }
+        None
+    }
+
+    pub fn new(mdio: zynq7000_hal::eth::mdio::Mdio, addr: u5) -> Self {
+        Self { mdio, addr }
+    }
+
+    pub fn reset(&mut self) {
+        let mut ctrl = CopperControlRegister::new_with_raw_value(
+            self.mdio
+                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
+        );
+        ctrl.set_copper_reset(true);
+        self.mdio.write_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperControl.raw_value(),
+            ctrl.raw_value(),
+        );
+    }
+
+    pub fn restart_auto_negotiation(&mut self) {
+        let mut ctrl = CopperControlRegister::new_with_raw_value(
+            self.mdio
+                .read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
+        );
+        ctrl.set_auto_negotiation_enable(true);
+        ctrl.set_restart_auto_negotiation(true);
+        self.mdio.write_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperControl.raw_value(),
+            ctrl.raw_value(),
+        );
+    }
+
+    pub fn read_copper_status(&mut self) -> CopperStatusRegister {
+        let raw_value = self
+            .mdio
+            .read_blocking(self.addr, MarvellRegistersPage0::CopperStatus.raw_value());
+        CopperStatusRegister::new_with_raw_value(raw_value)
+    }
+
+    pub fn read_copper_specific_status_register_1(&mut self) -> CopperSpecificStatusRegister {
+        let raw_value = self.mdio.read_blocking(
+            self.addr,
+            MarvellRegistersPage0::CopperSpecificStatus.raw_value(),
+        );
+        CopperSpecificStatusRegister::new_with_raw_value(raw_value)
+    }
+}