continue fsbl

fsbl/src/main.rs

@@ -9,7 +9,7 @@ use log::error;
 use zynq7000_hal::{
     BootMode,
     clocks::pll::{PllConfig, configure_arm_pll, configure_ddr_pll, configure_io_pll},
-    ddr::configure_dci,
+    ddr::{calculate_dci_divisors, calibrate_iob_impedance_for_ddr3},
     time::Hertz,
 };
 use zynq7000_rt as _;
@@ -58,10 +58,11 @@ pub fn main() -> ! {
         PllConfig::new_from_target_clock(PS_CLK, DDR_CLK).unwrap(),
     );
     // Safety: Only done once here during start-up.
-    let ddr_clk = unsafe {
+    let ddr_clks = unsafe {
         zynq7000_hal::clocks::DdrClocks::new_with_2x_3x_init(DDR_CLK, u6::new(2), u6::new(3))
     };
-    configure_dci(&ddr_clk);
+    let dci_clk_cfg = calculate_dci_divisors(&ddr_clks);
+    calibrate_iob_impedance_for_ddr3(dci_clk_cfg, false);
 
     loop {
         cortex_ar::asm::nop();