continue

.gitignore

@@ -2,3 +2,4 @@
 /app.map
 /xsct-output.log
 /.vscode
+/Cargo.lock

Cargo.lock

@@ -1,160 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
-version = 4
-
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-
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- "quote",
- "syn",
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-
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- "cortex-ar",
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-
-[[package]]
-name = "zynq-examples"
-version = "0.1.0"
-dependencies = [
- "cortex-ar",
- "zynq7000",
- "zynq7000-rt",
-]
-
-[[package]]
-name = "zynq7000"
-version = "0.1.0"
-dependencies = [
- "arbitrary-int",
- "bitbybit",
- "derive-mmio",
-]
-
-[[package]]
-name = "zynq7000-rt"
-version = "0.1.0"
-dependencies = [
- "cortex-a-rt",
- "cortex-ar",
-]

zynq-examples/src/main.rs

@@ -19,7 +19,7 @@ pub extern "C" fn boot_core(cpu_id: u32) -> ! {
 
 #[unsafe(export_name = "main")]
 pub fn main() -> ! {
-    let mut gpio = unsafe { zynq7000::gpio::Gpio::new_mmio_fixed() };
+    let mut gpio = unsafe { zynq7000::gpio::Gpio::new_mmio() };
     gpio.modify_dirm_0(|v| v | ZEDBOARD_LED_MASK);
     gpio.modify_out_en_0(|v| v | ZEDBOARD_LED_MASK);
     loop {

zynq7000/Cargo.toml

@@ -11,7 +11,8 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-derive-mmio = "0.2"
+static_assertions = "1.1"
+derive-mmio = { path = "../../derive-mmio" }
 bitbybit = "1.3"
 arbitrary-int = "1.3"
 # cortex-r

zynq7000/src/gpio.rs

@@ -8,6 +8,7 @@ pub struct MaskedOutput {
 }
 
 #[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
 #[repr(C)]
 pub struct Gpio {
     /// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
@@ -134,6 +135,8 @@ pub struct Gpio {
     int_any_3: u32,
 }
 
+static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x2E8);
+
 impl Gpio {
     /// Create a new XGPIOPS GPIO MMIO instance.
     ///
@@ -142,7 +145,9 @@ impl Gpio {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub unsafe fn new_mmio_fixed() -> MmioGpio {
+    pub const unsafe fn new_mmio() -> MmioGpio {
-        unsafe { Self::new_mmio_at(0xE000A000) }
+        MmioGpio {
+            ptr: 0xE000A000 as *mut Gpio,
+        }
     }
 }

zynq7000/src/gtc.rs

@@ -0,0 +1,42 @@
+//! Global timer counter module.
+
+pub const GTC_BASE_ADDR: usize = super::MPCORE_BASE_ADDR + 0x0000_0200;
+
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct GlobalTimerCounter {
+    /// Count register 0, lower 32 bits
+    count_lower: u32,
+    /// Count register 1, upper 32 bits
+    count_upper: u32,
+    /// Control register
+    ctrl: u32,
+    /// Interrupt status register
+    isr: u32,
+    /// Comparator 0, lower 32 bits
+    comparator_lower: u32,
+    /// Comparator 1, upper 32 bits
+    comparator_upper: u32,
+    /// Auto-increment register
+    auto_increment: u32
+}
+
+pub type Gtc = GlobalTimerCounter;
+
+static_assertions::const_assert_eq!(core::mem::size_of::<Gtc>(), 0x1C);
+
+pub type MmioGtc = MmioGlobalTimerCounter;
+
+impl GlobalTimerCounter {
+    /// Create a new GTC MMIO instance.
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub const unsafe fn new_mmio() -> MmioGtc {
+        MmioGtc { ptr: GTC_BASE_ADDR as *mut Gtc }
+    }
+}

zynq7000/src/lib.rs

@@ -1,4 +1,8 @@
 //! Rust peripheral acess crate to the AMD Zynq 7000 SoCs
 #![no_std]
 
+pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000;
+
 pub mod gpio;
+pub mod uart;
+pub mod gtc;

zynq7000/src/sclr.rs

@@ -0,0 +1,11 @@
+//! System Level Control Registers (slcr)
+
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct Slcr {
+    scl: u32,
+}
+
+pub type SystemLevelControlRegisters = Slcr;
+

zynq7000/src/uart.rs

@@ -0,0 +1,66 @@
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct Uart {
+    /// Control Register
+    cr: u32,
+    /// Mode register
+    mr: u32,
+    /// Interrupt enable register
+    ier: u32,
+    /// Interrupt disable register
+    idr: u32,
+    /// Interrupt mask register
+    imr: u32,
+    /// Interrupt status register
+    isr: u32,
+    /// Baudgen register
+    baudgen: u32,
+    /// RX timeout register
+    rx_tout: u32,
+    /// RX FIFO trigger level register
+    rx_fifo_trigger: u32,
+    /// Modem control register
+    modem_cr: u32,
+    /// Modem status register
+    modem_sr: u32,
+    /// Channel status register
+    sr: u32,
+    /// FIFO register
+    fifo: u32,
+    /// Baud rate divider register
+    baud_rate_div: u32,
+    /// Flow control delay register
+    flow_delay: u32,
+
+    _reserved: [u32; 2],
+
+    /// TX fifo trigger level
+    tx_fifo_trigger: u32,
+}
+
+static_assertions::const_assert_eq!(core::mem::size_of::<Uart>(), 0x48);
+
+impl Uart {
+    /// Create a new UART MMIO instance for uart0 at address 0xE000_0000.
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub const unsafe fn new_mmio_0() -> MmioUart {
+        MmioUart { ptr: 0xE000_0000 as *mut Uart }
+    }
+
+    /// Create a new UART MMIO instance for uart1 at address 0xE000_1000.
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub const unsafe  fn new_mmio_1() -> MmioUart {
+        MmioUart { ptr: 0xE000_1000 as *mut Uart }
+    }
+}