continue
This commit is contained in:
parent
9a8f50d496
commit
d992a5a276
GPG Key ID:
A649FB78196E3849
1
.gitignore
vendored
1
.gitignore
vendored
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/app.map
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/xsct-output.log
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/.vscode
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/Cargo.lock
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160
Cargo.lock
generated
160
Cargo.lock
generated
@ -1,160 +0,0 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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version = 4
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[[package]]
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name = "arbitrary-int"
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version = "1.3.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "825297538d77367557b912770ca3083f778a196054b3ee63b22673c4a3cae0a5"
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[[package]]
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name = "arm-targets"
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version = "0.1.0"
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[[package]]
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name = "bitbybit"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "d317eeca82e7d88d606419a430590d83552bdceb899cb29904f63d694344b7fc"
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dependencies = [
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"arbitrary-int",
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"proc-macro2",
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"quote",
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"syn",
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]
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[[package]]
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name = "cortex-a-rt"
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version = "0.1.0"
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dependencies = [
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"arm-targets",
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"cortex-ar",
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"semihosting",
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]
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[[package]]
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name = "cortex-ar"
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version = "0.1.0"
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dependencies = [
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"arm-targets",
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"bitbybit",
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]
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[[package]]
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name = "derive-mmio"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"derive-mmio-macro",
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]
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[[package]]
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name = "derive-mmio-macro"
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version = "0.2.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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"proc-macro2",
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"rustversion",
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"syn",
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]
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[[package]]
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name = "proc-macro-error-attr2"
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"proc-macro-error-attr2",
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"proc-macro2",
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"quote",
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"syn",
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]
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[[package]]
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name = "proc-macro2"
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[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "rustversion"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "f7c45b9784283f1b2e7fb61b42047c2fd678ef0960d4f6f1eba131594cc369d4"
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[[package]]
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name = "semihosting"
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version = "0.1.19"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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name = "syn"
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dependencies = [
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"proc-macro2",
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"quote",
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"unicode-ident",
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]
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[[package]]
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name = "unicode-ident"
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version = "1.0.17"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "00e2473a93778eb0bad35909dff6a10d28e63f792f16ed15e404fca9d5eeedbe"
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[[package]]
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name = "zynq-examples"
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version = "0.1.0"
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dependencies = [
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"cortex-ar",
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"zynq7000",
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"zynq7000-rt",
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]
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[[package]]
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name = "zynq7000"
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version = "0.1.0"
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dependencies = [
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"arbitrary-int",
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"bitbybit",
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"derive-mmio",
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]
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[[package]]
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name = "zynq7000-rt"
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version = "0.1.0"
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dependencies = [
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"cortex-a-rt",
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"cortex-ar",
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]
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@ -19,7 +19,7 @@ pub extern "C" fn boot_core(cpu_id: u32) -> ! {
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#[unsafe(export_name = "main")]
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pub fn main() -> ! {
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let mut gpio = unsafe { zynq7000::gpio::Gpio::new_mmio_fixed() };
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let mut gpio = unsafe { zynq7000::gpio::Gpio::new_mmio() };
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gpio.modify_dirm_0(|v| v | ZEDBOARD_LED_MASK);
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gpio.modify_out_en_0(|v| v | ZEDBOARD_LED_MASK);
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loop {
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categories = ["embedded", "no-std", "hardware-support"]
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[dependencies]
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derive-mmio = "0.2"
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static_assertions = "1.1"
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derive-mmio = { path = "../../derive-mmio" }
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bitbybit = "1.3"
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arbitrary-int = "1.3"
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# cortex-r
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}
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#[derive(derive_mmio::Mmio)]
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#[mmio(no_ctors)]
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#[repr(C)]
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pub struct Gpio {
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/// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
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int_any_3: u32,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x2E8);
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impl Gpio {
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/// Create a new XGPIOPS GPIO MMIO instance.
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub unsafe fn new_mmio_fixed() -> MmioGpio {
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unsafe { Self::new_mmio_at(0xE000A000) }
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pub const unsafe fn new_mmio() -> MmioGpio {
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MmioGpio {
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ptr: 0xE000A000 as *mut Gpio,
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}
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}
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}
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42
zynq7000/src/gtc.rs
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42
zynq7000/src/gtc.rs
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//! Global timer counter module.
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pub const GTC_BASE_ADDR: usize = super::MPCORE_BASE_ADDR + 0x0000_0200;
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#[derive(derive_mmio::Mmio)]
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#[mmio(no_ctors)]
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#[repr(C)]
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pub struct GlobalTimerCounter {
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/// Count register 0, lower 32 bits
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count_lower: u32,
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/// Count register 1, upper 32 bits
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count_upper: u32,
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/// Control register
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ctrl: u32,
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/// Interrupt status register
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isr: u32,
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/// Comparator 0, lower 32 bits
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comparator_lower: u32,
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/// Comparator 1, upper 32 bits
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comparator_upper: u32,
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/// Auto-increment register
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auto_increment: u32
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}
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pub type Gtc = GlobalTimerCounter;
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static_assertions::const_assert_eq!(core::mem::size_of::<Gtc>(), 0x1C);
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pub type MmioGtc = MmioGlobalTimerCounter;
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impl GlobalTimerCounter {
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/// Create a new GTC MMIO instance.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio() -> MmioGtc {
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MmioGtc { ptr: GTC_BASE_ADDR as *mut Gtc }
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}
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}
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//! Rust peripheral acess crate to the AMD Zynq 7000 SoCs
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#![no_std]
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pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000;
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pub mod gpio;
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pub mod uart;
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pub mod gtc;
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11
zynq7000/src/sclr.rs
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11
zynq7000/src/sclr.rs
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//! System Level Control Registers (slcr)
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#[derive(derive_mmio::Mmio)]
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#[mmio(no_ctors)]
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#[repr(C)]
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pub struct Slcr {
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scl: u32,
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}
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pub type SystemLevelControlRegisters = Slcr;
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66
zynq7000/src/uart.rs
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66
zynq7000/src/uart.rs
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#[derive(derive_mmio::Mmio)]
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#[mmio(no_ctors)]
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#[repr(C)]
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pub struct Uart {
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/// Control Register
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cr: u32,
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/// Mode register
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mr: u32,
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/// Interrupt enable register
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ier: u32,
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/// Interrupt disable register
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idr: u32,
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/// Interrupt mask register
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imr: u32,
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/// Interrupt status register
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isr: u32,
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/// Baudgen register
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baudgen: u32,
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/// RX timeout register
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rx_tout: u32,
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/// RX FIFO trigger level register
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rx_fifo_trigger: u32,
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/// Modem control register
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modem_cr: u32,
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/// Modem status register
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modem_sr: u32,
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/// Channel status register
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sr: u32,
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/// FIFO register
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fifo: u32,
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/// Baud rate divider register
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baud_rate_div: u32,
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/// Flow control delay register
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flow_delay: u32,
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_reserved: [u32; 2],
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/// TX fifo trigger level
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tx_fifo_trigger: u32,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<Uart>(), 0x48);
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impl Uart {
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/// Create a new UART MMIO instance for uart0 at address 0xE000_0000.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_0() -> MmioUart {
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MmioUart { ptr: 0xE000_0000 as *mut Uart }
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}
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/// Create a new UART MMIO instance for uart1 at address 0xE000_1000.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_1() -> MmioUart {
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MmioUart { ptr: 0xE000_1000 as *mut Uart }
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}
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}
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