replaced cortex-ar and cortex-a-rt by aarch32-rt and aarch32-cpu

2025-10-28 00:05:27 +01:00
parent b394da69f3
commit efbd65f524
49 changed files with 129 additions and 207 deletions
--- a/zynq/examples/embassy/Cargo.toml
+++ b/zynq/examples/embassy/Cargo.toml
@@ -11,7 +11,7 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]

 [dependencies]
-cortex-ar = { version = "0.3", features = ["critical-section-single-core"] }
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
--- a/zynq/examples/embassy/memory.x
+++ b/zynq/examples/embassy/memory.x
@@ -7,6 +7,7 @@ MEMORY
  UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
 }

+REGION_ALIAS("VECTORS", CODE);
 REGION_ALIAS("DATA", CODE);

 SECTIONS
--- a/zynq/examples/embassy/src/bin/dht22-open-drain-pins.rs
+++ b/zynq/examples/embassy/src/bin/dht22-open-drain-pins.rs
@@ -3,7 +3,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Delay, Duration, Ticker};
 use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
--- a/zynq/examples/embassy/src/bin/embassy-hello.rs
+++ b/zynq/examples/embassy/src/bin/embassy-hello.rs
@@ -2,7 +2,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/examples/embassy/src/bin/logger-non-blocking.rs
+++ b/zynq/examples/embassy/src/bin/logger-non-blocking.rs
@@ -2,8 +2,8 @@
 #![no_std]
 #![no_main]

+use aarch32_cpu::asm::nop;
 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
@@ -70,6 +70,7 @@ async fn main(spawner: Spawner) -> ! {
    uart.write_all(b"-- Zynq 7000 Logging example --\n\r")
        .unwrap();
    uart.flush().unwrap();
+
    let (tx, _rx) = uart.split();
    let mut logger = TxAsync::new(tx);

--- a/zynq/examples/embassy/src/bin/pwm.rs
+++ b/zynq/examples/embassy/src/bin/pwm.rs
@@ -7,8 +7,8 @@
 #![no_std]
 #![no_main]

+use aarch32_cpu::asm::nop;
 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::{digital::StatefulOutputPin, pwm::SetDutyCycle};
@@ -80,8 +80,7 @@ async fn main(_spawner: Spawner) -> ! {
        (mio_pins.mio48, mio_pins.mio49),
    )
    .unwrap();
-    uart.write_all(b"-- Zynq 7000 Embassy Hello World --\n\r")
-        .unwrap();
+    uart.write_all(b"-- Zynq 7000 PWM example--\n\r").unwrap();
    // Safety: We are not multi-threaded yet.
    unsafe {
        zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
--- a/zynq/examples/embassy/src/main.rs
+++ b/zynq/examples/embassy/src/main.rs
@@ -2,7 +2,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/examples/simple/Cargo.toml
+++ b/zynq/examples/simple/Cargo.toml
@@ -9,7 +9,7 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
 license = "MIT OR Apache-2.0"

 [dependencies]
-cortex-ar = "0.3"
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3" }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
--- a/zynq/examples/simple/memory.x
+++ b/zynq/examples/simple/memory.x
@@ -7,6 +7,7 @@ MEMORY
  UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
 }

+REGION_ALIAS("VECTORS", CODE);
 REGION_ALIAS("DATA", CODE);

 SECTIONS
--- a/zynq/examples/simple/src/bin/blinky.rs
+++ b/zynq/examples/simple/src/bin/blinky.rs
@@ -2,8 +2,8 @@
 #![no_std]
 #![no_main]

+use aarch32_cpu::asm::nop;
 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
 use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
 use zynq7000::Peripherals;
 use zynq7000_hal::{
--- a/zynq/examples/simple/src/bin/gtc-ticks.rs
+++ b/zynq/examples/simple/src/bin/gtc-ticks.rs
@@ -2,8 +2,8 @@
 #![no_std]
 #![no_main]

+use aarch32_cpu::asm::nop;
 use core::{panic::PanicInfo, sync::atomic::AtomicU64};
-use cortex_ar::asm::nop;
 use embedded_hal::digital::StatefulOutputPin;
 use embedded_io::Write;
 use log::{error, info};
--- a/zynq/examples/simple/src/bin/logger.rs
+++ b/zynq/examples/simple/src/bin/logger.rs
@@ -2,8 +2,8 @@
 #![no_std]
 #![no_main]

+use aarch32_cpu::asm::nop;
 use core::{panic::PanicInfo, sync::atomic::AtomicU64};
-use cortex_ar::asm::nop;
 use embedded_hal::digital::StatefulOutputPin;
 use embedded_io::Write;
 use log::{error, info};
--- a/zynq/examples/simple/src/main.rs
+++ b/zynq/examples/simple/src/main.rs
@@ -2,8 +2,8 @@
 #![no_std]
 #![no_main]

+use aarch32_cpu::asm::nop;
 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
 use zynq7000_rt as _;

 /// Entry point (not called like a normal main function)
@@ -18,7 +18,7 @@ pub extern "C" fn boot_core(cpu_id: u32) -> ! {
 #[unsafe(export_name = "main")]
 pub fn main() -> ! {
    loop {
-        cortex_ar::asm::nop();
+        nop();
    }
 }

--- a/zynq/examples/zedboard/Cargo.toml
+++ b/zynq/examples/zedboard/Cargo.toml
@@ -11,7 +11,7 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]

 [dependencies]
-cortex-ar = "0.3"
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3" }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
--- a/zynq/examples/zedboard/memory.x
+++ b/zynq/examples/zedboard/memory.x
@@ -7,6 +7,7 @@ MEMORY
  UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
 }

+REGION_ALIAS("VECTORS", CODE);
 REGION_ALIAS("DATA", CODE);

 SECTIONS
--- a/zynq/examples/zedboard/src/bin/ethernet.rs
+++ b/zynq/examples/zedboard/src/bin/ethernet.rs
@@ -25,7 +25,7 @@
 #![no_main]

 use core::{net::Ipv4Addr, panic::PanicInfo};
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_net::{Ipv4Cidr, StaticConfigV4, tcp::TcpSocket, udp::UdpSocket};
 use embassy_time::{Duration, Timer};
--- a/zynq/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs
+++ b/zynq/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs
@@ -9,7 +9,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Delay, Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs
+++ b/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs
@@ -10,7 +10,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Delay, Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/examples/zedboard/src/bin/qspi.rs
+++ b/zynq/examples/zedboard/src/bin/qspi.rs
@@ -2,7 +2,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/examples/zedboard/src/bin/uart-blocking.rs
+++ b/zynq/examples/zedboard/src/bin/uart-blocking.rs
@@ -4,7 +4,7 @@
 use axi_uart16550::AxiUart16550;
 use axi_uartlite::AxiUartlite;
 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/examples/zedboard/src/bin/uart-non-blocking.rs
+++ b/zynq/examples/zedboard/src/bin/uart-non-blocking.rs
@@ -29,7 +29,7 @@ use alloc::format;
 use axi_uart16550::AxiUart16550;
 use axi_uartlite::AxiUartlite;
 use core::{cell::RefCell, panic::PanicInfo};
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use critical_section::Mutex;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
--- a/zynq/examples/zedboard/src/main.rs
+++ b/zynq/examples/zedboard/src/main.rs
@@ -2,7 +2,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
--- a/zynq/zedboard-fsbl/Cargo.toml
+++ b/zynq/zedboard-fsbl/Cargo.toml
@@ -9,7 +9,7 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
 license = "MIT OR Apache-2.0"

 [dependencies]
-cortex-ar = { version = "0.3", features = ["critical-section-single-core"] }
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
--- a/zynq/zedboard-fsbl/memory.x
+++ b/zynq/zedboard-fsbl/memory.x
@@ -9,6 +9,7 @@ MEMORY
  UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
 }

+REGION_ALIAS("VECTORS", CODE);
 REGION_ALIAS("DATA", CODE);

 SECTIONS
--- a/zynq/zedboard-fsbl/src/main.rs
+++ b/zynq/zedboard-fsbl/src/main.rs
@@ -10,7 +10,7 @@

 use arbitrary_int::u6;
 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embedded_io::Write as _;
 use log::{error, info};
 use zedboard_bsp::qspi_spansion::{self, QspiSpansionS25Fl256SLinearMode};
@@ -178,7 +178,7 @@ pub fn main() -> ! {
        qspi_boot(spansion_lqspi, priv_tim);
    }
    loop {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
    }
 }

@@ -321,10 +321,10 @@ fn qspi_boot(mut qspi: QspiSpansionS25Fl256SLinearMode, _priv_tim: priv_tim::Cpu

            // Some clean up and preparation for jumping to the user application.
            zynq7000_hal::cache::clean_and_invalidate_data_cache();
-            cortex_ar::register::TlbIAll::write();
-            cortex_ar::register::BpIAll::write();
-            cortex_ar::asm::dsb();
-            cortex_ar::asm::isb();
+            aarch32_cpu::register::TlbIAll::write();
+            aarch32_cpu::register::BpIAll::write();
+            aarch32_cpu::asm::dsb();
+            aarch32_cpu::asm::isb();

            let jump_func: extern "C" fn() -> ! = unsafe { core::mem::transmute(jump_addr) };
            jump_func();
--- a/zynq/zedboard-qspi-flasher/Cargo.toml
+++ b/zynq/zedboard-qspi-flasher/Cargo.toml
@@ -4,7 +4,7 @@ version = "0.1.0"
 edition = "2024"

 [dependencies]
-cortex-ar = { version = "0.3" }
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
--- a/zynq/zedboard-qspi-flasher/src/main.rs
+++ b/zynq/zedboard-qspi-flasher/src/main.rs
@@ -4,7 +4,7 @@
 #![no_main]

 use core::panic::PanicInfo;
-use cortex_ar::asm::nop;
+use aarch32_cpu::asm::nop;
 use embedded_hal::{delay::DelayNs as _, digital::StatefulOutputPin as _};
 use embedded_io::Write as _;
 use log::{error, info};
--- a/zynq/zynq7000-hal/Cargo.toml
+++ b/zynq/zynq7000-hal/Cargo.toml
@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "amd", "zynq7000", "bare-metal"]
 categories = ["embedded", "no-std", "hardware-support"]

 [dependencies]
-cortex-ar = { version = "0.3" }
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3" }
 zynq7000 = { path = "../zynq7000", version = "0.1" }
 zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }

--- a/zynq/zynq7000-hal/src/cache.rs
+++ b/zynq/zynq7000-hal/src/cache.rs
@@ -4,7 +4,7 @@
 //! L2 cache in the correct order. This module provides commonly required operations.
 use core::sync::atomic::compiler_fence;

-use cortex_ar::{
+use aarch32_cpu::{
    asm::dsb,
    cache::{
        clean_and_invalidate_data_cache_line_to_poc, clean_data_cache_line_to_poc,
@@ -28,7 +28,7 @@ pub fn clean_and_invalidate_l2c_line(l2c: &mut MmioRegisters<'static>, addr: u32
 pub fn clean_and_invalidate_data_cache() {
    dsb();

-    cortex_ar::cache::clean_l1_data_cache::<2, 5, 8>();
+    aarch32_cpu::cache::clean_l1_data_cache::<2, 5, 8>();
    dsb();

    // Clean all ways in L2 cache.
@@ -37,7 +37,7 @@ pub fn clean_and_invalidate_data_cache() {
    while l2c.read_cache_sync().busy() {}
    compiler_fence(core::sync::atomic::Ordering::SeqCst);

-    cortex_ar::cache::clean_and_invalidate_l1_data_cache::<2, 5, 8>();
+    aarch32_cpu::cache::clean_and_invalidate_l1_data_cache::<2, 5, 8>();
    dsb();
 }

--- a/zynq/zynq7000-hal/src/clocks/pll.rs
+++ b/zynq/zynq7000-hal/src/clocks/pll.rs
@@ -346,9 +346,7 @@ unsafe fn configure_pll_unchecked(
    while ((slcr.clk_ctrl().read_pll_status().raw_value() >> pll_type.bit_offset_pll_locked())
        & 0b1)
        != 1
-    {
-        cortex_ar::asm::nop();
-    }
+    {}

    pll_ctrl = unsafe { core::ptr::read_volatile(pll_ctrl_reg) };
    pll_ctrl.set_bypass_force(false);
--- a/zynq/zynq7000-hal/src/ddr/ll.rs
+++ b/zynq/zynq7000-hal/src/ddr/ll.rs
@@ -163,10 +163,7 @@ pub unsafe fn calibrate_iob_impedance(
            val
        });
        if poll_for_done {
-            while !slcr.ddriob().read_dci_status().done() {
-                // Wait for the DDR IOB impedance calibration to complete.
-                cortex_ar::asm::nop();
-            }
+            while !slcr.ddriob().read_dci_status().done() {}
        }
    });
 }
--- a/zynq/zynq7000-hal/src/ddr/mod.rs
+++ b/zynq/zynq7000-hal/src/ddr/mod.rs
@@ -89,7 +89,7 @@ pub fn configure_ddr_for_ddr3(
    let ddriob_shared = slcr.regs().ddriob_shared();
    // Wait for DDR IOB impedance calibration to complete first.
    while !ddriob_shared.read_dci_status().done() {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
    }
    log::debug!("DDR IOB impedance calib done");

@@ -103,7 +103,7 @@ pub fn configure_ddr_for_ddr3(
        != zynq7000::ddrc::regs::OperatingMode::NormalOperation
    {
        // Wait for the soft reset to complete.
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
    }
 }

--- a/zynq/zynq7000-hal/src/eth/ll.rs
+++ b/zynq/zynq7000-hal/src/eth/ll.rs
@@ -226,7 +226,7 @@ impl EthernetLowLevel {
            Slcr::with(|regs| {
                regs.reset_ctrl().write_eth(assert_reset);
                for _ in 0..cycles {
-                    cortex_ar::asm::nop();
+                    aarch32_cpu::asm::nop();
                }
                regs.reset_ctrl().write_eth(EthernetReset::DEFAULT);
            });
--- a/zynq/zynq7000-hal/src/gic.rs
+++ b/zynq/zynq7000-hal/src/gic.rs
@@ -8,7 +8,7 @@
 //! - [GTC ticks](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
 use arbitrary_int::prelude::*;

-use cortex_ar::interrupt;
+use aarch32_cpu::interrupt;
 use zynq7000::gic::{
    DistributorControlRegister, GicCpuInterfaceRegisters, GicDistributorRegisters,
    InterfaceControl, InterruptSignalRegister, MmioGicCpuInterfaceRegisters,
--- a/zynq/zynq7000-hal/src/gpio/mod.rs
+++ b/zynq/zynq7000-hal/src/gpio/mod.rs
@@ -49,7 +49,7 @@ pub fn reset() {
            regs.reset_ctrl()
                .write_gpio(GpioClockReset::builder().with_gpio_cpu1x_rst(true).build());
            // Keep it in reset for one cycle.. not sure if this is necessary.
-            cortex_ar::asm::nop();
+            aarch32_cpu::asm::nop();
            regs.reset_ctrl()
                .write_gpio(GpioClockReset::builder().with_gpio_cpu1x_rst(false).build());
        });
--- a/zynq/zynq7000-hal/src/i2c.rs
+++ b/zynq/zynq7000-hal/src/i2c.rs
@@ -658,7 +658,7 @@ pub fn reset(id: I2cId) {
            // Keep it in reset for some cycles.. The TMR just mentions some small delay,
            // no idea what is meant with that.
            for _ in 0..3 {
-                cortex_ar::asm::nop();
+                aarch32_cpu::asm::nop();
            }
            regs.reset_ctrl().write_i2c(DualClockReset::DEFAULT);
        });
--- a/zynq/zynq7000-hal/src/log.rs
+++ b/zynq/zynq7000-hal/src/log.rs
@@ -20,7 +20,7 @@ pub mod uart_blocking {
    use core::cell::{Cell, RefCell, UnsafeCell};
    use embedded_io::Write as _;

-    use cortex_ar::register::Cpsr;
+    use aarch32_cpu::register::Cpsr;
    use critical_section::Mutex;
    use log::{LevelFilter, Log, set_logger, set_max_level};

@@ -130,8 +130,8 @@ pub mod uart_blocking {
        fn log(&self, record: &log::Record) {
            if self.skip_in_isr.get() {
                match Cpsr::read().mode().unwrap() {
-                    cortex_ar::register::cpsr::ProcessorMode::Fiq
-                    | cortex_ar::register::cpsr::ProcessorMode::Irq => {
+                    aarch32_cpu::register::cpsr::ProcessorMode::Fiq
+                    | aarch32_cpu::register::cpsr::ProcessorMode::Irq => {
                        return;
                    }
                    _ => {}
--- a/zynq/zynq7000-hal/src/priv_tim.rs
+++ b/zynq/zynq7000-hal/src/priv_tim.rs
@@ -27,7 +27,7 @@ impl CpuPrivateTimer {
    ///
    /// This function can only be called once for each given core.
    pub fn take(clocks: &ArmClocks) -> Option<Self> {
-        let mpidr = cortex_ar::register::mpidr::Mpidr::read();
+        let mpidr = aarch32_cpu::register::mpidr::Mpidr::read();
        let core = mpidr.0 & 0xff;
        if core != 0 && core != 1 {
            return None;
--- a/zynq/zynq7000-hal/src/qspi/mod.rs
+++ b/zynq/zynq7000-hal/src/qspi/mod.rs
@@ -678,7 +678,7 @@ pub fn reset() {
            );
            // Keep it in reset for some cycles.
            for _ in 0..3 {
-                cortex_ar::asm::nop();
+                aarch32_cpu::asm::nop();
            }
            regs.reset_ctrl().write_lqspi(QspiResetControl::DEFAULT);
        });
--- a/zynq/zynq7000-hal/src/spi/mod.rs
+++ b/zynq/zynq7000-hal/src/spi/mod.rs
@@ -1119,7 +1119,7 @@ pub fn reset(id: SpiId) {
            // Keep it in reset for some cycles.. The TMR just mentions some small delay,
            // no idea what is meant with that.
            for _ in 0..3 {
-                cortex_ar::asm::nop();
+                aarch32_cpu::asm::nop();
            }
            regs.reset_ctrl().write_spi(DualRefAndClockReset::DEFAULT);
        });
--- a/zynq/zynq7000-hal/src/uart/mod.rs
+++ b/zynq/zynq7000-hal/src/uart/mod.rs
@@ -645,7 +645,7 @@ pub fn reset(id: UartId) {
        Slcr::with(|regs| {
            regs.reset_ctrl().write_uart(assert_reset);
            // Keep it in reset for one cycle.. not sure if this is necessary.
-            cortex_ar::asm::nop();
+            aarch32_cpu::asm::nop();
            regs.reset_ctrl().write_uart(DualRefAndClockReset::DEFAULT);
        });
    }
--- a/zynq/zynq7000-mmu/Cargo.toml
+++ b/zynq/zynq7000-mmu/Cargo.toml
@@ -11,7 +11,7 @@ categories = ["embedded", "no-std", "hardware-support"]

 [dependencies]
 thiserror = { version = "2", default-features = false }
-cortex-ar = { version = "0.3" }
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3" }

 [build-dependencies]
 arm-targets = { version = "0.3" }
--- a/zynq/zynq7000-mmu/src/lib.rs
+++ b/zynq/zynq7000-mmu/src/lib.rs
@@ -5,15 +5,15 @@
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_cfg))]

-use core::cell::UnsafeCell;
-use cortex_ar::mmu::L1Section;
+use aarch32_cpu::mmu::L1Section;
 #[cfg(all(not(feature = "tools"), arm_profile = "a"))]
-use cortex_ar::{
+use aarch32_cpu::{
    asm::{dsb, isb},
    cache::clean_and_invalidate_l1_data_cache,
    mmu::SectionAttributes,
    register::{BpIAll, TlbIAll},
 };
+use core::cell::UnsafeCell;

 pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;

--- a/zynq/zynq7000-rt/Cargo.toml
+++ b/zynq/zynq7000-rt/Cargo.toml
@@ -11,8 +11,8 @@ keywords = ["no-std", "rt", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]

 [dependencies]
-cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
-cortex-ar = { version = "0.3" }
+aarch32-rt = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.2", optional = true } # features = ["vfp-dp"] }
+aarch32-cpu = { git = "https://github.com/thejpster/cortex-ar.git", branch = "merge-rename", version = "0.3" }
 arbitrary-int = "2"
 zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }

@@ -21,7 +21,7 @@ arm-targets = { version = "0.3" }

 [features]
 default = ["rt"]
-rt = ["dep:cortex-a-rt"]
+rt = ["dep:aarch32-rt"]

 [package.metadata.docs.rs]
 targets = ["armv7a-none-eabihf"]
--- a/zynq/zynq7000-rt/src/lib.rs
+++ b/zynq/zynq7000-rt/src/lib.rs
@@ -10,7 +10,7 @@
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_cfg))]
 #[cfg(all(feature = "rt", arm_profile = "a"))]
-pub use cortex_a_rt::*;
+pub use aarch32_rt::*;

 #[cfg(feature = "rt")]
 use zynq7000_mmu::L1TableWrapper;
--- a/zynq/zynq7000-rt/src/mmu.rs
+++ b/zynq/zynq7000-rt/src/mmu.rs
@@ -84,10 +84,10 @@ pub mod segments {
 }

 pub mod section_attrs {
-    use arbitrary_int::u4;
-    use cortex_ar::mmu::{
+    use aarch32_cpu::mmu::{
        AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
    };
+    use arbitrary_int::u4;

    pub const DEFAULT_DOMAIN: u4 = u4::new(0b0000);
    // DDR is in different domain, but all domains are set as manager domains during run-time
--- a/zynq/zynq7000-rt/src/mmu_table.rs
+++ b/zynq/zynq7000-rt/src/mmu_table.rs
@@ -1,6 +1,6 @@
 //! This file was auto-generated by table-gen.rs
 use crate::mmu::section_attrs;
-use cortex_ar::mmu::L1Section;
+use aarch32_cpu::mmu::L1Section;
 use zynq7000_mmu::L1Table;

 /// MMU Level 1 Page table.
--- a/zynq/zynq7000-rt/src/rt.rs
+++ b/zynq/zynq7000-rt/src/rt.rs
@@ -5,8 +5,8 @@
 //! but does NOT provide the L2 cache initialization.
 //!
 //! The boot routine includes stack, MMU and .bss/.data section initialization.
-use cortex_a_rt as _;
-use cortex_ar::register::{Cpsr, cpsr::ProcessorMode};
+use aarch32_cpu::register::{Cpsr, cpsr::ProcessorMode};
+use aarch32_rt as _;

 // Start-up code for Armv7-A
 //
@@ -16,17 +16,6 @@ core::arch::global_asm!(
 .set PSS_L2CC_BASE_ADDR, 0xF8F02000
 .set PSS_SLCR_BASE_ADDR, 0xF8000000

-.set RESERVED,		0x0fffff00
-.set LRemap,		0xFE00000F		/* set the base address of the peripheral block as not shared */
-.set L2CCWay,		(PSS_L2CC_BASE_ADDR + 0x077C)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
-.set L2CCSync,		(PSS_L2CC_BASE_ADDR + 0x0730)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
-.set L2CCCrtl,		(PSS_L2CC_BASE_ADDR + 0x0100)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
-.set L2CCAuxCrtl,	(PSS_L2CC_BASE_ADDR + 0x0104)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
-.set L2CCTAGLatReg,	(PSS_L2CC_BASE_ADDR + 0x0108)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
-.set L2CCDataLatReg,	(PSS_L2CC_BASE_ADDR + 0x010C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
-.set L2CCIntClear,	(PSS_L2CC_BASE_ADDR + 0x0220)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
-.set L2CCIntRaw,	(PSS_L2CC_BASE_ADDR + 0x021C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
-
 .set SLCRlockReg,	    (PSS_SLCR_BASE_ADDR + 0x04)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
 .set SLCRUnlockReg,     (PSS_SLCR_BASE_ADDR + 0x08)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
 .set SLCRL2cRamReg,     (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
@@ -36,12 +25,6 @@ core::arch::global_asm!(
 .set CRValMmuCac,	0b01000000000101	/* Enable IDC, and MMU */
 .set CRValHiVectorAddr,	0b10000000000000	/* Set the Vector address to high, 0xFFFF0000 */

-.set L2CCAuxControl,	0x72360000		/* Enable all prefetching, Cache replacement policy, Parity enable,
-                                        Event monitor bus enable and Way Size (64 KB) */
-.set L2CCControl,	0x01			/* Enable L2CC */
-.set L2CCTAGLatency,	0x0111			/* latency for TAG RAM */
-.set L2CCDataLatency,	0x0121			/* latency for DATA RAM */
-
 .set SLCRlockKey,	        0x767B			/* SLCR lock key */
 .set SLCRUnlockKey,	        0xDF0D			/* SLCR unlock key */
 .set SLCRL2cRamConfig,      0x00020202      /* SLCR L2C ram configuration */