init commit
This commit is contained in:
5
zedboard-fpga-design/.gitignore
vendored
Normal file
5
zedboard-fpga-design/.gitignore
vendored
Normal file
@ -0,0 +1,5 @@
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||||
/zedboard-rust
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||||
/.Xil
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/vivado*
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/sdt_out
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/xsct-output.log
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||||
40
zedboard-fpga-design/README.md
Normal file
40
zedboard-fpga-design/README.md
Normal file
@ -0,0 +1,40 @@
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||||
Zedboard FPGA design for Rust
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||||
=======
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||||
|
||||
This is an example/reference design which was used to verify various components provided
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||||
by this library. To minimize the amount of HW designs required, one project is provided.
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The design was kept as generic as possible. In principle, it should be possible to adapt the
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hardware design to other boards with modifications.
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||||
# Pre-Requisites
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||||
- [Vivado installation](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html)
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or [Vitis installation](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html)
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||||
which includes Vivado. This example design was created with/for Vivado 2024.1, but also might work
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for newer versions.
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||||
- [Zedboard board files](https://github.com/Digilent/vivado-boards) added to the Vivado installation.
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||||
# Loading the project and the block design with the GUI
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||||
You can load the project using the batch mode of `vivado` inside the folder where you want to
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||||
create the `zedboard-rust` project:
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```sh
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vivado -mode batch -source <path to zedboard-rust.tcl> -tclargs --overwrite
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```
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||||
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for example, to create the directory directly insdie this directory:
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```sh
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vivado -mode batch -source zedboard-rust.tcl -tclargs --overwrite
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||||
```
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||||
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||||
This should create a `zedboard-rust` Vivado project folder containing a `zedboard-rust.xpr`
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project file. You can load this project file with Vivado:
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```sh
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vivado zedboard-rust.xpr
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```
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||||
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||||
You can perform all the steps specified in the Vivado GUI as well using `Execute TCL script` and
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`Load Project`.
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2
zedboard-fpga-design/export-hw.tcl
Normal file
2
zedboard-fpga-design/export-hw.tcl
Normal file
@ -0,0 +1,2 @@
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set hw_file "[get_property DIRECTORY [current_project]]/zedboard-rust.xsa"
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write_hw_platform -fixed -include_bit -force -file $hw_file
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69
zedboard-fpga-design/sdtgen.py
Executable file
69
zedboard-fpga-design/sdtgen.py
Executable file
@ -0,0 +1,69 @@
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#!/usr/bin/env python3
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import argparse
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import os
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import subprocess
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import sys
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def main():
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parser = argparse.ArgumentParser(
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description="Script to generate SDT files from a XSA file"
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)
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parser.add_argument(
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||||
"-t",
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"--tools",
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# Required only if env var is not set
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required=not bool(os.getenv("AMD_TOOLS")),
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# Use env var if set
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default=os.getenv("AMD_TOOLS"),
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help="The path to the tool to use. Must point to a valid Vivado tools installation which"
|
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"also provides xsct, for example a Vitis installation.\nThe directory where the path "
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||||
"points to should contain a shell script named settings64.sh.\n You can also set the "
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"AMD_TOOLS env variable to set this.",
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)
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parser.add_argument(
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"-x",
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"--xsa",
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help="Path to the input XSA file",
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default="zedboard-rust/zedboard-rust.xsa",
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)
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parser.add_argument(
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"-o",
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"--out",
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default="sdt_out",
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help="Directory to store the generated SDT files",
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)
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args = parser.parse_args()
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settings_script = os.path.join(args.tools, "settings64.sh")
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if not os.path.isfile(settings_script):
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print(f"Invalid tool path {args.tools}, did not find settings file.")
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sys.exit(1)
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# Source the settings script and check for xsdb availability
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command = f"source {settings_script} && command -v xsct"
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result = subprocess.run(
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command,
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shell=True,
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capture_output=True,
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executable="/bin/bash",
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)
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if result.returncode != 0:
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print("Error: 'xsct' could not be found after sourcing settings64.sh.")
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sys.exit(1)
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xsct_script = "sdtgen.tcl"
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command = f"bash -c 'source {settings_script} && xsct {xsct_script} {args.xsa} {args.out} | tee xsct-output.log'"
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subprocess.run(
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command,
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shell=True,
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||||
check=True,
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||||
)
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||||
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||||
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||||
if __name__ == "__main__":
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main()
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4
zedboard-fpga-design/sdtgen.tcl
Normal file
4
zedboard-fpga-design/sdtgen.tcl
Normal file
@ -0,0 +1,4 @@
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set outdir [lindex $argv 1]
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set xsa [lindex $argv 0]
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sdtgen set_dt_param -xsa $xsa -dir $outdir -board_dts zedboard
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sdtgen generate_sdt
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88
zedboard-fpga-design/src/uart_mux.vhd
Normal file
88
zedboard-fpga-design/src/uart_mux.vhd
Normal file
@ -0,0 +1,88 @@
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||||
----------------------------------------------------------------------------------
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||||
-- Company: Institute of Space Systems, University of Stuttgart
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-- Engineer: Robin Mueller
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||||
--
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||||
-- Description:
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||||
-- The module multiplexes three UART modules.
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-- It can be used to select between UART0 through EMIO, UARTLITE or UART16550.
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----------------------------------------------------------------------------------
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||||
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity uart_mux is
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port(
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sys_clk : in std_logic;
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||||
|
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uart_0_tx : in std_logic;
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uart_0_rx : out std_logic;
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|
||||
uart_1_tx : in std_logic;
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||||
uart_1_rx : out std_logic;
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||||
|
||||
uart_2_tx : in std_logic;
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uart_2_rx : out std_logic;
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||||
|
||||
tx_out: out std_logic;
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||||
rx_in: in std_logic;
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||||
|
||||
-- "000" -> UART0
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||||
-- "001" -> UART1
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||||
-- "010" -> UART2
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||||
-- "011" -> UART0 to UART1
|
||||
-- "100" -> UART0 to UART2
|
||||
-- "101" -> UART1 to UART2
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||||
sel : in std_logic_vector(2 downto 0)
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||||
|
||||
);
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||||
end uart_mux;
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||||
|
||||
architecture Behavioral of uart_mux is
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||||
|
||||
begin
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||||
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||||
switch : process(sys_clk)
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||||
begin
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||||
if rising_edge(sys_clk) then
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case sel is
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||||
when "000" =>
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tx_out <= uart_0_tx;
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||||
uart_0_rx <= rx_in;
|
||||
uart_1_rx <= '1';
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||||
uart_2_rx <= '1';
|
||||
when "001" =>
|
||||
tx_out <= uart_1_tx;
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||||
uart_1_rx <= rx_in;
|
||||
uart_2_rx <= '1';
|
||||
uart_0_rx <= '1';
|
||||
when "010" =>
|
||||
tx_out <= uart_2_tx;
|
||||
uart_2_rx <= rx_in;
|
||||
uart_1_rx <= '1';
|
||||
uart_0_rx <= '1';
|
||||
when "011" =>
|
||||
tx_out <= '1';
|
||||
uart_1_rx <= uart_0_tx;
|
||||
uart_0_rx <= uart_1_tx;
|
||||
uart_2_rx <= '1';
|
||||
when "100" =>
|
||||
tx_out <= '1';
|
||||
uart_2_rx <= uart_0_tx;
|
||||
uart_0_rx <= uart_2_tx;
|
||||
uart_1_rx <= '1';
|
||||
when "101" =>
|
||||
tx_out <= '1';
|
||||
uart_1_rx <= uart_2_tx;
|
||||
uart_2_rx <= uart_1_tx;
|
||||
uart_0_rx <= '1';
|
||||
when others =>
|
||||
tx_out <= '1';
|
||||
uart_0_rx <= '1';
|
||||
uart_1_rx <= '1';
|
||||
uart_2_rx <= '1';
|
||||
end case;
|
||||
end if;
|
||||
end process; -- switch
|
||||
|
||||
end Behavioral;
|
||||
698
zedboard-fpga-design/src/zedboard-bd.tcl
Normal file
698
zedboard-fpga-design/src/zedboard-bd.tcl
Normal file
@ -0,0 +1,698 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: zedboard
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2024.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
|
||||
|
||||
} else {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source zedboard_script.tcl
|
||||
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# uart_mux
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7z020clg484-1
|
||||
set_property BOARD_PART digilentinc.com:zedboard:part0:1.1 [current_project]
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name zedboard
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:processing_system7:5.5\
|
||||
xilinx.com:ip:axi_uartlite:2.0\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:axi_uart16550:2.0\
|
||||
xilinx.com:ip:xlconcat:2.1\
|
||||
xilinx.com:ip:xlslice:1.0\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
uart_mux\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
|
||||
|
||||
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
|
||||
|
||||
|
||||
# Create ports
|
||||
set LEDS [ create_bd_port -dir O -from 7 -to 0 LEDS ]
|
||||
set SWITCHES [ create_bd_port -dir I -from 7 -to 0 SWITCHES ]
|
||||
set BTTNS [ create_bd_port -dir I -from 4 -to 0 BTTNS ]
|
||||
set UART_txd [ create_bd_port -dir O UART_txd ]
|
||||
set UART_rxd [ create_bd_port -dir I UART_rxd ]
|
||||
set TTC0_WAVEOUT [ create_bd_port -dir O TTC0_WAVEOUT ]
|
||||
|
||||
# Create instance: processing_system7_0, and set properties
|
||||
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
|
||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
|
||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
|
||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
|
||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
|
||||
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
|
||||
CONFIG.PCW_CLK0_FREQ {100000000} \
|
||||
CONFIG.PCW_CLK1_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
||||
CONFIG.PCW_CORE0_FIQ_INTR {0} \
|
||||
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
|
||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
|
||||
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
|
||||
CONFIG.PCW_ENET0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET_RESET_ENABLE {1} \
|
||||
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
|
||||
CONFIG.PCW_EN_EMIO_GPIO {1} \
|
||||
CONFIG.PCW_EN_EMIO_TTC0 {1} \
|
||||
CONFIG.PCW_EN_EMIO_TTC1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_UART0 {1} \
|
||||
CONFIG.PCW_EN_EMIO_WP_SDIO0 {1} \
|
||||
CONFIG.PCW_EN_ENET0 {1} \
|
||||
CONFIG.PCW_EN_GPIO {1} \
|
||||
CONFIG.PCW_EN_QSPI {1} \
|
||||
CONFIG.PCW_EN_SDIO0 {1} \
|
||||
CONFIG.PCW_EN_TTC0 {1} \
|
||||
CONFIG.PCW_EN_TTC1 {0} \
|
||||
CONFIG.PCW_EN_UART0 {1} \
|
||||
CONFIG.PCW_EN_UART1 {1} \
|
||||
CONFIG.PCW_EN_USB0 {1} \
|
||||
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
|
||||
CONFIG.PCW_I2C_RESET_ENABLE {1} \
|
||||
CONFIG.PCW_IRQ_F2P_INTR {1} \
|
||||
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_0_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_0_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_10_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_10_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_11_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_11_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_12_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_12_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_13_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_13_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_14_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_14_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_15_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_15_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_16_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_16_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_17_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_17_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_18_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_18_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_19_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_19_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_1_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_1_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_20_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_20_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_21_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_21_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_22_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_22_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_23_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_23_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_24_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_24_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_25_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_25_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_26_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_26_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} \
|
||||
CONFIG.PCW_MIO_27_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_27_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_28_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_28_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_29_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_29_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_2_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_30_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_30_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_31_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_31_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_32_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_32_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_33_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_33_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_34_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_34_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_35_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_35_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_36_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_36_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_37_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_37_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_38_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_38_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_39_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_39_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_3_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_40_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_40_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_41_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_41_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_42_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_42_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_43_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_43_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_44_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_44_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_45_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_45_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_46_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_46_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_47_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_47_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_48_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_48_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_49_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_49_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_4_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_50_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_50_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_51_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_51_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_52_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_52_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_53_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_53_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_5_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_6_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_7_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_8_SLEW {fast} \
|
||||
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_9_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_9_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet\
|
||||
0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#GPIO#GPIO}\
|
||||
\
|
||||
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#gpio[52]#gpio[53]}\
|
||||
\
|
||||
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
|
||||
CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
|
||||
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
||||
CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
|
||||
CONFIG.PCW_SD0_GRP_WP_IO {EMIO} \
|
||||
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
||||
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
||||
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
|
||||
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_UART0_UART0_IO {EMIO} \
|
||||
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.176} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.159} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.162} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.187} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.034} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.03} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.082} \
|
||||
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
|
||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
|
||||
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_USB0_RESET_ENABLE {1} \
|
||||
CONFIG.PCW_USB0_RESET_IO {MIO 46} \
|
||||
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
|
||||
CONFIG.PCW_USB_RESET_ENABLE {1} \
|
||||
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
|
||||
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
|
||||
] $processing_system7_0
|
||||
|
||||
|
||||
# Create instance: axi_uartlite_0, and set properties
|
||||
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_BAUDRATE {115200} \
|
||||
CONFIG.UARTLITE_BOARD_INTERFACE {Custom} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $axi_uartlite_0
|
||||
|
||||
|
||||
# Create instance: ps7_0_axi_periph, and set properties
|
||||
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
|
||||
set_property CONFIG.NUM_MI {2} $ps7_0_axi_periph
|
||||
|
||||
|
||||
# Create instance: rst_ps7_0_100M, and set properties
|
||||
set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
|
||||
|
||||
# Create instance: axi_uart16550_0, and set properties
|
||||
set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.UART_BOARD_INTERFACE {Custom} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $axi_uart16550_0
|
||||
|
||||
|
||||
# Create instance: IRQ_F2P, and set properties
|
||||
set IRQ_F2P [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 IRQ_F2P ]
|
||||
|
||||
# Create instance: LEDS, and set properties
|
||||
set LEDS [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 LEDS ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIN_FROM {7} \
|
||||
CONFIG.DIN_WIDTH {16} \
|
||||
] $LEDS
|
||||
|
||||
|
||||
# Create instance: EMIO_O_0, and set properties
|
||||
set EMIO_O_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 EMIO_O_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIN_FROM {15} \
|
||||
CONFIG.DIN_WIDTH {64} \
|
||||
] $EMIO_O_0
|
||||
|
||||
|
||||
# Create instance: EMIO_O_1, and set properties
|
||||
set EMIO_O_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 EMIO_O_1 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIN_FROM {47} \
|
||||
CONFIG.DIN_TO {32} \
|
||||
CONFIG.DIN_WIDTH {64} \
|
||||
] $EMIO_O_1
|
||||
|
||||
|
||||
# Create instance: EMIO_I, and set properties
|
||||
set EMIO_I [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 EMIO_I ]
|
||||
set_property -dict [list \
|
||||
CONFIG.IN0_WIDTH {16} \
|
||||
CONFIG.IN1_WIDTH {16} \
|
||||
CONFIG.IN2_WIDTH {16} \
|
||||
CONFIG.IN3_WIDTH {16} \
|
||||
CONFIG.NUM_PORTS {4} \
|
||||
] $EMIO_I
|
||||
|
||||
|
||||
# Create instance: EMIO_I_0, and set properties
|
||||
set EMIO_I_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 EMIO_I_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.IN0_WIDTH {8} \
|
||||
CONFIG.IN1_WIDTH {5} \
|
||||
CONFIG.IN2_WIDTH {3} \
|
||||
CONFIG.NUM_PORTS {3} \
|
||||
] $EMIO_I_0
|
||||
|
||||
|
||||
# Create instance: xlconstant_0, and set properties
|
||||
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CONST_VAL {0} \
|
||||
CONFIG.CONST_WIDTH {3} \
|
||||
] $xlconstant_0
|
||||
|
||||
|
||||
# Create instance: EMIO_I_1, and set properties
|
||||
set EMIO_I_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 EMIO_I_1 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CONST_VAL {0} \
|
||||
CONFIG.CONST_WIDTH {16} \
|
||||
] $EMIO_I_1
|
||||
|
||||
|
||||
# Create instance: uart_mux_0, and set properties
|
||||
set block_name uart_mux
|
||||
set block_cell_name uart_mux_0
|
||||
if { [catch {set uart_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $uart_mux_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: UART_MUX, and set properties
|
||||
set UART_MUX [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 UART_MUX ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIN_FROM {10} \
|
||||
CONFIG.DIN_TO {8} \
|
||||
CONFIG.DIN_WIDTH {16} \
|
||||
] $UART_MUX
|
||||
|
||||
|
||||
# Create instance: xlconstant_1, and set properties
|
||||
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
|
||||
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net EMIO_O_1_Dout [get_bd_pins EMIO_O_1/Dout] [get_bd_pins EMIO_I/In2]
|
||||
connect_bd_net -net In0_0_1 [get_bd_ports SWITCHES] [get_bd_pins EMIO_I_0/In0]
|
||||
connect_bd_net -net In1_0_1 [get_bd_ports BTTNS] [get_bd_pins EMIO_I_0/In1]
|
||||
connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins IRQ_F2P/In1]
|
||||
connect_bd_net -net axi_uart16550_0_sout [get_bd_pins axi_uart16550_0/sout] [get_bd_pins uart_mux_0/uart_2_tx]
|
||||
connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins IRQ_F2P/In0]
|
||||
connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins uart_mux_0/uart_1_tx]
|
||||
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins uart_mux_0/sys_clk]
|
||||
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
|
||||
connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins processing_system7_0/GPIO_O] [get_bd_pins EMIO_O_0/Din] [get_bd_pins EMIO_O_1/Din]
|
||||
connect_bd_net -net processing_system7_0_TTC0_WAVE0_OUT [get_bd_pins processing_system7_0/TTC0_WAVE0_OUT] [get_bd_ports TTC0_WAVEOUT]
|
||||
connect_bd_net -net processing_system7_0_UART0_TX [get_bd_pins processing_system7_0/UART0_TX] [get_bd_pins uart_mux_0/uart_0_tx]
|
||||
connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M01_ARESETN]
|
||||
connect_bd_net -net rx_in_0_1 [get_bd_ports UART_rxd] [get_bd_pins uart_mux_0/rx_in]
|
||||
connect_bd_net -net uart_mux_0_tx_out [get_bd_pins uart_mux_0/tx_out] [get_bd_ports UART_txd]
|
||||
connect_bd_net -net uart_mux_0_uart_0_rx [get_bd_pins uart_mux_0/uart_0_rx] [get_bd_pins processing_system7_0/UART0_RX]
|
||||
connect_bd_net -net uart_mux_0_uart_1_rx [get_bd_pins uart_mux_0/uart_1_rx] [get_bd_pins axi_uartlite_0/rx]
|
||||
connect_bd_net -net uart_mux_0_uart_2_rx [get_bd_pins uart_mux_0/uart_2_rx] [get_bd_pins axi_uart16550_0/sin]
|
||||
connect_bd_net -net xlconcat_0_dout [get_bd_pins IRQ_F2P/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
|
||||
connect_bd_net -net xlconcat_1_dout [get_bd_pins EMIO_I/dout] [get_bd_pins processing_system7_0/GPIO_I]
|
||||
connect_bd_net -net xlconcat_1_dout1 [get_bd_pins EMIO_I_0/dout] [get_bd_pins EMIO_I/In1]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins EMIO_I_0/In2]
|
||||
connect_bd_net -net xlconstant_1_dout [get_bd_pins EMIO_I_1/dout] [get_bd_pins EMIO_I/In3]
|
||||
connect_bd_net -net xlconstant_1_dout1 [get_bd_pins xlconstant_1/dout] [get_bd_pins axi_uart16550_0/rin] [get_bd_pins axi_uart16550_0/dsrn] [get_bd_pins axi_uart16550_0/ctsn] [get_bd_pins axi_uart16550_0/dcdn]
|
||||
connect_bd_net -net xlslice_0_Dout [get_bd_pins LEDS/Dout] [get_bd_ports LEDS]
|
||||
connect_bd_net -net xlslice_0_Dout1 [get_bd_pins UART_MUX/Dout] [get_bd_pins uart_mux_0/sel]
|
||||
connect_bd_net -net xlslice_1_Dout [get_bd_pins EMIO_O_0/Dout] [get_bd_pins LEDS/Din] [get_bd_pins EMIO_I/In0] [get_bd_pins UART_MUX/Din]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
75
zedboard-fpga-design/src/zedboard.xdc
Normal file
75
zedboard-fpga-design/src/zedboard.xdc
Normal file
@ -0,0 +1,75 @@
|
||||
# Zedboard LD0
|
||||
set_property PACKAGE_PIN T22 [get_ports {LEDS[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}]
|
||||
# Zedboard LD1
|
||||
set_property PACKAGE_PIN T21 [get_ports {LEDS[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}]
|
||||
# Zedboard LD2
|
||||
set_property PACKAGE_PIN U22 [get_ports {LEDS[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[2]}]
|
||||
# Zedboard LD3
|
||||
set_property PACKAGE_PIN U21 [get_ports {LEDS[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[3]}]
|
||||
# Zedboard LD4
|
||||
set_property PACKAGE_PIN V22 [get_ports {LEDS[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[4]}]
|
||||
# Zedboard LD5
|
||||
set_property PACKAGE_PIN W22 [get_ports {LEDS[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[5]}]
|
||||
# Zedboard LD6
|
||||
set_property PACKAGE_PIN U19 [get_ports {LEDS[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[6]}]
|
||||
# Zedboard LD7
|
||||
set_property PACKAGE_PIN U14 [get_ports {LEDS[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[7]}]
|
||||
|
||||
# Zedboard SW0
|
||||
set_property PACKAGE_PIN F22 [get_ports {SWITCHES[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[0]}]
|
||||
# Zedboard SW1
|
||||
set_property PACKAGE_PIN G22 [get_ports {SWITCHES[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[1]}]
|
||||
# Zedboard SW2
|
||||
set_property PACKAGE_PIN H22 [get_ports {SWITCHES[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[2]}]
|
||||
# Zedboard SW3
|
||||
set_property PACKAGE_PIN F21 [get_ports {SWITCHES[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[3]}]
|
||||
# Zedboard SW4
|
||||
set_property PACKAGE_PIN H19 [get_ports {SWITCHES[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[4]}]
|
||||
# Zedboard SW5
|
||||
set_property PACKAGE_PIN H18 [get_ports {SWITCHES[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[5]}]
|
||||
# Zedboard SW6
|
||||
set_property PACKAGE_PIN H17 [get_ports {SWITCHES[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[6]}]
|
||||
# Zedboard SW7
|
||||
set_property PACKAGE_PIN M15 [get_ports {SWITCHES[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SWITCHES[7]}]
|
||||
|
||||
# Zedboard BTNC
|
||||
set_property PACKAGE_PIN P16 [get_ports {BTTNS[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {BTTNS[0]}]
|
||||
# Zedboard BTND
|
||||
set_property PACKAGE_PIN R16 [get_ports {BTTNS[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {BTTNS[1]}]
|
||||
# Zedboard BTNL
|
||||
set_property PACKAGE_PIN N15 [get_ports {BTTNS[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {BTTNS[2]}]
|
||||
# Zedboard BTNR
|
||||
set_property PACKAGE_PIN R18 [get_ports {BTTNS[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {BTTNS[3]}]
|
||||
# Zedboard BTNU
|
||||
set_property PACKAGE_PIN T18 [get_ports {BTTNS[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {BTTNS[4]}]
|
||||
|
||||
# UART
|
||||
set_property PACKAGE_PIN Y11 [get_ports UART_rxd]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports UART_rxd]
|
||||
set_property PACKAGE_PIN AA11 [get_ports UART_txd]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports UART_txd]
|
||||
|
||||
# TTC0 Wave Out
|
||||
set_property PACKAGE_PIN W12 [get_ports {TTC0_WAVEOUT}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {TTC0_WAVEOUT}]
|
||||
528
zedboard-fpga-design/zedboard-rust.tcl
Normal file
528
zedboard-fpga-design/zedboard-rust.tcl
Normal file
@ -0,0 +1,528 @@
|
||||
#*****************************************************************************************
|
||||
# Vivado (TM) v2024.1 (64-bit)
|
||||
#
|
||||
# zedboard-rust.tcl: Tcl script for re-creating project 'zedboard-rust'
|
||||
#
|
||||
# Generated by Vivado on Fri Mar 14 13:10:19 CET 2025
|
||||
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
# when this script was generated. In order to re-create the project, please source this
|
||||
# file in the Vivado Tcl Shell.
|
||||
#
|
||||
# * Note that the runs in the created project will be configured the same way as the
|
||||
# original project, however they will not be launched automatically. To regenerate the
|
||||
# run results please launch the synthesis/implementation runs as needed.
|
||||
#
|
||||
#*****************************************************************************************
|
||||
# NOTE: In order to use this script for source control purposes, please make sure that the
|
||||
# following files are added to the source control system:-
|
||||
#
|
||||
# 1. This project restoration tcl script (zedboard-rust.tcl) that was generated.
|
||||
# 2. Constraints file in src directory
|
||||
# 3. BD export file in src directory
|
||||
#
|
||||
#*****************************************************************************************
|
||||
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
||||
set script_dir [file dirname [info script]]
|
||||
set origin_dir "."
|
||||
|
||||
set constr_file [file normalize "$script_dir/src/zedboard.xdc"]
|
||||
set bd_file [file normalize "$script_dir/src/zedboard-bd.tcl"]
|
||||
|
||||
set uart_mux_file [file normalize "$script_dir/src/uart_mux.vhd"]
|
||||
|
||||
# Check file required for this script exists
|
||||
proc checkRequiredFiles { origin_dir} {
|
||||
set status true
|
||||
set files [list \
|
||||
"[file normalize $constr_file]"\
|
||||
"[file normalize $bd_file]"\
|
||||
]
|
||||
foreach ifile $files {
|
||||
if { ![file isfile $ifile] } {
|
||||
puts " Could not find local file $ifile "
|
||||
set status false
|
||||
}
|
||||
}
|
||||
|
||||
return $status
|
||||
}
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
# Set the project name
|
||||
set _xil_proj_name_ "zedboard-rust"
|
||||
|
||||
# Use project name variable, if specified in the tcl shell
|
||||
if { [info exists ::user_project_name] } {
|
||||
set _xil_proj_name_ $::user_project_name
|
||||
}
|
||||
|
||||
variable script_file
|
||||
set script_file "zedboard-rust.tcl"
|
||||
|
||||
# Help information for this script
|
||||
proc print_help {} {
|
||||
variable script_file
|
||||
puts "\nDescription:"
|
||||
puts "Recreate a Vivado project from this script. The created project will be"
|
||||
puts "functionally equivalent to the original project for which this script was"
|
||||
puts "generated. The script contains commands for creating a project, filesets,"
|
||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
||||
puts "Syntax:"
|
||||
puts "$script_file"
|
||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
||||
puts "$script_file -tclargs \[--help\]\n"
|
||||
puts "$script_file -tclargs \[--overwrite\]\n"
|
||||
puts "Usage:"
|
||||
puts "Name Description"
|
||||
puts "-------------------------------------------------------------------------"
|
||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
||||
puts " origin_dir path value is \".\", otherwise, the value"
|
||||
puts " that was set with the \"-paths_relative_to\" switch"
|
||||
puts " when this script was generated.\n"
|
||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
||||
puts " name is the name of the project from where this"
|
||||
puts " script was generated.\n"
|
||||
puts "\[--help\] Print help information for this script"
|
||||
puts "\[--overwrite\] Ovewrite the existing project if it exists"
|
||||
puts "-------------------------------------------------------------------------\n"
|
||||
exit 0
|
||||
}
|
||||
|
||||
set _force ""
|
||||
|
||||
if { $::argc > 0 } {
|
||||
for {set i 0} {$i < $::argc} {incr i} {
|
||||
set option [string trim [lindex $::argv $i]]
|
||||
switch -regexp -- $option {
|
||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
||||
"--overwrite" { incr i; set _force "-force"}
|
||||
"--help" { print_help }
|
||||
default {
|
||||
if { [regexp {^-} $option] } {
|
||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Create project
|
||||
if { $_force ne "" } {
|
||||
create_project ${_xil_proj_name_} ${origin_dir}/${_xil_proj_name_} -part xc7z020clg484-1 $_force
|
||||
} else {
|
||||
create_project ${_xil_proj_name_} ${origin_dir}/${_xil_proj_name_} -part xc7z020clg484-1
|
||||
}
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
||||
# Reconstruct message rules
|
||||
# None
|
||||
|
||||
# Set project properties
|
||||
set obj [current_project]
|
||||
set_property -name "board_part" -value "digilentinc.com:zedboard:part0:1.1" -objects $obj
|
||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
||||
set_property -name "enable_resource_estimation" -value "0" -objects $obj
|
||||
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
|
||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
||||
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
|
||||
set_property -name "platform.board_id" -value "zedboard" -objects $obj
|
||||
set_property -name "revised_directory_structure" -value "1" -objects $obj
|
||||
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
||||
set_property -name "sim_compile_state" -value "1" -objects $obj
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
set files [list \
|
||||
$uart_mux_file \
|
||||
]
|
||||
add_files -norecurse -fileset $obj $files
|
||||
|
||||
set_property file_type "VHDL" [get_files $uart_mux_file]
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
|
||||
# Create 'constrs_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
add_files -fileset constrs_1 -norecurse $constr_file
|
||||
|
||||
# Retrieve the file object correctly
|
||||
set file_obj [get_files -of_objects [get_filesets constrs_1]]
|
||||
# Set the file type property
|
||||
set_property -name "file_type" -value "XDC" -objects $file_obj
|
||||
# Set as target constraints file.
|
||||
# set_property -name "target_constrs_file" -value $constr_file -objects $file_obj
|
||||
set_property target_constrs_file $constr_file [current_fileset -constrset]
|
||||
set_property target_ucf $constr_file [current_fileset -constrset]
|
||||
|
||||
# Load block design.
|
||||
set ret [source $bd_file]
|
||||
if {$ret != ""} {
|
||||
error "Failed to generate block design with return value $ret"
|
||||
}
|
||||
set design_name [get_bd_designs]
|
||||
make_wrapper -files [get_files $design_name.bd] -top -import
|
||||
|
||||
# Create 'sim_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
||||
create_fileset -simset sim_1
|
||||
}
|
||||
|
||||
# Set 'sim_1' fileset object
|
||||
set obj [get_filesets sim_1]
|
||||
# Empty (no sources present)
|
||||
|
||||
# Set 'sim_1' fileset properties
|
||||
set obj [get_filesets sim_1]
|
||||
set_property -name "top" -value "zedboard_wrapper" -objects $obj
|
||||
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
||||
|
||||
# Set 'utils_1' fileset object
|
||||
set obj [get_filesets utils_1]
|
||||
|
||||
# Set 'utils_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'utils_1' fileset file properties for local files
|
||||
# None
|
||||
|
||||
# Set 'utils_1' fileset properties
|
||||
set obj [get_filesets utils_1]
|
||||
|
||||
set idrFlowPropertiesConstraints ""
|
||||
catch {
|
||||
set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
|
||||
set_param runs.disableIDRFlowPropertyConstraints 1
|
||||
}
|
||||
|
||||
# Create 'synth_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
||||
create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
||||
} else {
|
||||
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
||||
set_property flow "Vivado Synthesis 2024" [get_runs synth_1]
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property set_report_strategy_name 1 $obj
|
||||
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
||||
set_property set_report_strategy_name 0 $obj
|
||||
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
||||
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property -name "needs_refresh" -value "1" -objects $obj
|
||||
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
|
||||
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
|
||||
|
||||
# set the current synth run
|
||||
current_run -synthesis [get_runs synth_1]
|
||||
|
||||
# Create 'impl_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet impl_1] ""]} {
|
||||
create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
||||
} else {
|
||||
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
||||
set_property flow "Vivado Implementation 2024" [get_runs impl_1]
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property set_report_strategy_name 1 $obj
|
||||
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
||||
set_property set_report_strategy_name 0 $obj
|
||||
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
||||
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_io_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.verbose" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_drc_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_power_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
||||
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property -name "needs_refresh" -value "1" -objects $obj
|
||||
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
||||
|
||||
# set the current impl run
|
||||
current_run -implementation [get_runs impl_1]
|
||||
catch {
|
||||
if { $idrFlowPropertiesConstraints != {} } {
|
||||
set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
|
||||
}
|
||||
}
|
||||
|
||||
puts "INFO: Project created:${_xil_proj_name_}"
|
||||
# Create 'drc_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {drc_1} -type drc
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
|
||||
|
||||
# Create 'methodology_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {methodology_1} -type methodology
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
|
||||
|
||||
# Create 'power_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {power_1} -type power
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "power_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
|
||||
|
||||
# Create 'timing_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {timing_1} -type timing
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
|
||||
|
||||
# Create 'utilization_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {utilization_1} -type utilization
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
|
||||
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
|
||||
set_property -name "run.step" -value "synth_design" -objects $obj
|
||||
set_property -name "run.type" -value "synthesis" -objects $obj
|
||||
|
||||
# Create 'utilization_2' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
|
||||
create_dashboard_gadget -name {utilization_2} -type utilization
|
||||
}
|
||||
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
|
||||
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
|
||||
|
||||
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
|
||||
move_dashboard_gadget -name {power_1} -row 1 -col 0
|
||||
move_dashboard_gadget -name {drc_1} -row 2 -col 0
|
||||
move_dashboard_gadget -name {timing_1} -row 0 -col 1
|
||||
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
|
||||
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
|
||||
Reference in New Issue
Block a user