rust/zynq7000-rs
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Robin Müller
2025-02-19 11:00:04 +01:00
commit f842673e3a
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zedboard-fpga-design/sdtgen.tcl Normal file
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set outdir [lindex $argv 1]
set xsa [lindex $argv 0]
sdtgen set_dt_param -xsa $xsa -dir $outdir -board_dts zedboard
sdtgen generate_sdt