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345
zynq7000-hal/src/gpio/ll.rs
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345
zynq7000-hal/src/gpio/ll.rs
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//! Low-level GPIO access module.
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use embedded_hal::digital::PinState;
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use zynq7000::gpio::{Gpio, MaskedOutput, MmioGpio};
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use crate::slcr::Slcr;
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use super::{mio::MuxConf, PinIsOutputOnly};
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#[derive(Debug, Clone, Copy)]
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pub enum PinOffset {
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Mio(usize),
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Emio(usize),
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}
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impl PinOffset {
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/// Returs [None] if offset is larger than 53.
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pub const fn new_for_mio(offset: usize) -> Option<Self> {
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if offset > 53 {
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return None;
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}
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Some(PinOffset::Mio(offset))
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}
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/// Returs [None] if offset is larger than 63.
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pub const fn new_for_emio(offset: usize) -> Option<Self> {
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if offset > 63 {
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return None;
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}
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Some(PinOffset::Emio(offset))
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}
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pub fn is_mio(&self) -> bool {
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match self {
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PinOffset::Mio(_) => true,
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PinOffset::Emio(_) => false,
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}
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}
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}
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impl PinOffset {
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pub fn offset(&self) -> usize {
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match self {
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PinOffset::Mio(offset) => *offset,
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PinOffset::Emio(offset) => *offset,
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}
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}
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}
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pub struct LowLevelGpio {
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offset: PinOffset,
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regs: MmioGpio<'static>,
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}
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impl LowLevelGpio {
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pub fn new(offset: PinOffset) -> Self {
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Self {
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offset,
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regs: unsafe { Gpio::new_mmio_fixed() },
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}
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}
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pub fn offset(&self) -> PinOffset {
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self.offset
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}
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/// Convert the pin into an output pin.
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pub fn configure_as_output_push_pull(&mut self, init_level: PinState) {
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let (offset, dirm, outen) = self.get_dirm_outen_regs_and_local_offset();
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if self.offset.is_mio() {
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// Tri-state bit must be 0 for the output driver to work.
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self.reconfigure_slcr_mio_cfg(false, None, Some(MuxConf::new_for_gpio()));
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}
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let mut curr_dirm = unsafe { core::ptr::read_volatile(dirm) };
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curr_dirm |= 1 << offset;
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unsafe { core::ptr::write_volatile(dirm, curr_dirm) };
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let mut curr_outen = unsafe { core::ptr::read_volatile(outen) };
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curr_outen |= 1 << offset;
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unsafe { core::ptr::write_volatile(outen, curr_outen) };
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// Unwrap okay, just set mode.
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self.write_state(init_level);
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}
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/// Convert the pin into an output pin with open drain emulation.
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///
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/// This works by only enabling the output driver when the pin is driven low and letting
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/// the pin float when it is driven high. A pin pull-up is used for MIO pins as well which
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/// pulls the pin to a defined state if it is not driven. This allows something like 1-wire bus
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/// operation because other devices can pull the pin low as well.
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///
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/// For EMIO pins, the pull-up and the IO buffer necessary for open-drain usage must be
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/// provided by the FPGA design.
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pub fn configure_as_output_open_drain(
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&mut self,
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init_level: PinState,
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with_internal_pullup: bool,
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) {
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let (offset, dirm, outen) = self.get_dirm_outen_regs_and_local_offset();
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if self.offset.is_mio() {
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// Tri-state bit must be 0 for the output driver to work. Enable the pullup pin.
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self.reconfigure_slcr_mio_cfg(
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false,
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Some(with_internal_pullup),
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Some(MuxConf::new_for_gpio()),
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);
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}
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let mut curr_dirm = unsafe { core::ptr::read_volatile(dirm) };
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curr_dirm |= 1 << offset;
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unsafe { core::ptr::write_volatile(dirm, curr_dirm) };
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// Disable the output driver depending on initial level.
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let mut curr_outen = unsafe { core::ptr::read_volatile(outen) };
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if init_level == PinState::High {
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curr_outen &= !(1 << offset);
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} else {
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curr_outen |= 1 << offset;
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self.write_state(init_level);
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}
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unsafe { core::ptr::write_volatile(outen, curr_outen) };
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}
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/// Convert the pin into a floating input pin.
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pub fn configure_as_input_floating(&mut self) -> Result<(), PinIsOutputOnly> {
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if self.offset.is_mio() {
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let offset_raw = self.offset.offset();
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if offset_raw == 7 || offset_raw == 8 {
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return Err(PinIsOutputOnly);
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}
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self.reconfigure_slcr_mio_cfg(true, Some(false), Some(MuxConf::new_for_gpio()));
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}
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self.configure_input_pin();
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Ok(())
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}
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/// Convert the pin into an input pin with a pull up.
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pub fn configure_as_input_with_pull_up(&mut self) -> Result<(), PinIsOutputOnly> {
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if self.offset.is_mio() {
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let offset_raw = self.offset.offset();
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if offset_raw == 7 || offset_raw == 8 {
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return Err(PinIsOutputOnly);
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}
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self.reconfigure_slcr_mio_cfg(true, Some(true), Some(MuxConf::new_for_gpio()));
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}
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self.configure_input_pin();
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Ok(())
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}
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/// Convert the pin into an IO peripheral pin.
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pub fn configure_as_io_periph_pin(&mut self, mux_conf: MuxConf, pullup: Option<bool>) {
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self.reconfigure_slcr_mio_cfg(false, pullup, Some(mux_conf));
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}
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#[inline]
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pub fn is_low(&self) -> bool {
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let (offset, in_reg) = self.get_data_in_reg_and_local_offset();
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let in_val = unsafe { core::ptr::read_volatile(in_reg) };
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((in_val >> offset) & 0b1) == 0
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}
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#[inline]
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pub fn is_high(&self) -> bool {
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!self.is_low()
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}
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#[inline]
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pub fn is_set_low(&self) -> bool {
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let (offset, out_reg) = self.get_data_out_reg_and_local_offset();
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let out_val = unsafe { core::ptr::read_volatile(out_reg) };
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((out_val >> offset) & 0b1) == 0
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}
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#[inline]
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pub fn is_set_high(&self) -> bool {
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!self.is_set_low()
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}
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#[inline]
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pub fn enable_output_driver(&mut self) {
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let (offset, _dirm, outen) = self.get_dirm_outen_regs_and_local_offset();
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let mut outen_reg = unsafe { core::ptr::read_volatile(outen) };
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outen_reg |= 1 << offset;
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unsafe { core::ptr::write_volatile(outen, outen_reg) };
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}
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#[inline]
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pub fn disable_output_driver(&mut self) {
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let (offset, _dirm, outen) = self.get_dirm_outen_regs_and_local_offset();
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let mut outen_reg = unsafe { core::ptr::read_volatile(outen) };
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outen_reg &= !(1 << offset);
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unsafe { core::ptr::write_volatile(outen, outen_reg) };
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}
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#[inline]
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pub fn set_low(&mut self) {
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self.write_state(PinState::Low)
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}
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#[inline]
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pub fn set_high(&mut self) {
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self.write_state(PinState::High)
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}
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#[inline]
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fn write_state(&mut self, level: PinState) {
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let (offset_in_reg, masked_out_ptr) = self.get_masked_out_reg_and_local_offset();
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unsafe {
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core::ptr::write_volatile(
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masked_out_ptr,
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MaskedOutput::builder()
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.with_mask(!(1 << offset_in_reg))
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.with_output((level as u16) << offset_in_reg)
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.build(),
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);
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}
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}
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fn reconfigure_slcr_mio_cfg(
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&mut self,
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tristate: bool,
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pullup: Option<bool>,
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mux_conf: Option<MuxConf>,
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) {
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let raw_offset = self.offset.offset();
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// Safety: We only modify the MIO config of the pin.
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let mut slcr_wrapper = unsafe { Slcr::steal() };
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// We read first, because writing also required unlocking the SLCR.
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// This allows the user to configure the SLCR themselves to avoid unnecessary
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// re-configuration which might also be potentially unsafe at run-time.
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let mio_cfg = slcr_wrapper.regs().read_mio_pins(raw_offset).unwrap();
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if (pullup.is_some() && mio_cfg.pullup() != pullup.unwrap())
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|| (mux_conf.is_some() && MuxConf::from(mio_cfg) != mux_conf.unwrap())
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|| tristate != mio_cfg.tri_enable()
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{
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slcr_wrapper.modify(|mut_slcr| {
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mut_slcr
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.modify_mio_pins(raw_offset, |mut val| {
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if let Some(pullup) = pullup {
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val.set_pullup(pullup);
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}
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if let Some(mux_conf) = mux_conf {
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val.set_l0_sel(mux_conf.l0_sel());
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val.set_l1_sel(mux_conf.l1_sel());
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val.set_l2_sel(mux_conf.l2_sel());
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val.set_l3_sel(mux_conf.l3_sel());
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}
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val.set_tri_enable(tristate);
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val
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})
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.unwrap();
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});
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}
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}
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fn configure_input_pin(&mut self) {
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let (offset, dirm, outen) = self.get_dirm_outen_regs_and_local_offset();
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let mut curr_dirm = unsafe { core::ptr::read_volatile(dirm) };
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curr_dirm &= !(1 << offset);
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unsafe { core::ptr::write_volatile(dirm, curr_dirm) };
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let mut curr_outen = unsafe { core::ptr::read_volatile(outen) };
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curr_outen &= !(1 << offset);
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unsafe { core::ptr::write_volatile(outen, curr_outen) };
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}
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#[inline(always)]
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fn get_data_in_reg_and_local_offset(&self) -> (usize, *mut u32) {
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match self.offset {
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PinOffset::Mio(offset) => match offset {
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0..=31 => (offset, self.regs.pointer_to_in_0()),
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32..=53 => (offset - 32, self.regs.pointer_to_in_1()),
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_ => panic!("invalid MIO pin offset"),
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},
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PinOffset::Emio(offset) => match offset {
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0..=31 => (offset, self.regs.pointer_to_in_2()),
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32..=63 => (offset - 32, self.regs.pointer_to_in_3()),
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_ => panic!("invalid EMIO pin offset"),
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},
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}
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}
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#[inline(always)]
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fn get_data_out_reg_and_local_offset(&self) -> (usize, *mut u32) {
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match self.offset {
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PinOffset::Mio(offset) => match offset {
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0..=31 => (offset, self.regs.pointer_to_out_0()),
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32..=53 => (offset - 32, self.regs.pointer_to_out_1()),
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_ => panic!("invalid MIO pin offset"),
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},
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PinOffset::Emio(offset) => match offset {
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0..=31 => (offset, self.regs.pointer_to_out_2()),
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32..=63 => (offset - 32, self.regs.pointer_to_out_3()),
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_ => panic!("invalid EMIO pin offset"),
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},
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}
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}
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#[inline(always)]
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fn get_dirm_outen_regs_and_local_offset(&self) -> (usize, *mut u32, *mut u32) {
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match self.offset {
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PinOffset::Mio(offset) => match offset {
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0..=31 => (
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offset,
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self.regs.bank_0_shared().pointer_to_dirm(),
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self.regs.bank_0_shared().pointer_to_out_en(),
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),
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32..=53 => (
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offset - 32,
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self.regs.bank_1_shared().pointer_to_dirm(),
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self.regs.bank_1_shared().pointer_to_out_en(),
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),
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_ => panic!("invalid MIO pin offset"),
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},
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PinOffset::Emio(offset) => match offset {
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0..=31 => (
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offset,
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self.regs.bank_2_shared().pointer_to_dirm(),
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self.regs.bank_2_shared().pointer_to_out_en(),
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),
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32..=63 => (
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offset - 32,
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self.regs.bank_3_shared().pointer_to_dirm(),
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self.regs.bank_3_shared().pointer_to_out_en(),
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),
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_ => panic!("invalid EMIO pin offset"),
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},
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}
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}
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#[inline(always)]
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fn get_masked_out_reg_and_local_offset(&mut self) -> (usize, *mut MaskedOutput) {
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match self.offset {
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PinOffset::Mio(offset) => match offset {
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0..=15 => (offset, self.regs.pointer_to_masked_out_0_lsw()),
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16..=31 => (offset - 16, self.regs.pointer_to_masked_out_0_msw()),
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32..=47 => (offset - 32, self.regs.pointer_to_masked_out_1_lsw()),
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48..=53 => (offset - 48, self.regs.pointer_to_masked_out_1_msw()),
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_ => panic!("invalid MIO pin offset"),
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},
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PinOffset::Emio(offset) => match offset {
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0..=15 => (offset, self.regs.pointer_to_masked_out_2_lsw()),
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16..=31 => (offset - 16, self.regs.pointer_to_masked_out_2_msw()),
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32..=47 => (offset - 32, self.regs.pointer_to_masked_out_3_lsw()),
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48..=63 => (offset - 48, self.regs.pointer_to_masked_out_3_msw()),
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_ => panic!("invalid EMIO pin offset"),
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},
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}
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}
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}
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