after some further deliberation, readability is more important

zynq7000/src/eth.rs

@@ -6,7 +6,7 @@ pub const GEM_1_BASE_ADDR: usize = 0xE000_C000;
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct NetworkCtrl {
+pub struct NetworkControl {
     #[bit(18, w)]
     flush_next_rx_dpram_pkt: bool,
     #[bit(17, w)]
@@ -56,7 +56,7 @@ pub enum PcsSelect {
 
 #[bitbybit::bitenum(u3, exhaustive = true)]
 #[derive(Debug, PartialEq, Eq)]
-pub enum MdcClkDiv {
+pub enum MdcClockDivisor {
     Div8 = 0,
     Div16 = 1,
     Div32 = 2,
@@ -67,24 +67,24 @@ pub enum MdcClkDiv {
     Div224 = 7,
 }
 
-impl MdcClkDiv {
+impl MdcClockDivisor {
     pub fn divisor(&self) -> usize {
         match self {
-            MdcClkDiv::Div8 => 8,
-            MdcClkDiv::Div16 => 16,
-            MdcClkDiv::Div32 => 32,
-            MdcClkDiv::Div48 => 48,
-            MdcClkDiv::Div64 => 64,
-            MdcClkDiv::Div96 => 96,
-            MdcClkDiv::Div128 => 128,
-            MdcClkDiv::Div224 => 224,
+            MdcClockDivisor::Div8 => 8,
+            MdcClockDivisor::Div16 => 16,
+            MdcClockDivisor::Div32 => 32,
+            MdcClockDivisor::Div48 => 48,
+            MdcClockDivisor::Div64 => 64,
+            MdcClockDivisor::Div96 => 96,
+            MdcClockDivisor::Div128 => 128,
+            MdcClockDivisor::Div224 => 224,
         }
     }
 }
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct NetworkCfg {
+pub struct NetworkConfig {
     #[bit(30, rw)]
     ignore_ipg_rx_error: bool,
     #[bit(29, rw)]
@@ -105,7 +105,7 @@ pub struct NetworkCfg {
     #[bits(21..=22, r)]
     dbus_width: u2,
     #[bits(18..=20, rw)]
-    mdc_clk_div: MdcClkDiv,
+    mdc_clk_div: MdcClockDivisor,
     #[bit(17, rw)]
     fcs_removal: bool,
     #[bit(16, rw)]
@@ -217,7 +217,7 @@ impl DmaRxBufSize {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct DmaCfg {
+pub struct DmaConfig {
     #[bit(24, rw)]
     discard_when_ahb_full: bool,
     /// DMA receive buffer size in AHB system memory.
@@ -340,7 +340,7 @@ pub struct InterruptStatus {
 
 #[bitbybit::bitfield(u32, default = 0x00)]
 #[derive(Debug)]
-pub struct InterruptCtrl {
+pub struct InterruptControl {
     #[bit(26, w)]
     tsu_sec_incr: bool,
     /// Marked N/A in datasheet. Probably because external PHYs are used.
@@ -380,7 +380,7 @@ pub struct InterruptCtrl {
     mgmt_frame_sent: bool,
 }
 
-impl InterruptCtrl {
+impl InterruptControl {
     pub fn new_clear_all() -> Self {
         Self::new_with_raw_value(0xFFFF_FFFF)
     }
@@ -430,19 +430,19 @@ pub struct MatchRegister {
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ethernet {
-    net_ctrl: NetworkCtrl,
-    net_cfg: NetworkCfg,
+    net_ctrl: NetworkControl,
+    net_cfg: NetworkConfig,
     #[mmio(PureRead)]
     net_status: NetworkStatus,
     _reserved0: u32,
-    dma_cfg: DmaCfg,
+    dma_cfg: DmaConfig,
     tx_status: TxStatus,
     rx_buf_queue_base_addr: u32,
     tx_buf_queue_base_addr: u32,
     rx_status: RxStatus,
     interrupt_status: InterruptStatus,
-    interrupt_enable: InterruptCtrl,
-    interrupt_disable: InterruptCtrl,
+    interrupt_enable: InterruptControl,
+    interrupt_disable: InterruptControl,
     interrupt_mask: InterruptStatus,
     phy_maintenance: PhyMaintenance,
     #[mmio(PureRead)]

zynq7000/src/gic.rs

@@ -5,7 +5,7 @@ use static_assertions::const_assert_eq;
 
 /// Distributor Control Register
 #[bitbybit::bitfield(u32, default = 0x0)]
-pub struct Dcr {
+pub struct DistributorControlRegister {
     #[bit(1, rw)]
     enable_non_secure: bool,
     #[bit(0, rw)]
@@ -14,7 +14,7 @@ pub struct Dcr {
 
 /// Read only bit. This register only returns fixed constants.
 #[bitbybit::bitfield(u32)]
-pub struct TypeReg {
+pub struct TypeRegister {
     #[bits(11..=15, r)]
     lspi: u5,
     #[bit(10, r)]
@@ -25,7 +25,7 @@ pub struct TypeReg {
     it_lines_number: u5,
 }
 
-impl TypeReg {
+impl TypeRegister {
     pub const SECURITY_EXTNS_BIT: bool = true;
     /// 31 LSPIs.
     pub const NUM_LSPI: usize = 0x1f;
@@ -38,14 +38,14 @@ impl TypeReg {
     pub const NUM_OF_INTERRUPTS: usize = 96;
 }
 
-pub type Typer = TypeReg;
+pub type Typer = TypeRegister;
 
 /// GIC Distributor registers.
 #[derive(derive_mmio::Mmio)]
 #[repr(C, align(8))]
 pub struct GicDistributor {
     /// Distributor Control Register
-    pub dcr: Dcr,
+    pub dcr: DistributorControlRegister,
     /// Interrupt Controller Type Register
     #[mmio(PureRead)]
     pub ictr: Typer,
@@ -128,7 +128,7 @@ impl GicDistributor {
 
 /// CPU interface control register.
 #[bitbybit::bitfield(u32, default = 0x0)]
-pub struct InterfaceCtrl {
+pub struct InterfaceControl {
     #[bit(4, rw)]
     sbpr: bool,
     #[bit(3, rw)]
@@ -143,7 +143,7 @@ pub struct InterfaceCtrl {
 
 /// Priority Mask Register
 #[bitbybit::bitfield(u32)]
-pub struct PriorityReg {
+pub struct PriorityRegister {
     #[bits(0..=7, rw)]
     priority: u8,
 }
@@ -163,9 +163,9 @@ pub struct InterruptSignalRegister {
 #[repr(C, align(8))]
 pub struct GicCpuInterface {
     /// CPU Interface Control Register (ICR).
-    pub icr: InterfaceCtrl,
+    pub icr: InterfaceControl,
     /// Interrupt Priority Mask Register.
-    pub pmr: PriorityReg,
+    pub pmr: PriorityRegister,
     /// Binary Point Register.
     pub bpr: u32,
     /// Interrupt Acknowledge Register.
@@ -173,7 +173,7 @@ pub struct GicCpuInterface {
     /// End of Interrupt Register.
     pub eoir: InterruptSignalRegister,
     /// Running Priority Register.
-    pub rpr: PriorityReg,
+    pub rpr: PriorityRegister,
     /// Highest Pending Interrupt Register.
     pub hpir: InterruptSignalRegister,
     /// Aliased Binary Point Register

zynq7000/src/gpio.rs

@@ -10,7 +10,7 @@ pub struct MaskedOutput {
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct BankCtrl {
+pub struct BankControl {
     /// Direction mode
     dirm: u32,
     /// Output enable
@@ -84,22 +84,22 @@ pub struct Gpio {
     _reserved_2: [u32; 101],
 
     #[mmio(Inner)]
-    bank_0: BankCtrl,
+    bank_0: BankControl,
 
     _reserved_3: [u32; 7],
 
     #[mmio(Inner)]
-    bank_1: BankCtrl,
+    bank_1: BankControl,
 
     _reserved_4: [u32; 7],
 
     #[mmio(Inner)]
-    bank_2: BankCtrl,
+    bank_2: BankControl,
 
     _reserved_5: [u32; 7],
 
     #[mmio(Inner)]
-    bank_3: BankCtrl,
+    bank_3: BankControl,
 }
 
 static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x2E8);

zynq7000/src/gtc.rs

@@ -3,7 +3,7 @@
 pub const GTC_BASE_ADDR: usize = super::mpcore::MPCORE_BASE_ADDR + 0x0000_0200;
 
 #[bitbybit::bitfield(u32)]
-pub struct GtcCtrl {
+pub struct GtcControl {
     #[bits(8..=15, rw)]
     prescaler: u8,
     #[bit(3, rw)]
@@ -31,7 +31,7 @@ pub struct GlobalTimerCounter {
     /// Count register 1, upper 32 bits
     count_upper: u32,
     /// Control register
-    ctrl: GtcCtrl,
+    ctrl: GtcControl,
     /// Interrupt status register
     #[mmio(PureRead, Write)]
     isr: InterruptStatus,

zynq7000/src/i2c.rs

@@ -6,7 +6,7 @@ pub const I2C_1_BASE_ADDR: usize = 0xE000_5000;
 
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[derive(Debug)]
-pub enum Dir {
+pub enum Direction {
     Receiver = 0b1,
     Transmitter = 0b0,
 }
@@ -19,7 +19,7 @@ pub enum Mode {
 }
 
 #[bitbybit::bitfield(u32, default = 0x0)]
-pub struct Ctrl {
+pub struct Control {
     /// Divides the input PCLK frequency by this value + 1
     #[bits(14..=15, rw)]
     div_a: u2,
@@ -44,7 +44,7 @@ pub struct Ctrl {
     #[bit(1, rw)]
     mode: Mode,
     #[bit(0, rw)]
-    dir: Dir,
+    dir: Direction,
 }
 
 #[bitbybit::bitfield(u32)]
@@ -66,7 +66,7 @@ pub struct Status {
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct Addr {
+pub struct Address {
     #[bits(0..=9, rw)]
     addr: u10,
 }
@@ -159,10 +159,10 @@ pub struct TransferSize {
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct I2c {
-    cr: Ctrl,
+    cr: Control,
     #[mmio(PureRead)]
     sr: Status,
-    addr: Addr,
+    addr: Address,
     #[mmio(Read, Write)]
     data: Fifo,
     #[mmio(PureRead, Write, Modify)]

zynq7000/src/l2_cache.rs

@@ -18,7 +18,7 @@ pub struct CacheSync {
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct DebugCtrl {
+pub struct DebugControl {
     #[bit(2, rw)]
     spniden: bool,
     #[bit(1, rw)]
@@ -41,9 +41,9 @@ pub struct CacheId {
 }
 
 #[repr(transparent)]
-pub struct Ctrl(u32);
+pub struct Control(u32);
 
-impl Ctrl {
+impl Control {
     pub fn new_enabled() -> Self {
         Self(0x1)
     }
@@ -87,7 +87,7 @@ pub enum Associativity {
 }
 
 #[bitbybit::bitfield(u32, default = 0x0)]
-pub struct AuxCtrl {
+pub struct AuxControl {
     #[bit(30, rw)]
     early_bresp_enable: bool,
     #[bit(29, rw)]
@@ -127,7 +127,7 @@ pub struct AuxCtrl {
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug, PartialEq, Eq)]
-pub struct LatencyCfg {
+pub struct LatencyConfig {
     /// Latency is the numerical value + 1 cycles.
     #[bits(8..=10, rw)]
     write_access_latency: u3,
@@ -165,7 +165,7 @@ pub struct InterruptStatus {
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct InterruptCtrl {
+pub struct InterruptControl {
     #[bit(8, w)]
     dec_error_l3: bool,
     #[bit(7, w)]
@@ -197,10 +197,10 @@ pub struct L2Cache {
 
     _reserved: [u32; 0x3E],
 
-    control: Ctrl,
-    aux_control: AuxCtrl,
-    tag_ram_latency: LatencyCfg,
-    data_ram_latency: LatencyCfg,
+    control: Control,
+    aux_control: AuxControl,
+    tag_ram_latency: LatencyConfig,
+    data_ram_latency: LatencyConfig,
 
     _reserved2: [u32; 0x3C],
 
@@ -215,7 +215,7 @@ pub struct L2Cache {
     #[mmio(PureRead)]
     interrupt_raw_status: InterruptStatus,
     #[mmio(Write)]
-    interrupt_clear: InterruptCtrl,
+    interrupt_clear: InterruptControl,
 
     _reserved3: [u32; 0x143],
 
@@ -264,7 +264,7 @@ pub struct L2Cache {
 
     _reserved13: [u32; 0xCE],
 
-    debug_control: DebugCtrl,
+    debug_control: DebugControl,
 
     _reserved14: [u32; 0x7],
 
@@ -278,7 +278,7 @@ pub struct L2Cache {
 static_assertions::const_assert_eq!(core::mem::size_of::<L2Cache>(), 0xF84);
 
 impl L2Cache {
-    /// Create a new L2C MMIO instance for for L2 Cache at address [I2C_0_BASE_ADDR].
+    /// Create a new L2C MMIO instance for for L2 Cache at address [L2C_BASE_ADDR].
     ///
     /// # Safety
     ///

zynq7000/src/mpcore.rs

@@ -15,7 +15,7 @@ pub const GICD_BASE_ADDR: usize = MPCORE_BASE_ADDR + 0x1000;
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Scu {
+pub struct SnoopControlUnit {
     ctrl: u32,
     config: u32,
     cpu_power_status: u32,
@@ -28,7 +28,7 @@ pub struct Scu {
     non_secure_access_ctrl: u32,
 }
 
-impl Scu {
+impl SnoopControlUnit {
     /// Create a new Snoop Control Unit interface at the fixed base address.
     ///
     /// # Safety
@@ -37,18 +37,18 @@ impl Scu {
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
     #[inline]
-    pub const unsafe fn new_mmio_fixed() -> MmioScu<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioSnoopControlUnit<'static> {
         unsafe { Self::new_mmio_at(SCU_BASE_ADDR) }
     }
 }
 
-const_assert_eq!(core::mem::size_of::<Scu>(), 0x58);
+const_assert_eq!(core::mem::size_of::<SnoopControlUnit>(), 0x58);
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Mpcore {
+pub struct MpCore {
     #[mmio(Inner)]
-    scu: Scu,
+    scu: SnoopControlUnit,
 
     _reserved_0: [u32; 0x2A],
 
@@ -80,9 +80,9 @@ pub struct Mpcore {
     gicd: GicDistributor,
 }
 
-const_assert_eq!(core::mem::size_of::<Mpcore>(), 0x2000);
+const_assert_eq!(core::mem::size_of::<MpCore>(), 0x2000);
 
-impl Mpcore {
+impl MpCore {
     /// Create a MP core peripheral interface at the fixed base address.
     ///
     /// # Safety
@@ -91,7 +91,7 @@ impl Mpcore {
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
     #[inline]
-    pub const unsafe fn new_mmio_fixed() -> MmioMpcore<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioMpCore<'static> {
         unsafe { Self::new_mmio_at(MPCORE_BASE_ADDR) }
     }
 }

zynq7000/src/slcr/clocks.rs

@@ -20,7 +20,7 @@ pub enum BypassQual {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct PllCtrl {
+pub struct PllControl {
     /// Feedback divisor for the PLL.
     ///
     /// NOTE: Before changing this value, the PLL must first be bypassed and then put into
@@ -43,7 +43,7 @@ pub struct PllCtrl {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct PllCfg {
+pub struct PllConfig {
     #[bits(12..=21, rw)]
     lock_count: u10,
     /// Charge Pump control
@@ -73,7 +73,7 @@ pub struct PllStatus {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct FpgaClkCtrl {
+pub struct FpgaClockControl {
     // Reset value 0x1
     #[bits(20..=25, rw)]
     divisor_1: u6,
@@ -86,14 +86,14 @@ pub struct FpgaClkCtrl {
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct FpgaClkCtrlBlock {
-    ctrl: FpgaClkCtrl,
+pub struct FpgaClockControlBlock {
+    ctrl: FpgaClockControl,
     thr_ctrl: u32,
     thr_cnt: u32,
     thr_status: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<FpgaClkCtrlBlock>(), 0x10);
+static_assertions::const_assert_eq!(core::mem::size_of::<FpgaClockControlBlock>(), 0x10);
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[derive(Debug)]
@@ -105,7 +105,7 @@ pub enum SrcSelArm {
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct ArmClkCtrl {
+pub struct ArmClockControl {
     #[bit(28, rw)]
     cpu_peri_clk_act: bool,
     #[bit(27, rw)]
@@ -126,7 +126,7 @@ pub struct ArmClkCtrl {
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct DdrClkCtrl {
+pub struct DdrClockControl {
     /// Divisor for DDR 2x clock. Reset value: 0x6
     #[bits(26..=31, rw)]
     div_2x_clk: u6,
@@ -142,7 +142,7 @@ pub struct DdrClkCtrl {
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct DciClkCtrl {
+pub struct DciClockControl {
     /// Second cascade divider. Reset value: 0x1E
     #[bits(20..=25, rw)]
     divisor_1: u6,
@@ -156,15 +156,15 @@ pub struct DciClkCtrl {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct ClkRatioSelectReg {
+pub struct ClockRatioSelectReg {
     /// Reset value: 0x1 (6:2:1 clock)
     #[bit(0, rw)]
-    sel: ClkRatioSelect,
+    sel: ClockkRatioSelect,
 }
 
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[derive(Debug)]
-pub enum ClkRatioSelect {
+pub enum ClockkRatioSelect {
     /// 4:2:1 clock ratio, which is an abbreviation for 4:2:2:1.
     FourToTwoToOne = 0b0,
     /// 6:2:1 clock ratio, which is an abbreviation for 6:3:2:1.
@@ -201,7 +201,7 @@ impl PartialEq for SrcSelIo {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct GigEthClkCtrl {
+pub struct GigEthClockControl {
     #[bits(20..=25, rw)]
     divisor_1: u6,
     #[bits(8..=13, rw)]
@@ -223,7 +223,7 @@ pub enum SrcSelGigEthRclk {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct GigEthRclkCtrl {
+pub struct GigEthRclkControl {
     #[bit(4, rw)]
     srcsel: SrcSelGigEthRclk,
     // Enable the ethernet controller RX clock.
@@ -233,7 +233,7 @@ pub struct GigEthRclkCtrl {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct CanClkCtrl {
+pub struct CanClockControl {
     #[bits(20..=25, rw)]
     divisor_1: u6,
     #[bits(8..=13, rw)]
@@ -247,7 +247,7 @@ pub struct CanClkCtrl {
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct SingleCommonPeriphIoClkCtrl {
+pub struct SingleCommonPeriphIoClockControl {
     #[bits(8..=13, rw)]
     divisor: u6,
     #[bits(4..=5, rw)]
@@ -258,7 +258,7 @@ pub struct SingleCommonPeriphIoClkCtrl {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct DualCommonPeriphIoClkCtrl {
+pub struct DualCommonPeriphIoClockControl {
     #[bits(8..=13, rw)]
     divisor: u6,
     #[bits(4..=5, rw)]
@@ -283,7 +283,7 @@ pub enum SrcSelTpiu {
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct TracePortClkCtrl {
+pub struct TracePortClockControl {
     #[bits(8..=13, rw)]
     divisor: u6,
     #[bits(4..=6, rw)]
@@ -299,7 +299,7 @@ pub struct TracePortClkCtrl {
 /// These clocks must be enabled if you want to read from the peripheral register space.
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct AperClkCtrl {
+pub struct AperClockControl {
     #[bit(24, rw)]
     smc_1x_clk_act: bool,
     #[bit(23, rw)]
@@ -341,46 +341,46 @@ pub struct AperClkCtrl {
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct ClockControl {
-    arm_pll: PllCtrl,
-    ddr_pll: PllCtrl,
-    io_pll: PllCtrl,
+    arm_pll: PllControl,
+    ddr_pll: PllControl,
+    io_pll: PllControl,
     pll_status: PllStatus,
-    arm_pll_cfg: PllCfg,
-    ddr_pll_cfg: PllCfg,
-    io_pll_cfg: PllCfg,
+    arm_pll_cfg: PllConfig,
+    ddr_pll_cfg: PllConfig,
+    io_pll_cfg: PllConfig,
     _gap0: u32,
-    arm_clk_ctrl: ArmClkCtrl,
-    ddr_clk_ctrl: DdrClkCtrl,
-    dci_clk_ctrl: DciClkCtrl,
+    arm_clk_ctrl: ArmClockControl,
+    ddr_clk_ctrl: DdrClockControl,
+    dci_clk_ctrl: DciClockControl,
     /// AMBA peripheral clock control
-    aper_clk_ctrl: AperClkCtrl,
+    aper_clk_ctrl: AperClockControl,
     usb_0_clk_ctrl: u32,
     usb_1_clk_ctrl: u32,
-    gem_0_rclk_ctrl: GigEthRclkCtrl,
-    gem_1_rclk_ctrl: GigEthRclkCtrl,
-    gem_0_clk_ctrl: GigEthClkCtrl,
-    gem_1_clk_ctrl: GigEthClkCtrl,
-    smc_clk_ctrl: SingleCommonPeriphIoClkCtrl,
-    lqspi_clk_ctrl: SingleCommonPeriphIoClkCtrl,
-    sdio_clk_ctrl: DualCommonPeriphIoClkCtrl,
-    uart_clk_ctrl: DualCommonPeriphIoClkCtrl,
-    spi_clk_ctrl: DualCommonPeriphIoClkCtrl,
-    can_clk_ctrl: CanClkCtrl,
+    gem_0_rclk_ctrl: GigEthRclkControl,
+    gem_1_rclk_ctrl: GigEthRclkControl,
+    gem_0_clk_ctrl: GigEthClockControl,
+    gem_1_clk_ctrl: GigEthClockControl,
+    smc_clk_ctrl: SingleCommonPeriphIoClockControl,
+    lqspi_clk_ctrl: SingleCommonPeriphIoClockControl,
+    sdio_clk_ctrl: DualCommonPeriphIoClockControl,
+    uart_clk_ctrl: DualCommonPeriphIoClockControl,
+    spi_clk_ctrl: DualCommonPeriphIoClockControl,
+    can_clk_ctrl: CanClockControl,
     can_mioclk_ctrl: u32,
     /// Debug or Trace Port clock control.
-    dbg_clk_ctrl: TracePortClkCtrl,
-    pcap_clk_ctrl: SingleCommonPeriphIoClkCtrl,
+    dbg_clk_ctrl: TracePortClockControl,
+    pcap_clk_ctrl: SingleCommonPeriphIoClockControl,
     topsw_clk_ctrl: u32,
     #[mmio(Inner)]
-    fpga_0_clk_ctrl: FpgaClkCtrlBlock,
+    fpga_0_clk_ctrl: FpgaClockControlBlock,
     #[mmio(Inner)]
-    fpga_1_clk_ctrl: FpgaClkCtrlBlock,
+    fpga_1_clk_ctrl: FpgaClockControlBlock,
     #[mmio(Inner)]
-    fpga_2_clk_ctrl: FpgaClkCtrlBlock,
+    fpga_2_clk_ctrl: FpgaClockControlBlock,
     #[mmio(Inner)]
-    fpga_3_clk_ctrl: FpgaClkCtrlBlock,
+    fpga_3_clk_ctrl: FpgaClockControlBlock,
     _gap1: [u32; 5],
-    clk_621_true: ClkRatioSelectReg,
+    clk_621_true: ClockRatioSelectReg,
 }
 
 impl ClockControl {

zynq7000/src/slcr/mod.rs

@@ -58,7 +58,7 @@ pub enum VrefSel {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct GpiobCtrl {
+pub struct GpiobControl {
     #[bit(11, rw)]
     vref_sw_en: bool,
     #[bits(4..=6, rw)]
@@ -70,7 +70,7 @@ pub struct GpiobCtrl {
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct GpiobRegisters {
-    ctrl: GpiobCtrl,
+    ctrl: GpiobControl,
     cfg_cmos18: u32,
     cfg_cmos25: u32,
     cfg_cmos33: u32,
@@ -95,7 +95,7 @@ impl GpiobRegisters {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct BootModeReg {
+pub struct BootModeRegister {
     #[bit(4, r)]
     pll_bypass: bool,
     #[bits(0..=3, r)]
@@ -104,16 +104,16 @@ pub struct BootModeReg {
 
 #[bitbybit::bitenum(u4)]
 #[derive(Debug, PartialEq, Eq)]
-pub enum LevelShifterCfg {
+pub enum LevelShifterConfig {
     DisableAll = 0x00,
     EnablePsToPl = 0xA,
     EnableAll = 0xF,
 }
 
 #[bitbybit::bitfield(u32)]
-pub struct LevelShifterReg {
+pub struct LevelShifterRegister {
     #[bits(0..=3, rw)]
-    user_lvl_shftr_en: Option<LevelShifterCfg>,
+    user_lvl_shftr_en: Option<LevelShifterConfig>,
 }
 
 /// System Level Control Registers
@@ -142,7 +142,7 @@ pub struct Slcr {
     _gap2: [u32; 0x02],
 
     reboot_status: u32,
-    boot_mode: BootModeReg,
+    boot_mode: BootModeRegister,
 
     _gap3: [u32; 0x28],
 
@@ -186,7 +186,7 @@ pub struct Slcr {
 
     _gap13: [u32; 0x32],
 
-    lvl_shftr_en: LevelShifterReg,
+    lvl_shftr_en: LevelShifterRegister,
 
     _gap14: [u32; 0x03],
 

zynq7000/src/slcr/reset.rs

@@ -2,7 +2,7 @@ use super::{RESET_BLOCK_OFFSET, SLCR_BASE_ADDR};
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct DualClkRst {
+pub struct DualClockReset {
     /// Peripheral 1 AMBA software reset.
     #[bit(1, rw)]
     periph1_cpu1x_rst: bool,
@@ -13,7 +13,7 @@ pub struct DualClkRst {
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct DualRefAndClkRst {
+pub struct DualRefAndClockReset {
     /// Periperal 1 Reference software reset.
     #[bit(3, rw)]
     periph1_ref_rst: bool,
@@ -30,14 +30,14 @@ pub struct DualRefAndClkRst {
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct GpioClkRst {
+pub struct GpioClockReset {
     #[bit(0, rw)]
     gpio_cpu1x_rst: bool,
 }
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct EthernetRst {
+pub struct EthernetReset {
     #[bit(5, rw)]
     gem1_ref_rst: bool,
     #[bit(4, rw)]
@@ -62,13 +62,13 @@ pub struct ResetControl {
     topsw: u32,
     dmac: u32,
     usb: u32,
-    eth: EthernetRst,
-    sdio: DualRefAndClkRst,
-    spi: DualRefAndClkRst,
-    can: DualClkRst,
-    i2c: DualClkRst,
-    uart: DualRefAndClkRst,
-    gpio: GpioClkRst,
+    eth: EthernetReset,
+    sdio: DualRefAndClockReset,
+    spi: DualRefAndClockReset,
+    can: DualClockReset,
+    i2c: DualClockReset,
+    uart: DualRefAndClockReset,
+    gpio: GpioClockReset,
     lqspi: u32,
     smc: u32,
     ocm: u32,

zynq7000/src/spi.rs

@@ -33,7 +33,7 @@ impl BaudDivSel {
 
 #[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
-pub struct Cfg {
+pub struct Config {
     #[bit(17, rw)]
     modefail_gen_en: bool,
     #[bit(16, w)]
@@ -182,7 +182,7 @@ pub struct DelayControl {
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Spi {
-    cr: Cfg,
+    cr: Config,
     #[mmio(PureRead, Write)]
     isr: InterruptStatus,
     /// Interrupt Enable Register.

zynq7000/src/ttc.rs

@@ -14,7 +14,7 @@ pub enum ClockSource {
 }
 
 #[bitbybit::bitfield(u32, default = 0x0)]
-pub struct ClkCtrl {
+pub struct ClockControl {
     /// When this bit is set and the external clock is selected, the counter clocks on the
     /// negative edge of the external clock input.
     #[bit(6, rw)]
@@ -146,7 +146,7 @@ pub struct EventCount {
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ttc {
-    clk_cntr: [ClkCtrl; 3],
+    clk_cntr: [ClockControl; 3],
     cnt_ctrl: [CounterControl; 3],
     #[mmio(PureRead)]
     current_counter: [Counter; 3],

zynq7000/src/uart.rs

@@ -20,7 +20,7 @@ pub enum Parity {
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[derive(Default, Debug, PartialEq, Eq)]
-pub enum Chrl {
+pub enum CharLen {
     SixBits = 0b11,
     SevenBits = 0b10,
     #[default]
@@ -30,7 +30,7 @@ pub enum Chrl {
 
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[derive(Default, Debug, PartialEq, Eq)]
-pub enum ClkSel {
+pub enum ClockSelect {
     #[default]
     UartRefClk = 0b0,
     UartRefClkDiv8 = 0b1,
@@ -57,7 +57,7 @@ pub enum ChMode {
 
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
-pub struct Ctrl {
+pub struct Control {
     /// Stop transmitter break.
     #[bit(8, rw)]
     stopbrk: bool,
@@ -98,9 +98,9 @@ pub struct Mode {
     par: Parity,
     /// Char length.
     #[bits(1..=2, rw)]
-    chrl: Chrl,
+    chrl: CharLen,
     #[bit(0, rw)]
-    clksel: ClkSel,
+    clksel: ClockSelect,
 }
 
 #[bitbybit::bitfield(u32, default = 0x0)]
@@ -287,7 +287,7 @@ impl InterruptStatus {
 #[repr(C)]
 pub struct Uart {
     /// Control Register
-    cr: Ctrl,
+    cr: Control,
     /// Mode register
     mr: Mode,
     /// Interrupt enable register