Ethernet and smoltcp/embassy-net support

zynq7000-hal/src/eth/embassy_net.rs

@@ -228,15 +228,16 @@ impl embassy_net_driver::RxToken for EmbassyNetRxToken<'_> {
         // The DMA will write the received frame into DDR. The L1 and L2 cache lines for the
         // particular reception address need to be invalidated, to avoid fetching stale data from
         // the cache instead of the DDR.
-        // TODO: For some reason, we have to do a clean and invalidate here. Just invalidating
-        // is not sufficient or leads to weird issues with ICMP pings..
         let clean_invalidate_len = (self.rx_size + CACHE_LINE_SIZE - 1) & !(CACHE_LINE_SIZE - 1);
         invalidate_data_cache_range(self.rx_buf.0.as_ptr() as u32, clean_invalidate_len)
             .expect("RX buffer or buffer size not aligned to cache line size");
-        //log::debug!("eth rx {} bytes", self.rx_size);
-        //log::trace!("rx data: {:x?}", &self.rx_buf.0[0..self.rx_size]);
+        log::debug!("eth rx {} bytes", self.rx_size);
+        log::trace!("rx data: {:x?}", &self.rx_buf.0[0..self.rx_size]);
         let result = f(&mut self.rx_buf.0[0..self.rx_size]);
         self.descr_list.clear_slot(self.slot_index);
+        // Okay, this is weird, but we have to do this. I encountered this bug where ICMP replies
+        // were duplicated after the descriptor rings wrapped. My theory is that there is
+        // some data in the cache after the embassy reception function which needs to be cleaned.
         clean_and_invalidate_data_cache_range(self.rx_buf.0.as_ptr() as u32, clean_invalidate_len)
             .expect("RX buffer or buffer size not aligned to cache line size");
         result
@@ -257,14 +258,8 @@ impl embassy_net_driver::TxToken for EmbassyNetTxToken<'_> {
         assert!(len <= super::MTU, "packet length exceeds MTU");
         // In the transmit call, it was checked that the buffer queue actually is not full.
         let tx_idx = self.descr_list.current_tx_idx();
-        //log::info!("eth tx on idx {tx_idx}");
-        //let slots = self.tx_bufs.len();
-        // let tx_bufs_base = self.tx_bufs.as_ptr() as u32;
-        //let tx_bufs_len = size_of_val(self.tx_bufs);
         let buffer = self.tx_bufs.get_mut(tx_idx).unwrap();
         let addr = buffer.0.as_ptr() as u32;
-        //clean_and_invalidate_data_cache_range(tx_bufs_base, tx_bufs_len)
-        //.expect("TX buffer or buffer size not aligned to cache line size");
         let result = f(&mut buffer.0[0..len]);
         let clean_invalidate_len = (len + CACHE_LINE_SIZE - 1) & !(CACHE_LINE_SIZE - 1);
         // DMA accesses the DDR memory directly, so we need to flush everything that might