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zynq7000-rt: small bugs in startup code #26

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muellerr merged 2 commits from mohr/fixes into main 2025-11-28 14:52:04 +01:00
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mohr commented 2025-11-28 13:31:47 +01:00
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  • MMU was enabled before MMU table (within .data) was copied into place. No effect in this configuration because MMU table was already in place as the code is run from RAM: > DATA AT>CODE is reduced to > CODE by REGION_ALIAS("DATA", CODE); in memory.x.
  • Added shortcut if .data is already in place as this should be the default case for zynq (.data will be in RAM and loaded by FSBL as part of the binary)
  • r1 was used to mask CPSR but was overwritten in previous step -> replaced by write to cpsr_c (which masks the correct bits).
  • Minor nitpicking: .addr() is more correct than as u32 (see docs)
- MMU was enabled before MMU table (within .data) was copied into place. No effect in this configuration because MMU table was already in place as the code is run from RAM: ` > DATA AT>CODE` is reduced to `> CODE` by `REGION_ALIAS("DATA", CODE);` in memory.x. - Added shortcut if .data is already in place as this should be the default case for zynq (.data will be in RAM and loaded by FSBL as part of the binary) - r1 was used to mask CPSR but was overwritten in previous step -> replaced by write to `cpsr_c` (which masks the correct bits). - Minor nitpicking: `.addr()` is more correct than `as u32` (see [docs](https://doc.rust-lang.org/std/primitive.pointer.html#method.addr))
mohr added 1 commit 2025-11-28 13:31:48 +01:00
zynq7000-rt: small bugs in startup code
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muellerr commented 2025-11-28 14:04:33 +01:00
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Are those bugs in the Xilinx startup files as well then? Because a lot of the stuff is copied from the XIlinx startup..

I'll check the xilinx startup code again.

Are those bugs in the Xilinx startup files as well then? Because a lot of the stuff is copied from the XIlinx startup.. I'll check the xilinx startup code again.
mohr commented 2025-11-28 14:07:04 +01:00
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Negative, Xilinx has the MMU table as section in the linker (no copy needed) and reloads r1 before masking CPSR.

Negative, Xilinx has the MMU table as section in the linker (no copy needed) and reloads r1 before masking CPSR.
muellerr commented 2025-11-28 14:18:20 +01:00
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That must have been lost when merging the aarch32 rt and the xilinx specific code.

That must have been lost when merging the aarch32 rt and the xilinx specific code.
muellerr commented 2025-11-28 14:32:46 +01:00
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LGTM and thanks for finding this! Can you update the CHANGELOG?

LGTM and thanks for finding this! Can you update the CHANGELOG?
mohr added 1 commit 2025-11-28 14:50:02 +01:00
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muellerr merged commit 0235e1d769 into main 2025-11-28 14:52:04 +01:00
muellerr deleted branch mohr/fixes 2025-11-28 14:52:04 +01:00
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Reference: rust/zynq7000-rs#26
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