89 lines
2.0 KiB
VHDL
89 lines
2.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: Institute of Space Systems, University of Stuttgart
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-- Engineer: Robin Mueller
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--
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-- Description:
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-- The module multiplexes three UART modules.
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-- It can be used to select between UART0 through EMIO, UARTLITE or UART16550.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity uart_mux is
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port(
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sys_clk : in std_logic;
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uart_0_tx : in std_logic;
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uart_0_rx : out std_logic;
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uart_1_tx : in std_logic;
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uart_1_rx : out std_logic;
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uart_2_tx : in std_logic;
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uart_2_rx : out std_logic;
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tx_out: out std_logic;
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rx_in: in std_logic;
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-- "000" -> UART0
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-- "001" -> UART1
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-- "010" -> UART2
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-- "011" -> UART0 to UART1
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-- "100" -> UART0 to UART2
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-- "101" -> UART1 to UART2
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sel : in std_logic_vector(2 downto 0)
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);
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end uart_mux;
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architecture Behavioral of uart_mux is
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begin
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switch : process(sys_clk)
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begin
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if rising_edge(sys_clk) then
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case sel is
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when "000" =>
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tx_out <= uart_0_tx;
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uart_0_rx <= rx_in;
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uart_1_rx <= '1';
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uart_2_rx <= '1';
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when "001" =>
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tx_out <= uart_1_tx;
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uart_1_rx <= rx_in;
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uart_2_rx <= '1';
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uart_0_rx <= '1';
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when "010" =>
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tx_out <= uart_2_tx;
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uart_2_rx <= rx_in;
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uart_1_rx <= '1';
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uart_0_rx <= '1';
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when "011" =>
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tx_out <= '1';
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uart_1_rx <= uart_0_tx;
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uart_0_rx <= uart_1_tx;
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uart_2_rx <= '1';
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when "100" =>
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tx_out <= '1';
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uart_2_rx <= uart_0_tx;
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uart_0_rx <= uart_2_tx;
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uart_1_rx <= '1';
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when "101" =>
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tx_out <= '1';
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uart_1_rx <= uart_2_tx;
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uart_2_rx <= uart_1_tx;
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uart_0_rx <= '1';
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when others =>
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tx_out <= '1';
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uart_0_rx <= '1';
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uart_1_rx <= '1';
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uart_2_rx <= '1';
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end case;
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end if;
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end process; -- switch
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end Behavioral;
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