270 lines
8.2 KiB
Rust
270 lines
8.2 KiB
Rust
#![no_std]
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#![no_main]
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use axi_uart16550::AxiUart16550;
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use axi_uartlite::AxiUartlite;
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use core::panic::PanicInfo;
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use cortex_ar::asm::nop;
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use embassy_executor::Spawner;
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use embassy_time::{Duration, Ticker};
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use embedded_hal::digital::StatefulOutputPin;
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use embedded_io::Write;
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use fugit::RateExtU32;
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use log::{error, info};
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use zedboard::PS_CLOCK_FREQUENCY;
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use zynq7000_hal::{
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BootMode,
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clocks::Clocks,
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configure_level_shifter,
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gic::{GicConfigurator, GicInterruptHelper, Interrupt},
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gpio::{EmioPin, GpioPins, PinState},
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gtc::Gtc,
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uart::{ClkConfigRaw, Uart, UartConfig},
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};
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use zynq7000::{PsPeripherals, slcr::LevelShifterConfig};
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use zynq7000_rt as _;
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const INIT_STRING: &str = "-- Zynq 7000 Zedboard blocking UART example --\n\r";
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const AXI_UARTLITE_BASE_ADDR: u32 = 0x42C0_0000;
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const AXI_UAR16550_BASE_ADDR: u32 = 0x43C0_0000;
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/// Entry point (not called like a normal main function)
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#[unsafe(no_mangle)]
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pub extern "C" fn boot_core(cpu_id: u32) -> ! {
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if cpu_id != 0 {
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panic!("unexpected CPU ID {}", cpu_id);
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}
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main();
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}
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#[derive(Debug, Copy, Clone, PartialEq)]
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pub enum UartSel {
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Uart0 = 0b000,
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Uartlite = 0b001,
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Uart16550 = 0b010,
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Uart0ToUartlite = 0b011,
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Uart0ToUart16550 = 0b100,
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UartliteToUart16550 = 0b101,
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}
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pub struct UartMultiplexer {
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sel_pins: [EmioPin; 3],
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}
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impl UartMultiplexer {
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pub fn new(mut sel_pins: [EmioPin; 3]) -> Self {
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for pin in sel_pins.iter_mut() {
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pin.into_output(PinState::Low);
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}
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Self { sel_pins }
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}
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pub fn select(&mut self, sel: UartSel) {
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// TODO: A pin group switcher would be nice to do this in one go.
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match sel {
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UartSel::Uart0 => {
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self.sel_pins[2].set_low().unwrap();
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self.sel_pins[1].set_low().unwrap();
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self.sel_pins[0].set_low().unwrap();
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}
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UartSel::Uartlite => {
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self.sel_pins[2].set_low().unwrap();
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self.sel_pins[1].set_low().unwrap();
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self.sel_pins[0].set_high().unwrap();
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}
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UartSel::Uart16550 => {
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self.sel_pins[2].set_low().unwrap();
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self.sel_pins[1].set_high().unwrap();
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self.sel_pins[0].set_low().unwrap();
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}
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UartSel::Uart0ToUartlite => {
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self.sel_pins[2].set_low().unwrap();
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self.sel_pins[1].set_high().unwrap();
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self.sel_pins[0].set_high().unwrap();
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}
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UartSel::Uart0ToUart16550 => {
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self.sel_pins[2].set_high().unwrap();
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self.sel_pins[1].set_low().unwrap();
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self.sel_pins[0].set_low().unwrap();
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}
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UartSel::UartliteToUart16550 => {
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self.sel_pins[2].set_high().unwrap();
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self.sel_pins[1].set_low().unwrap();
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self.sel_pins[0].set_high().unwrap();
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}
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}
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}
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}
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#[embassy_executor::main]
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#[unsafe(export_name = "main")]
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async fn main(_spawner: Spawner) -> ! {
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// Enable PS-PL level shifters.
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configure_level_shifter(LevelShifterConfig::EnableAll);
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let dp = PsPeripherals::take().unwrap();
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// Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
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let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
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// Set up the global interrupt controller.
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let mut gic = GicConfigurator::new_with_init(dp.gicc, dp.gicd);
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gic.enable_all_interrupts();
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gic.set_all_spi_interrupt_targets_cpu0();
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gic.enable();
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unsafe {
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gic.enable_interrupts();
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}
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let mut gpio_pins = GpioPins::new(dp.gpio);
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// Set up global timer counter and embassy time driver.
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let gtc = Gtc::new(dp.gtc, clocks.arm_clocks());
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zynq7000_embassy::init(clocks.arm_clocks(), gtc);
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// Set up the UART, we are logging with it.
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let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200)
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.unwrap()
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.0;
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let uart_tx = gpio_pins.mio.mio48.into_uart();
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let uart_rx = gpio_pins.mio.mio49.into_uart();
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let mut log_uart = Uart::new_with_mio(
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dp.uart_1,
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UartConfig::new_with_clk_config(uart_clk_config),
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(uart_tx, uart_rx),
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)
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.unwrap();
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log_uart.write_all(INIT_STRING.as_bytes()).unwrap();
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// Safety: Co-operative multi-tasking is used.
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unsafe {
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zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
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log_uart,
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log::LevelFilter::Trace,
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false,
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)
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};
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// UART0 routed through EMIO to PL pins.
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let mut uart_0 =
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Uart::new_with_emio(dp.uart_0, UartConfig::new_with_clk_config(uart_clk_config)).unwrap();
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// Safety: Valid address of AXI UARTLITE.
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let mut uartlite = unsafe { AxiUartlite::new(AXI_UARTLITE_BASE_ADDR) };
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// TODO: Can we determine/read the clock frequency to the FPGAs as well?
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let (clk_config, error) =
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axi_uart16550::ClkConfig::new_autocalc_with_error(100.MHz(), 115200).unwrap();
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assert!(error < 0.02);
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let mut uart_16550 = unsafe {
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AxiUart16550::new(
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AXI_UAR16550_BASE_ADDR,
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axi_uart16550::UartConfig::new_with_clk_config(clk_config),
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)
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};
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let boot_mode = BootMode::new();
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info!("Boot mode: {:?}", boot_mode);
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let mut ticker = Ticker::every(Duration::from_millis(1000));
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let mut mio_led = gpio_pins.mio.mio7.into_output(PinState::Low);
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let mut emio_leds: [EmioPin; 8] = [
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gpio_pins.emio.take(0).unwrap(),
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gpio_pins.emio.take(1).unwrap(),
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gpio_pins.emio.take(2).unwrap(),
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gpio_pins.emio.take(3).unwrap(),
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gpio_pins.emio.take(4).unwrap(),
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gpio_pins.emio.take(5).unwrap(),
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gpio_pins.emio.take(6).unwrap(),
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gpio_pins.emio.take(7).unwrap(),
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];
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for led in emio_leds.iter_mut() {
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led.into_output(PinState::Low);
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}
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let mut uart_mux = UartMultiplexer::new([
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gpio_pins.emio.take(8).unwrap(),
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gpio_pins.emio.take(9).unwrap(),
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gpio_pins.emio.take(10).unwrap(),
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]);
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let mut current_sel = UartSel::Uart0;
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uart_mux.select(current_sel);
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let mut led_idx = 0;
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loop {
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mio_led.toggle().unwrap();
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emio_leds[led_idx].toggle().unwrap();
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led_idx += 1;
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if led_idx >= emio_leds.len() {
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led_idx = 0;
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}
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uart_0
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.write_all("Hello, World from UART0!\n\r".as_bytes())
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.unwrap();
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uartlite
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.write_all("Hello, World from AXI UARTLITE!\n\r".as_bytes())
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.unwrap();
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uart_16550
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.write_all("Hello, World from AXI UART16550!\n\r".as_bytes())
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.unwrap();
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uart_0.flush().unwrap();
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uartlite.flush().unwrap();
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uart_16550.flush().unwrap();
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match current_sel {
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UartSel::Uart0 => current_sel = UartSel::Uartlite,
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UartSel::Uartlite => current_sel = UartSel::Uart16550,
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UartSel::Uart16550 => current_sel = UartSel::Uart0,
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UartSel::Uart0ToUartlite | UartSel::Uart0ToUart16550 | UartSel::UartliteToUart16550 => {
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}
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}
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uart_mux.select(current_sel);
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ticker.next().await; // Wait for the next cycle of the ticker
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}
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _irq_handler() {
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let mut gic_helper = GicInterruptHelper::new();
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let irq_info = gic_helper.acknowledge_interrupt();
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match irq_info.interrupt() {
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Interrupt::Sgi(_) => (),
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Interrupt::Ppi(ppi_interrupt) => {
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if ppi_interrupt == zynq7000_hal::gic::PpiInterrupt::GlobalTimer {
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unsafe {
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zynq7000_embassy::on_interrupt();
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}
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}
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}
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Interrupt::Spi(_spi_interrupt) => (),
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Interrupt::Invalid(_) => (),
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Interrupt::Spurious => (),
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}
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gic_helper.end_of_interrupt(irq_info);
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _abort_handler() {
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loop {
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nop();
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}
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _undefined_handler() {
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loop {
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nop();
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}
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _prefetch_handler() {
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loop {
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nop();
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}
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}
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/// Panic handler
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#[panic_handler]
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fn panic(info: &PanicInfo) -> ! {
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error!("Panic: {:?}", info);
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loop {}
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}
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