1032 lines
32 KiB
Rust
1032 lines
32 KiB
Rust
use core::convert::Infallible;
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use crate::clocks::Clocks;
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use crate::enable_amba_peripheral_clock;
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use crate::gpio::{
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IoPeriph, IoPeriphPin, Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31,
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Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, MioPin, MuxConf,
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};
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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use crate::gpio::{
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Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27, Mio40,
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Mio41, Mio42, Mio43, Mio44, Mio45, Mio46, Mio47, Mio48, Mio49, Mio50, Mio51,
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};
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use crate::{clocks::IoClocks, slcr::Slcr, time::Hertz};
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use arbitrary_int::{Number, u3, u4, u6};
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use embedded_hal::delay::DelayNs;
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pub use embedded_hal::spi::Mode;
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use embedded_hal::spi::{MODE_0, MODE_1, MODE_2, MODE_3, SpiBus as _};
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use zynq7000::slcr::reset::DualRefAndClockReset;
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use zynq7000::spi::{
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BaudDivSelect, DelayControl, FifoWrite, MmioSpi, SPI_0_BASE_ADDR, SPI_1_BASE_ADDR,
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};
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pub const FIFO_DEPTH: usize = 128;
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pub const MODULE_ID: u32 = 0x90106;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum SpiId {
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Spi0,
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Spi1,
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}
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pub trait PsSpi {
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fn reg_block(&self) -> MmioSpi<'static>;
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fn id(&self) -> Option<SpiId>;
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}
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impl PsSpi for MmioSpi<'static> {
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#[inline]
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fn reg_block(&self) -> MmioSpi<'static> {
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unsafe { self.clone() }
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}
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#[inline]
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fn id(&self) -> Option<SpiId> {
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let base_addr = unsafe { self.ptr() } as usize;
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if base_addr == SPI_0_BASE_ADDR {
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return Some(SpiId::Spi0);
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} else if base_addr == SPI_1_BASE_ADDR {
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return Some(SpiId::Spi1);
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}
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None
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}
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}
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pub trait SckPin: IoPeriphPin {
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const SPI: SpiId;
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const GROUP: usize;
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}
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pub trait MosiPin: IoPeriphPin {
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const SPI: SpiId;
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const GROUP: usize;
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}
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pub trait MisoPin: IoPeriphPin {
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const SPI: SpiId;
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const GROUP: usize;
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}
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pub trait SsPin: IoPeriphPin {
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const IDX: usize;
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const SPI: SpiId;
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const GROUP: usize;
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}
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pub const SPI_MUX_CONF: MuxConf = MuxConf::new_with_l3(u3::new(0b101));
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macro_rules! impl_into_spi {
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(($($Mio:ident),+)) => {
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$(
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impl<M: $crate::gpio::PinMode> MioPin<$Mio, M> {
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/// Convert the pin into SPI pins by configuring the pin routing via the
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/// MIO multiplexer bits. Also disables pull-ups for the pins.
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pub fn into_spi(self) -> MioPin<$Mio, IoPeriph> {
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self.into_io_periph(SPI_MUX_CONF, Some(false))
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}
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}
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)+
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};
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl_into_spi!((
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Mio16, Mio21, Mio17, Mio18, Mio19, Mio20, Mio40, Mio45, Mio41, Mio42, Mio43, Mio44, Mio24,
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Mio22, Mio23, Mio25, Mio26, Mio27, Mio48, Mio46, Mio47, Mio49, Mio50, Mio51
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));
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impl_into_spi!((
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Mio28, Mio33, Mio29, Mio30, Mio31, Mio32, Mio12, Mio10, Mio11, Mio13, Mio14, Mio15, Mio36,
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Mio34, Mio35, Mio37, Mio38, Mio39
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));
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// SPI0, choice 1
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SckPin for MioPin<Mio16, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MosiPin for MioPin<Mio21, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MisoPin for MioPin<Mio17, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio18, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 0;
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const IDX: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio19, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 0;
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const IDX: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio20, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 0;
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const IDX: usize = 2;
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}
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// SPI0, choice 2
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impl SckPin for MioPin<Mio28, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 1;
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}
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impl MosiPin for MioPin<Mio33, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 1;
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}
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impl MisoPin for MioPin<Mio29, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 1;
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}
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impl SsPin for MioPin<Mio30, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 1;
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const IDX: usize = 0;
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}
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impl SsPin for MioPin<Mio31, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 1;
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const IDX: usize = 1;
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}
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impl SsPin for MioPin<Mio32, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 1;
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const IDX: usize = 2;
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}
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// SPI0, choice 3
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SckPin for MioPin<Mio40, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 2;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MosiPin for MioPin<Mio45, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 2;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MisoPin for MioPin<Mio41, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 2;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio42, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 2;
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const IDX: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio43, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 2;
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const IDX: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio44, IoPeriph> {
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const SPI: SpiId = SpiId::Spi0;
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const GROUP: usize = 2;
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const IDX: usize = 2;
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}
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// SPI1, choice 1
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impl SckPin for MioPin<Mio12, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 0;
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}
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impl MosiPin for MioPin<Mio10, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 0;
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}
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impl MisoPin for MioPin<Mio11, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 0;
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}
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impl SsPin for MioPin<Mio13, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 0;
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const IDX: usize = 0;
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}
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impl SsPin for MioPin<Mio14, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 0;
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const IDX: usize = 1;
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}
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impl SsPin for MioPin<Mio15, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 0;
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const IDX: usize = 2;
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}
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// SPI1, choice 2
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SckPin for MioPin<Mio24, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MosiPin for MioPin<Mio22, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MisoPin for MioPin<Mio23, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio25, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 1;
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const IDX: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio26, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 1;
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const IDX: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio27, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 1;
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const IDX: usize = 2;
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}
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// SPI1, choice 2
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impl SckPin for MioPin<Mio36, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 2;
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}
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impl MosiPin for MioPin<Mio34, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 2;
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}
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impl MisoPin for MioPin<Mio35, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 2;
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}
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impl SsPin for MioPin<Mio37, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 2;
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const IDX: usize = 0;
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}
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impl SsPin for MioPin<Mio38, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 2;
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const IDX: usize = 1;
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}
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impl SsPin for MioPin<Mio39, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 2;
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const IDX: usize = 2;
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}
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// SPI1, choice 3
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SckPin for MioPin<Mio48, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 3;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MosiPin for MioPin<Mio46, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 3;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl MisoPin for MioPin<Mio47, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 3;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio49, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 3;
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const IDX: usize = 0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio50, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 3;
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const IDX: usize = 1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl SsPin for MioPin<Mio51, IoPeriph> {
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const SPI: SpiId = SpiId::Spi1;
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const GROUP: usize = 3;
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const IDX: usize = 2;
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}
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum ChipSelect {
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Slave0,
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Slave1,
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Slave2,
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Decoded { cs0: bool, cs1: bool, cs2: bool },
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None,
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}
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impl ChipSelect {
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pub const fn raw_reg(&self) -> u4 {
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u4::new(match self {
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ChipSelect::Slave0 => 0b0000,
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ChipSelect::Slave1 => 0b0001,
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ChipSelect::Slave2 => 0b0010,
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ChipSelect::None => 0b1111,
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ChipSelect::Decoded { cs0, cs1, cs2 } => {
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(1 << 3) | (*cs0 as u8) | ((*cs1 as u8) << 1) | ((*cs2 as u8) << 2)
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}
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})
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}
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#[inline]
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pub const fn cs_no_ext_decoding(&self, raw: u4) -> Option<ChipSelect> {
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let val = raw.value();
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if val == 0b1111 {
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return Some(ChipSelect::None);
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}
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if val & 0b1 == 0 {
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return Some(ChipSelect::Slave0);
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} else if val & 0b11 == 0b01 {
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return Some(ChipSelect::Slave1);
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} else if val & 0b111 == 0b010 {
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return Some(ChipSelect::Slave2);
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}
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None
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}
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}
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#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)]
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/// Slave select configuration.
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pub enum SlaveSelectConfig {
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/// User must take care of controlling slave select lines as well as issuing a start command.
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ManualWithManualStart = 0b11,
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ManualAutoStart = 0b10,
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/// Hardware slave select, but start needs to be issued manually.
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AutoWithManualStart = 0b01,
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/// Hardware slave select, auto serialiation if there is data in the TX FIFO.
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#[default]
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AutoWithAutoStart = 0b00,
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}
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pub struct Config {
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baud_div: BaudDivSelect,
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init_mode: Mode,
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ss_config: SlaveSelectConfig,
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with_ext_decoding: bool,
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}
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impl Config {
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pub fn new(baud_div: BaudDivSelect, init_mode: Mode, ss_config: SlaveSelectConfig) -> Self {
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Self {
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baud_div,
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init_mode,
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ss_config,
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with_ext_decoding: false,
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}
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}
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pub fn enable_external_decoding(&mut self) {
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self.with_ext_decoding = true;
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}
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}
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/// Blocking Driver for the PS SPI peripheral in master mode.
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pub struct Spi {
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regs: zynq7000::spi::MmioSpi<'static>,
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sclk: Hertz,
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config: Config,
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outstanding_rx: bool,
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}
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#[derive(Debug, thiserror::Error)]
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#[error("invalid SPI ID")]
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pub struct InvalidPsSpiError;
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// TODO: Add and handle MUX config check.
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#[derive(Debug, thiserror::Error)]
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pub enum SpiConstructionError {
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#[error("invalid SPI ID {0}")]
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InvalidPsSpi(#[from] InvalidPsSpiError),
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/// The specified pins are not compatible to the specified SPI peripheral.
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#[error("pin invalid for SPI ID")]
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PinInvalidForSpiId,
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/// The specified pins are not from the same pin group.
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#[error("pin group missmatch")]
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GroupMissmatch,
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#[error("invalid pin configuration for SPI")]
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InvalidPinConf,
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}
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impl Spi {
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pub fn new_no_hw_ss<Sck: SckPin, Mosi: MosiPin, Miso: MisoPin>(
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spi: impl PsSpi,
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clocks: &IoClocks,
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config: Config,
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spi_pins: (Sck, Mosi, Miso),
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) -> Result<Self, SpiConstructionError> {
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let spi_id = spi.id();
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if spi_id.is_none() {
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return Err(InvalidPsSpiError.into());
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}
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let spi_id = spi_id.unwrap();
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if Sck::GROUP != Mosi::GROUP || Sck::GROUP != Miso::GROUP {
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return Err(SpiConstructionError::GroupMissmatch);
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}
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if Sck::SPI != spi_id || Mosi::SPI != spi_id || Miso::SPI != spi_id {
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return Err(SpiConstructionError::PinInvalidForSpiId);
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}
|
|
if spi_pins.0.mux_conf() != SPI_MUX_CONF
|
|
|| spi_pins.0.mux_conf() != spi_pins.2.mux_conf()
|
|
|| spi_pins.1.mux_conf() != spi_pins.2.mux_conf()
|
|
{
|
|
return Err(SpiConstructionError::InvalidPinConf);
|
|
}
|
|
Ok(Self::new_generic_unchecked(
|
|
spi_id,
|
|
spi.reg_block(),
|
|
clocks,
|
|
config,
|
|
))
|
|
}
|
|
|
|
pub fn new_one_hw_cs<Sck: SckPin, Mosi: MosiPin, Miso: MisoPin, Ss: SsPin>(
|
|
spi: impl PsSpi,
|
|
clocks: &IoClocks,
|
|
config: Config,
|
|
spi_pins: (Sck, Mosi, Miso),
|
|
ss_pin: Ss,
|
|
) -> Result<Self, SpiConstructionError> {
|
|
let spi_id = spi.id();
|
|
if spi_id.is_none() {
|
|
return Err(InvalidPsSpiError.into());
|
|
}
|
|
let spi_id = spi_id.unwrap();
|
|
if Sck::GROUP != Mosi::GROUP || Sck::GROUP != Miso::GROUP || Sck::GROUP != Ss::GROUP {
|
|
return Err(SpiConstructionError::GroupMissmatch);
|
|
}
|
|
if Sck::SPI != spi_id || Mosi::SPI != spi_id || Miso::SPI != spi_id || Ss::SPI != spi_id {
|
|
return Err(SpiConstructionError::PinInvalidForSpiId);
|
|
}
|
|
if spi_pins.0.mux_conf() != SPI_MUX_CONF
|
|
|| spi_pins.0.mux_conf() != spi_pins.2.mux_conf()
|
|
|| spi_pins.1.mux_conf() != spi_pins.2.mux_conf()
|
|
|| ss_pin.mux_conf() != spi_pins.0.mux_conf()
|
|
{
|
|
return Err(SpiConstructionError::InvalidPinConf);
|
|
}
|
|
Ok(Self::new_generic_unchecked(
|
|
spi_id,
|
|
spi.reg_block(),
|
|
clocks,
|
|
config,
|
|
))
|
|
}
|
|
|
|
pub fn new_with_two_hw_cs<Sck: SckPin, Mosi: MosiPin, Miso: MisoPin, Ss0: SsPin, Ss1: SsPin>(
|
|
spi: impl PsSpi,
|
|
clocks: &IoClocks,
|
|
config: Config,
|
|
spi_pins: (Sck, Mosi, Miso),
|
|
ss_pins: (Ss0, Ss1),
|
|
) -> Result<Self, SpiConstructionError> {
|
|
let spi_id = spi.id();
|
|
if spi_id.is_none() {
|
|
return Err(InvalidPsSpiError.into());
|
|
}
|
|
let spi_id = spi_id.unwrap();
|
|
if Sck::GROUP != Mosi::GROUP
|
|
|| Sck::GROUP != Miso::GROUP
|
|
|| Sck::GROUP != Ss0::GROUP
|
|
|| Sck::GROUP != Ss1::GROUP
|
|
{
|
|
return Err(SpiConstructionError::GroupMissmatch);
|
|
}
|
|
if Sck::SPI != spi_id
|
|
|| Mosi::SPI != spi_id
|
|
|| Miso::SPI != spi_id
|
|
|| Ss0::SPI != spi_id
|
|
|| Ss1::SPI != spi_id
|
|
{
|
|
return Err(SpiConstructionError::PinInvalidForSpiId);
|
|
}
|
|
if spi_pins.0.mux_conf() != SPI_MUX_CONF
|
|
|| spi_pins.0.mux_conf() != spi_pins.2.mux_conf()
|
|
|| spi_pins.1.mux_conf() != spi_pins.2.mux_conf()
|
|
|| ss_pins.0.mux_conf() != spi_pins.0.mux_conf()
|
|
|| ss_pins.1.mux_conf() != spi_pins.0.mux_conf()
|
|
{
|
|
return Err(SpiConstructionError::InvalidPinConf);
|
|
}
|
|
Ok(Self::new_generic_unchecked(
|
|
spi_id,
|
|
spi.reg_block(),
|
|
clocks,
|
|
config,
|
|
))
|
|
}
|
|
|
|
pub fn new_with_three_hw_cs<
|
|
Sck: SckPin,
|
|
Mosi: MosiPin,
|
|
Miso: MisoPin,
|
|
Ss0: SsPin,
|
|
Ss1: SsPin,
|
|
Ss2: SsPin,
|
|
>(
|
|
spi: impl PsSpi,
|
|
clocks: &IoClocks,
|
|
config: Config,
|
|
spi_pins: (Sck, Mosi, Miso),
|
|
ss_pins: (Ss0, Ss1, Ss2),
|
|
) -> Result<Self, SpiConstructionError> {
|
|
let spi_id = spi.id();
|
|
if spi_id.is_none() {
|
|
return Err(InvalidPsSpiError.into());
|
|
}
|
|
let spi_id = spi_id.unwrap();
|
|
if Sck::GROUP != Mosi::GROUP
|
|
|| Sck::GROUP != Miso::GROUP
|
|
|| Sck::GROUP != Ss0::GROUP
|
|
|| Sck::GROUP != Ss1::GROUP
|
|
|| Sck::GROUP != Ss2::GROUP
|
|
{
|
|
return Err(SpiConstructionError::GroupMissmatch);
|
|
}
|
|
if Sck::SPI != spi_id
|
|
|| Mosi::SPI != spi_id
|
|
|| Miso::SPI != spi_id
|
|
|| Ss0::SPI != spi_id
|
|
|| Ss1::SPI != spi_id
|
|
|| Ss2::SPI != spi_id
|
|
{
|
|
return Err(SpiConstructionError::PinInvalidForSpiId);
|
|
}
|
|
if spi_pins.0.mux_conf() != SPI_MUX_CONF
|
|
|| spi_pins.0.mux_conf() != spi_pins.2.mux_conf()
|
|
|| spi_pins.1.mux_conf() != spi_pins.2.mux_conf()
|
|
|| ss_pins.0.mux_conf() != spi_pins.0.mux_conf()
|
|
|| ss_pins.1.mux_conf() != spi_pins.0.mux_conf()
|
|
|| ss_pins.2.mux_conf() != spi_pins.2.mux_conf()
|
|
{
|
|
return Err(SpiConstructionError::InvalidPinConf);
|
|
}
|
|
Ok(Self::new_generic_unchecked(
|
|
spi_id,
|
|
spi.reg_block(),
|
|
clocks,
|
|
config,
|
|
))
|
|
}
|
|
|
|
pub fn new_generic_unchecked(
|
|
id: SpiId,
|
|
mut regs: MmioSpi<'static>,
|
|
clocks: &IoClocks,
|
|
config: Config,
|
|
) -> Self {
|
|
let periph_sel = match id {
|
|
SpiId::Spi0 => crate::PeripheralSelect::Spi0,
|
|
SpiId::Spi1 => crate::PeripheralSelect::Spi1,
|
|
};
|
|
enable_amba_peripheral_clock(periph_sel);
|
|
reset(id);
|
|
regs.write_enable(0);
|
|
let (man_ss, man_start) = match config.ss_config {
|
|
SlaveSelectConfig::ManualWithManualStart => (true, true),
|
|
SlaveSelectConfig::ManualAutoStart => (true, false),
|
|
SlaveSelectConfig::AutoWithManualStart => (false, true),
|
|
SlaveSelectConfig::AutoWithAutoStart => (false, false),
|
|
};
|
|
let (cpol, cpha) = match config.init_mode {
|
|
MODE_0 => (false, false),
|
|
MODE_1 => (false, true),
|
|
MODE_2 => (true, false),
|
|
MODE_3 => (true, true),
|
|
};
|
|
|
|
regs.write_cr(
|
|
zynq7000::spi::Config::builder()
|
|
.with_modefail_gen_en(false)
|
|
.with_manual_start(false)
|
|
.with_manual_start_enable(man_start)
|
|
.with_manual_cs(man_ss)
|
|
.with_cs_raw(ChipSelect::None.raw_reg())
|
|
.with_peri_sel(config.with_ext_decoding)
|
|
.with_baud_rate_div(config.baud_div)
|
|
.with_cpha(cpha)
|
|
.with_cpol(cpol)
|
|
.with_master_ern(true)
|
|
.build(),
|
|
);
|
|
// Configures for polling mode by default: TX trigger by one will lead to the
|
|
// TX FIFO not full signal being set when the TX FIFO is emtpy.
|
|
regs.write_tx_trig(1);
|
|
// Same as TX.
|
|
regs.write_rx_trig(1);
|
|
|
|
regs.write_enable(1);
|
|
let sclk = clocks.spi_clk() / config.baud_div.div_value() as u32;
|
|
Self {
|
|
regs,
|
|
sclk,
|
|
config,
|
|
outstanding_rx: false,
|
|
}
|
|
}
|
|
|
|
/// Retrieve SCLK clock frequency currently configured for this SPI.
|
|
#[inline]
|
|
pub const fn sclk(&self) -> Hertz {
|
|
self.sclk
|
|
}
|
|
|
|
#[inline]
|
|
pub fn regs(&mut self) -> &mut MmioSpi<'static> {
|
|
&mut self.regs
|
|
}
|
|
|
|
/// Select the peripheral chip select line.
|
|
///
|
|
/// This needs to be done before starting a transfer to select the correct peripheral chip
|
|
/// select line.
|
|
///
|
|
/// The decoder bits logic is is based
|
|
/// [on online documentation](https://www.realdigital.org/doc/3eb4f7a05e5003f2e0e6858a27a679bb?utm_source=chatgpt.com)
|
|
/// because the TRM does not specify how decoding really works. This also only works if
|
|
/// the external decoding was enabled via the [Config::enable_external_decoding] option.
|
|
#[inline]
|
|
pub fn select_hw_cs(&mut self, chip_select: ChipSelect) {
|
|
self.regs.modify_cr(|mut val| {
|
|
val.set_cs_raw(chip_select.raw_reg());
|
|
val
|
|
});
|
|
}
|
|
|
|
/// Re-configures the mode register.
|
|
#[inline]
|
|
pub fn configure_mode(&mut self, mode: Mode) {
|
|
let (cpol, cpha) = match mode {
|
|
MODE_0 => (false, false),
|
|
MODE_1 => (false, true),
|
|
MODE_2 => (true, false),
|
|
MODE_3 => (true, true),
|
|
};
|
|
self.regs.modify_cr(|mut val| {
|
|
val.set_cpha(cpha);
|
|
val.set_cpha(cpol);
|
|
val
|
|
});
|
|
}
|
|
|
|
/// Re-configures the delay control register.
|
|
#[inline]
|
|
pub fn configure_delays(&mut self, config: DelayControl) {
|
|
self.regs.write_delay_control(config)
|
|
}
|
|
|
|
/// No peripheral slave selection.
|
|
#[inline]
|
|
pub fn no_hw_cs(&mut self) {
|
|
self.select_hw_cs(ChipSelect::None);
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn write_fifo_unchecked(&mut self, data: u8) {
|
|
self.regs
|
|
.write_txd(FifoWrite::new_with_raw_value(data as u32));
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn read_fifo_unchecked(&mut self) -> u8 {
|
|
self.regs.read_rxd().data()
|
|
}
|
|
|
|
#[inline]
|
|
pub fn issue_manual_start(&mut self) {
|
|
self.regs.modify_cr(|mut val| {
|
|
val.set_manual_start(true);
|
|
val
|
|
});
|
|
}
|
|
|
|
#[inline]
|
|
pub fn issue_manual_start_for_manual_cfg(&mut self) {
|
|
if self.config.ss_config == SlaveSelectConfig::AutoWithManualStart
|
|
|| self.config.ss_config == SlaveSelectConfig::ManualWithManualStart
|
|
{
|
|
self.issue_manual_start();
|
|
}
|
|
}
|
|
|
|
fn initial_fifo_fill(&mut self, words: &[u8]) -> usize {
|
|
let write_len = core::cmp::min(FIFO_DEPTH, words.len());
|
|
(0..write_len).for_each(|idx| {
|
|
self.write_fifo_unchecked(words[idx]);
|
|
});
|
|
write_len
|
|
}
|
|
|
|
fn prepare_generic_blocking_transfer(&mut self, words: &[u8]) -> usize {
|
|
// We want to ensure the FIFO is empty for a new transfer. This is the simpler
|
|
// implementation for now.
|
|
self.flush().unwrap();
|
|
// Write this to 1 in any case to allow polling, defensive programming.
|
|
self.regs.write_rx_trig(1);
|
|
|
|
// Fill the FIFO with initial data.
|
|
let written = self.initial_fifo_fill(words);
|
|
|
|
// We assume that the slave select configuration was already performed, but we take
|
|
// care of issuing a start if necessary.
|
|
self.issue_manual_start_for_manual_cfg();
|
|
written
|
|
}
|
|
}
|
|
|
|
impl embedded_hal::spi::ErrorType for Spi {
|
|
type Error = Infallible;
|
|
}
|
|
|
|
impl embedded_hal::spi::SpiBus for Spi {
|
|
fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
if words.is_empty() {
|
|
return Ok(());
|
|
}
|
|
// We want to ensure the FIFO is empty for a new transfer. This is the simpler
|
|
// implementation for now.
|
|
self.flush()?;
|
|
// Write this to 1 in any case to allow polling, defensive programming.
|
|
self.regs.write_rx_trig(1);
|
|
|
|
let mut write_idx = core::cmp::min(FIFO_DEPTH, words.len());
|
|
// Send dummy bytes.
|
|
(0..write_idx).for_each(|_| {
|
|
self.write_fifo_unchecked(0);
|
|
});
|
|
|
|
// We assume that the slave select configuration was already performed, but we take
|
|
// care of issuing a start if necessary.
|
|
self.issue_manual_start_for_manual_cfg();
|
|
|
|
let mut read_idx = 0;
|
|
while read_idx < words.len() {
|
|
let status = self.regs.read_sr();
|
|
if status.rx_not_empty() {
|
|
words[read_idx] = self.read_fifo_unchecked();
|
|
read_idx += 1;
|
|
}
|
|
// Continue pumping the FIFO if necesary and possible.
|
|
if write_idx < words.len() && !status.tx_full() {
|
|
self.write_fifo_unchecked(0);
|
|
write_idx += 1;
|
|
}
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
|
if words.is_empty() {
|
|
return Ok(());
|
|
}
|
|
let mut written = self.prepare_generic_blocking_transfer(words);
|
|
let mut read_idx = 0;
|
|
|
|
while written < words.len() {
|
|
let status = self.regs.read_sr();
|
|
// We empty the FIFO to prevent it filling up completely, as long as we have to write
|
|
// bytes
|
|
if status.rx_not_empty() {
|
|
self.read_fifo_unchecked();
|
|
read_idx += 1;
|
|
}
|
|
if !status.tx_full() {
|
|
self.write_fifo_unchecked(words[written]);
|
|
written += 1;
|
|
}
|
|
}
|
|
// We exit once all bytes have been written, so some bytes to read might be outstanding.
|
|
// We use the FIFO trigger mechanism to determine when we can read all the remaining bytes.
|
|
self.regs.write_rx_trig((words.len() - read_idx) as u32);
|
|
self.outstanding_rx = true;
|
|
Ok(())
|
|
}
|
|
|
|
fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
|
|
if read.is_empty() {
|
|
return Ok(());
|
|
}
|
|
let mut write_idx = self.prepare_generic_blocking_transfer(write);
|
|
let mut read_idx = 0;
|
|
|
|
let mut writes_finished = write_idx == write.len();
|
|
let mut reads_finished = false;
|
|
while !writes_finished || !reads_finished {
|
|
let status = self.regs.read_sr();
|
|
if status.rx_not_empty() && !reads_finished {
|
|
read[read_idx] = self.read_fifo_unchecked();
|
|
read_idx += 1;
|
|
}
|
|
|
|
if !status.tx_full() && !writes_finished {
|
|
self.write_fifo_unchecked(write[write_idx]);
|
|
write_idx += 1;
|
|
}
|
|
writes_finished = write_idx == write.len();
|
|
reads_finished = read_idx == write.len();
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
if words.is_empty() {
|
|
return Ok(());
|
|
}
|
|
let mut write_idx = self.prepare_generic_blocking_transfer(words);
|
|
let mut read_idx = 0;
|
|
|
|
let mut writes_finished = write_idx == words.len();
|
|
let mut reads_finished = false;
|
|
while !writes_finished || !reads_finished {
|
|
let status = self.regs.read_sr();
|
|
if status.rx_not_empty() && !reads_finished {
|
|
words[read_idx] = self.read_fifo_unchecked();
|
|
read_idx += 1;
|
|
}
|
|
|
|
if !status.tx_full() && !writes_finished {
|
|
self.write_fifo_unchecked(words[write_idx]);
|
|
write_idx += 1;
|
|
}
|
|
writes_finished = write_idx == words.len();
|
|
reads_finished = read_idx == words.len();
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
if !self.outstanding_rx {
|
|
return Ok(());
|
|
}
|
|
let rx_trig = self.regs.read_rx_trig();
|
|
while !self.regs.read_sr().rx_not_empty() {}
|
|
(0..rx_trig).for_each(|_| {
|
|
self.regs.read_rxd();
|
|
});
|
|
self.regs.write_rx_trig(1);
|
|
self.outstanding_rx = false;
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
pub struct SpiWithHwCs<Delay: DelayNs> {
|
|
pub spi: Spi,
|
|
pub cs: ChipSelect,
|
|
pub delay: Delay,
|
|
}
|
|
|
|
impl<Delay: DelayNs> SpiWithHwCs<Delay> {
|
|
pub fn new(spi: Spi, cs: ChipSelect, delay: Delay) -> Self {
|
|
Self { spi, cs, delay }
|
|
}
|
|
|
|
pub fn release(self) -> Spi {
|
|
self.spi
|
|
}
|
|
}
|
|
|
|
impl<Delay: DelayNs> embedded_hal::spi::ErrorType for SpiWithHwCs<Delay> {
|
|
type Error = Infallible;
|
|
}
|
|
|
|
impl<Delay: DelayNs> embedded_hal::spi::SpiDevice for SpiWithHwCs<Delay> {
|
|
fn transaction(
|
|
&mut self,
|
|
operations: &mut [embedded_hal::spi::Operation<'_, u8>],
|
|
) -> Result<(), Self::Error> {
|
|
self.spi.select_hw_cs(self.cs);
|
|
for op in operations {
|
|
match op {
|
|
embedded_hal::spi::Operation::Read(items) => {
|
|
self.spi.read(items)?;
|
|
}
|
|
embedded_hal::spi::Operation::Write(items) => {
|
|
self.spi.write(items)?;
|
|
}
|
|
embedded_hal::spi::Operation::Transfer(read, write) => {
|
|
self.spi.transfer(read, write)?;
|
|
}
|
|
embedded_hal::spi::Operation::TransferInPlace(items) => {
|
|
self.spi.transfer_in_place(items)?;
|
|
}
|
|
embedded_hal::spi::Operation::DelayNs(delay) => {
|
|
self.delay.delay_ns(*delay);
|
|
}
|
|
}
|
|
}
|
|
self.spi.flush()?;
|
|
self.spi.no_hw_cs();
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
/// Reset the SPI peripheral using the SLCR reset register for SPI.
|
|
///
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/// Please note that this function will interfere with an already configured
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/// SPI instance.
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#[inline]
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pub fn reset(id: SpiId) {
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let assert_reset = match id {
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SpiId::Spi0 => DualRefAndClockReset::builder()
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.with_periph1_ref_rst(false)
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.with_periph0_ref_rst(true)
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.with_periph1_cpu1x_rst(false)
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.with_periph0_cpu1x_rst(true)
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.build(),
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SpiId::Spi1 => DualRefAndClockReset::builder()
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.with_periph1_ref_rst(true)
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.with_periph0_ref_rst(false)
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.with_periph1_cpu1x_rst(true)
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.with_periph0_cpu1x_rst(false)
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.build(),
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};
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unsafe {
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Slcr::with(|regs| {
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regs.reset_ctrl().write_spi(assert_reset);
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// Keep it in reset for some cycles.. The TMR just mentions some small delay,
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// no idea what is meant with that.
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for _ in 0..3 {
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cortex_ar::asm::nop();
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}
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regs.reset_ctrl().write_spi(DualRefAndClockReset::DEFAULT);
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});
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}
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}
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/// Calculates the largest allowed SPI reference clock divisor.
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///
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/// The Zynq7000 SPI peripheral has the following requirement for the SPI reference clock:
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/// It must be larger than the CPU 1X clock. Therefore, the divisor used to calculate the reference
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/// clock has a maximum value, which can be calculated with this function.
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///
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/// [configure_spi_ref_clk] can be used to configure the SPI reference clock with the calculated
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/// value.
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pub fn calculate_largest_allowed_spi_ref_clk_divisor(clks: &Clocks) -> Option<u6> {
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let mut slcr = unsafe { Slcr::steal() };
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let spi_clk_ctrl = slcr.regs().clk_ctrl().read_spi_clk_ctrl();
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let div = match spi_clk_ctrl.srcsel() {
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zynq7000::slcr::clocks::SrcSelIo::IoPll | zynq7000::slcr::clocks::SrcSelIo::IoPllAlt => {
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clks.io_clocks().ref_clk() / clks.arm_clocks().cpu_1x_clk()
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}
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zynq7000::slcr::clocks::SrcSelIo::ArmPll => {
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clks.arm_clocks().ref_clk() / clks.arm_clocks().cpu_1x_clk()
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}
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zynq7000::slcr::clocks::SrcSelIo::DdrPll => {
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clks.ddr_clocks().ref_clk() / clks.arm_clocks().cpu_1x_clk()
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}
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};
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if div > u6::MAX.value() as u32 {
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return None;
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}
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|
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Some(u6::new(div as u8))
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}
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|
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pub fn configure_spi_ref_clk(clks: &mut Clocks, divisor: u6) {
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let mut slcr = unsafe { Slcr::steal() };
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let spi_clk_ctrl = slcr.regs().clk_ctrl().read_spi_clk_ctrl();
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slcr.modify(|regs| {
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regs.clk_ctrl().modify_spi_clk_ctrl(|mut val| {
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val.set_divisor(divisor);
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val
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|
});
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|
});
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|
let new_clk = match spi_clk_ctrl.srcsel() {
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zynq7000::slcr::clocks::SrcSelIo::IoPll | zynq7000::slcr::clocks::SrcSelIo::IoPllAlt => {
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|
clks.io_clocks().ref_clk() / divisor.value() as u32
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|
}
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|
zynq7000::slcr::clocks::SrcSelIo::ArmPll => {
|
|
clks.arm_clocks().ref_clk() / divisor.value() as u32
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|
}
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|
zynq7000::slcr::clocks::SrcSelIo::DdrPll => {
|
|
clks.ddr_clocks().ref_clk() / divisor.value() as u32
|
|
}
|
|
};
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|
clks.io_clocks_mut().update_spi_clk(new_clk);
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|
}
|