Robin Mueller
38e2109e52
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229 lines
7.6 KiB
Rust
229 lines
7.6 KiB
Rust
//! # HAL for the AMD Zynq 7000 SoC family
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//!
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//! This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional
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//! hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq7000).
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//!
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//! It is the result of reading the datasheet for the device and encoding a type-safe layer over the
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//! raw PAC. This crate also implements traits specified by the
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//! [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
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//! various drivers in the embedded rust ecosystem.
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#![no_std]
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#[cfg(feature = "alloc")]
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extern crate alloc;
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use slcr::Slcr;
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use zynq7000::{
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SpiClockPhase, SpiClockPolarity,
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slcr::{BootModeRegister, BootPllConfig, LevelShifterRegister},
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};
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pub mod cache;
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pub mod clocks;
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pub mod ddr;
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pub mod eth;
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pub mod gic;
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pub mod gpio;
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pub mod gtc;
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pub mod i2c;
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pub mod l2_cache;
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pub mod log;
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pub mod prelude;
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pub mod priv_tim;
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pub mod devcfg;
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pub mod qspi;
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pub mod slcr;
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pub mod spi;
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pub mod time;
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pub mod ttc;
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pub mod uart;
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/// This enumeration encodes the various boot sources.
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#[derive(Debug, Copy, Clone)]
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pub enum BootDevice {
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JtagCascaded,
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JtagIndependent,
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Nor,
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Nand,
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Qspi,
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SdCard,
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}
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#[derive(Debug, Copy, Clone)]
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pub struct BootMode {
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boot_mode: Option<BootDevice>,
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pll_config: BootPllConfig,
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}
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impl BootMode {
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/// Create a new boot mode information structure by reading the boot mode register from the
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/// fixed SLCR block.
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pub fn new_from_regs() -> Self {
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// Safety: Only read a read-only register here.
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Self::new_with_reg(unsafe { zynq7000::slcr::Slcr::new_mmio_fixed() }.read_boot_mode())
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}
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fn new_with_reg(boot_mode_reg: BootModeRegister) -> Self {
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let boot_dev = boot_mode_reg.boot_mode();
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let msb_three_bits = (boot_dev.value() >> 1) & 0b111;
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let boot_mode = match msb_three_bits {
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0b000 => {
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if boot_dev.value() & 0b1 == 0 {
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Some(BootDevice::JtagCascaded)
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} else {
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Some(BootDevice::JtagIndependent)
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}
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}
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0b001 => Some(BootDevice::Nor),
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0b010 => Some(BootDevice::Nand),
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0b100 => Some(BootDevice::Qspi),
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0b110 => Some(BootDevice::SdCard),
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_ => None,
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};
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Self {
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boot_mode,
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pll_config: boot_mode_reg.pll_config(),
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}
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}
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pub const fn boot_device(&self) -> Option<BootDevice> {
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self.boot_mode
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}
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pub const fn pll_config(&self) -> BootPllConfig {
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self.pll_config
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}
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}
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/// This configures the level shifters between the programmable logic (PL) and the processing
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/// system (PS).
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///
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/// The Zynq-7000 TRM p.32 specifies more information about this register and how to use it.
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pub fn configure_level_shifter(config: zynq7000::slcr::LevelShifterConfig) {
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// Safety: We only manipulate the level shift registers.
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unsafe {
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Slcr::with(|slcr_unlocked| {
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slcr_unlocked
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.write_lvl_shftr_en(LevelShifterRegister::new_with_raw_value(config as u32));
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});
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}
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}
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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pub enum PeriphSelect {
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Smc = 24,
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Lqspi = 23,
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Gpio = 22,
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Uart1 = 21,
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Uart0 = 20,
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I2c1 = 19,
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I2c0 = 18,
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Can1 = 17,
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Can0 = 16,
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Spi1 = 15,
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Spi0 = 14,
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Sdio1 = 11,
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Sdio0 = 10,
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Gem1 = 7,
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Gem0 = 6,
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Usb1 = 3,
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Usb0 = 2,
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Dma = 0,
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}
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/// Enable the AMBA peripheral clock, which is required to read the registers of a peripheral
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/// block.
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#[inline]
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pub fn enable_amba_peripheral_clock(select: PeriphSelect) {
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unsafe {
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Slcr::with(|regs| {
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regs.clk_ctrl().modify_aper_clk_ctrl(|mut val| {
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match select {
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PeriphSelect::Smc => val.set_smc_1x_clk_act(true),
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PeriphSelect::Lqspi => val.set_lqspi_1x_clk_act(true),
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PeriphSelect::Gpio => val.set_gpio_1x_clk_act(true),
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PeriphSelect::Uart1 => val.set_uart_1_1x_clk_act(true),
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PeriphSelect::Uart0 => val.set_uart_0_1x_clk_act(true),
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PeriphSelect::I2c1 => val.set_i2c_1_1x_clk_act(true),
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PeriphSelect::I2c0 => val.set_i2c_0_1x_clk_act(true),
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PeriphSelect::Can1 => val.set_can_1_1x_clk_act(true),
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PeriphSelect::Can0 => val.set_can_0_1x_clk_act(true),
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PeriphSelect::Spi1 => val.set_spi_1_1x_clk_act(true),
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PeriphSelect::Spi0 => val.set_spi_1_1x_clk_act(true),
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PeriphSelect::Sdio1 => val.set_sdio_1_1x_clk_act(true),
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PeriphSelect::Sdio0 => val.set_sdio_0_1x_clk_act(true),
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PeriphSelect::Gem1 => val.set_gem_1_1x_clk_act(true),
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PeriphSelect::Gem0 => val.set_gem_0_1x_clk_act(true),
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PeriphSelect::Usb1 => val.set_usb_1_cpu_1x_clk_act(true),
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PeriphSelect::Usb0 => val.set_usb_0_cpu_1x_clk_act(true),
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PeriphSelect::Dma => val.set_dma_cpu_2x_clk_act(true),
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}
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val
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})
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});
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}
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}
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/// Disable the AMBA peripheral clock, which is required to read the registers of a peripheral
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/// block.
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#[inline]
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pub fn disable_amba_periph_clk(select: PeriphSelect) {
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unsafe {
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Slcr::with(|regs| {
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regs.clk_ctrl().modify_aper_clk_ctrl(|mut val| {
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match select {
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PeriphSelect::Smc => val.set_smc_1x_clk_act(false),
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PeriphSelect::Lqspi => val.set_lqspi_1x_clk_act(false),
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PeriphSelect::Gpio => val.set_gpio_1x_clk_act(false),
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PeriphSelect::Uart1 => val.set_uart_1_1x_clk_act(false),
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PeriphSelect::Uart0 => val.set_uart_0_1x_clk_act(false),
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PeriphSelect::I2c1 => val.set_i2c_1_1x_clk_act(false),
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PeriphSelect::I2c0 => val.set_i2c_0_1x_clk_act(false),
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PeriphSelect::Can1 => val.set_can_1_1x_clk_act(false),
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PeriphSelect::Can0 => val.set_can_0_1x_clk_act(false),
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PeriphSelect::Spi1 => val.set_spi_1_1x_clk_act(false),
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PeriphSelect::Spi0 => val.set_spi_1_1x_clk_act(false),
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PeriphSelect::Sdio1 => val.set_sdio_1_1x_clk_act(false),
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PeriphSelect::Sdio0 => val.set_sdio_0_1x_clk_act(false),
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PeriphSelect::Gem1 => val.set_gem_1_1x_clk_act(false),
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PeriphSelect::Gem0 => val.set_gem_0_1x_clk_act(false),
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PeriphSelect::Usb1 => val.set_usb_1_cpu_1x_clk_act(false),
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PeriphSelect::Usb0 => val.set_usb_0_cpu_1x_clk_act(false),
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PeriphSelect::Dma => val.set_dma_cpu_2x_clk_act(false),
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}
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val
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})
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});
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}
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}
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#[inline]
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const fn spi_mode_const_to_cpol_cpha(
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mode: embedded_hal::spi::Mode,
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) -> (SpiClockPolarity, SpiClockPhase) {
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match mode {
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embedded_hal::spi::MODE_0 => (
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SpiClockPolarity::QuiescentLow,
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SpiClockPhase::ActiveOutsideOfWord,
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),
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embedded_hal::spi::MODE_1 => (
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SpiClockPolarity::QuiescentLow,
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SpiClockPhase::InactiveOutsideOfWord,
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),
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embedded_hal::spi::MODE_2 => (
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SpiClockPolarity::QuiescentHigh,
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SpiClockPhase::ActiveOutsideOfWord,
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),
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embedded_hal::spi::MODE_3 => (
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SpiClockPolarity::QuiescentHigh,
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SpiClockPhase::InactiveOutsideOfWord,
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),
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}
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}
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#[allow(dead_code)]
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pub(crate) mod sealed {
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pub trait Sealed {}
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}
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