86 lines
2.1 KiB
Rust
86 lines
2.1 KiB
Rust
//! RX buffer descriptor module.
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pub use super::Ownership;
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use arbitrary_int::{u2, u3, u13, u30};
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/// RX buffer descriptor.
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///
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/// The user should declare an array of this structure inside uncached memory.
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///
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/// These descriptors are shared between software and hardware and contain information
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/// related to frame reception.
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#[repr(C)]
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pub struct Descriptor {
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/// The first word of the descriptor.
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pub word0: Word0,
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/// The second word of the descriptor.
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pub word1: Word1,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug, PartialEq, Eq)]
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pub struct Word0 {
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/// The full reception address with the last two bits cleared.
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#[bits(2..=31, rw)]
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addr_upper_30_bits: u30,
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#[bit(1, rw)]
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wrap: bool,
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#[bit(0, rw)]
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ownership: Ownership,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug, PartialEq, Eq)]
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pub struct Word1 {
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#[bit(31, r)]
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broadcast_detect: bool,
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#[bit(30, r)]
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multicast_hash: bool,
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#[bit(29, r)]
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unicast_hash: bool,
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#[bit(27, r)]
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specific_addr_match: bool,
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/// Specifies which of the 4 specific address registers was matched.
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#[bits(25..=26, r)]
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specific_addr_match_info: u2,
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#[bit(24, r)]
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type_id_match_or_snap_info: bool,
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#[bits(22..=23, r)]
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type_id_match_info_or_chksum_status: u2,
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#[bit(21, r)]
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vlan_tag_detected: bool,
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#[bit(20, r)]
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priority_tag_detected: bool,
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#[bits(17..=19, r)]
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vlan_prio: u3,
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#[bit(16, r)]
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cfi_bit: bool,
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#[bit(15, r)]
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end_of_frame: bool,
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#[bit(14, r)]
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start_of_frame: bool,
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/// Relevant when FCS errors are not ignored.
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/// 0: Frame has good FCS, 1: Frame has bad FCS, but was copied to memory as the ignore FCS
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/// functionality was enabled.
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#[bit(13, r)]
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fcs_status: bool,
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#[bits(0..=12, r)]
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rx_len: u13,
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}
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impl Descriptor {
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#[inline]
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pub fn set_ownership(&mut self, ownership: Ownership) {
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self.word0.set_ownership(ownership);
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}
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#[inline]
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pub fn set_wrap_bit(&mut self) {
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self.word0.set_wrap(true);
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}
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#[inline]
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pub fn write_rx_addr(&mut self, addr: u32) {
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self.word0.set_addr_upper_30_bits(u30::new(addr >> 2));
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}
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}
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