97 lines
2.3 KiB
Rust
97 lines
2.3 KiB
Rust
use super::{RESET_BLOCK_OFFSET, SLCR_BASE_ADDR};
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct DualClockReset {
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/// Peripheral 1 AMBA software reset.
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#[bit(1, rw)]
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periph1_cpu1x_rst: bool,
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/// Peripheral 0 AMBA software reset.
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#[bit(0, rw)]
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periph0_cpu1x_rst: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct DualRefAndClockReset {
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/// Periperal 1 Reference software reset.
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#[bit(3, rw)]
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periph1_ref_rst: bool,
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/// Peripheral 0 Reference software reset.
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#[bit(2, rw)]
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periph0_ref_rst: bool,
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/// Peripheral 1 AMBA software reset.
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#[bit(1, rw)]
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periph1_cpu1x_rst: bool,
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/// Peripheral 0 AMBA software reset.
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#[bit(0, rw)]
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periph0_cpu1x_rst: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct GpioClockReset {
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#[bit(0, rw)]
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gpio_cpu1x_rst: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct EthernetReset {
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#[bit(5, rw)]
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gem1_ref_rst: bool,
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#[bit(4, rw)]
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gem0_ref_rst: bool,
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#[bit(3, rw)]
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gem1_rx_rst: bool,
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#[bit(2, rw)]
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gem0_rx_rst: bool,
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#[bit(1, rw)]
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gem1_cpu1x_rst: bool,
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#[bit(0, rw)]
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gem0_cpu1x_rst: bool,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct ResetControl {
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/// PS Software reset control
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pss: u32,
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ddr: u32,
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/// Central interconnect reset control
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topsw: u32,
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dmac: u32,
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usb: u32,
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eth: EthernetReset,
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sdio: DualRefAndClockReset,
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spi: DualRefAndClockReset,
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can: DualClockReset,
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i2c: DualClockReset,
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uart: DualRefAndClockReset,
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gpio: GpioClockReset,
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lqspi: u32,
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smc: u32,
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ocm: u32,
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_gap0: u32,
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fpga: u32,
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a9_cpu: u32,
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_gap1: u32,
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rs_awdt: u32,
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}
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impl ResetControl {
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/// Create a new handle to this peripheral.
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///
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/// Writing to this register requires unlocking the SLCR registers first.
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///
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/// # Safety
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///
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/// If you create multiple instances of this handle at the same time, you are responsible for
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/// ensuring that there are no read-modify-write races on any of the registers.
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pub unsafe fn new_mmio_fixed() -> MmioResetControl<'static> {
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unsafe { Self::new_mmio_at(SLCR_BASE_ADDR + RESET_BLOCK_OFFSET) }
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}
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<ResetControl>(), 0x50);
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