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282 lines
7.2 KiB
Rust
282 lines
7.2 KiB
Rust
use arbitrary_int::{u2, u3};
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pub use crate::{SpiClockPhase, SpiClockPolarity};
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pub const QSPI_BASE_ADDR: usize = 0xE000D000;
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum InterfaceMode {
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LegacySpi = 0,
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FlashMemoryInterface = 1,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum Endianness {
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Little = 0,
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Big = 1,
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}
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/// Baud rate divisor register values.
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#[bitbybit::bitenum(u3, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum BaudRateDivisor {
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_2 = 0b000,
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_4 = 0b001,
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_8 = 0b010,
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_16 = 0b011,
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_32 = 0b100,
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_64 = 0b101,
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_128 = 0b110,
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_256 = 0b111,
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}
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impl BaudRateDivisor {
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/// Actual divisor value.
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pub fn divisor(&self) -> usize {
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match self {
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BaudRateDivisor::_2 => 2,
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BaudRateDivisor::_4 => 4,
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BaudRateDivisor::_8 => 8,
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BaudRateDivisor::_16 => 16,
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BaudRateDivisor::_32 => 32,
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BaudRateDivisor::_64 => 64,
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BaudRateDivisor::_128 => 128,
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BaudRateDivisor::_256 => 256,
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}
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}
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}
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// TODO: Use bitbybit debug support as soon as support for write fields has been implemented.
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct Config {
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#[bit(31, rw)]
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interface_mode: InterfaceMode,
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#[bit(26, rw)]
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edianness: Endianness,
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#[bit(19, rw)]
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holdb_dr: bool,
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#[bit(16, w)]
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manual_start_command: bool,
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#[bit(15, rw)]
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manual_start_enable: bool,
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#[bit(14, rw)]
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manual_cs: bool,
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/// Directly drives the chip select line when CS is driven manually (bit 14 is set)
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#[bit(10, rw)]
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peripheral_chip_select: bool,
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/// The only valid value is 0b11 (32 bits)
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#[bits(6..=7, rw)]
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fifo_width: u2,
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#[bits(3..=5, rw)]
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baud_rate_div: BaudRateDivisor,
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#[bit(2, rw)]
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clock_phase: SpiClockPhase,
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#[bit(1, rw)]
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clock_polarity: SpiClockPolarity,
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/// Must be set to 1 before using QSPI, 0 is a reserved value.
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#[bit(0, rw)]
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mode_select: bool,
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}
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#[bitbybit::bitfield(u32, debug)]
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pub struct InterruptStatus {
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/// Write-to-clear bit.
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#[bit(6, rw)]
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tx_underflow: bool,
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#[bit(5, r)]
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rx_full: bool,
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#[bit(4, r)]
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rx_above_threshold: bool,
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#[bit(3, r)]
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tx_full: bool,
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#[bit(2, r)]
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tx_below_threshold: bool,
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/// Write-to-clear bit.
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#[bit(0, rw)]
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rx_overrun: bool,
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}
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#[bitbybit::bitfield(u32)]
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pub struct InterruptControl {
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#[bit(6, w)]
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tx_underflow: bool,
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#[bit(5, w)]
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rx_full: bool,
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#[bit(4, w)]
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rx_not_empty: bool,
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#[bit(3, w)]
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tx_full: bool,
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#[bit(2, w)]
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tx_not_full: bool,
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#[bit(0, w)]
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rx_overrun: bool,
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}
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#[bitbybit::bitfield(u32, debug)]
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pub struct InterruptMask {
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#[bit(6, r)]
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tx_underflow: bool,
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#[bit(5, r)]
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rx_full: bool,
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#[bit(4, r)]
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rx_not_empty: bool,
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#[bit(3, r)]
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tx_full: bool,
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#[bit(2, r)]
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tx_not_full: bool,
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#[bit(0, r)]
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rx_overrun: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0, debug)]
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pub struct SpiEnable {
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#[bit(0, rw)]
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enable: bool,
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}
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/// All the delays are in SPI reference block or external clock cycles.
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#[bitbybit::bitfield(u32, debug)]
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pub struct Delay {
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/// Length of the master mode chip select output de-asserts between words when CPHA = 0.
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#[bits(24..=31, rw)]
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deassert: u8,
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/// Delay between one chip select being de-activated and another being activated.
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#[bits(16..=23, rw)]
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between: u8,
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/// Length between last bit of current word and first bit of next word.
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#[bits(8..=15, rw)]
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after: u8,
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/// Delay between setting chip select low and first bit transfer.
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#[bits(0..=7, rw)]
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init: u8,
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}
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#[bitbybit::bitfield(u32)]
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pub struct Gpio {
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/// Active low write-protect bit.
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#[bit(0, rw)]
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write_protect_n: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0, debug)]
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pub struct LoopbackMasterClockDelay {
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/// Use internal loopback master clock for read data capturing when the baud rate divisor
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/// is 2.
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#[bit(5, rw)]
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use_loopback: bool,
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#[bits(3..=4,rw)]
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delay_1: u2,
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#[bits(0..=2 ,rw)]
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delay_0: u3,
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}
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#[bitbybit::bitenum(u8, exhaustive = false)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum InstructionCode {
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Read = 0x03,
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FastRead = 0x0B,
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FastReadDualOutput = 0x3B,
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FastReadQuadOutput = 0x6B,
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FastReadDualIo = 0xBB,
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FastReadQuadIo = 0xEB,
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}
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#[bitbybit::bitfield(u32, default = 0x0, debug)]
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pub struct LinearQspiConfig {
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#[bit(31, rw)]
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enable_linear_mode: bool,
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#[bit(30, rw)]
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both_memories: bool,
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/// Only has a meaning is bit 30 is set (both memories).
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#[bit(29, rw)]
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separate_memory_bus: bool,
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/// Upper memory page, if set. Only has a meaning if bit 30 is set and bit 29 / bit 31 are
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/// cleared.
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///
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/// In LQSPI mode, address bit 25 will indicate the lower (0) or upper (1) page.
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/// In IO mode, this bit selects the lower or upper memory.
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#[bit(28, rw)]
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upper_memory_page: bool,
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#[bit(25, rw)]
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mode_enable: bool,
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#[bit(24, rw)]
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mode_on: bool,
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#[bits(16..=23, rw)]
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mode_bits: u8,
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#[bits(8..=10, rw)]
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num_dummy_bytes: u3,
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#[bits(0..=7, rw)]
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instruction_code: Option<InstructionCode>,
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}
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#[bitbybit::bitfield(u32, debug)]
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pub struct LinearQspiStatus {
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#[bit(2, rw)]
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data_fsm_error: bool,
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#[bit(1, rw)]
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axi_write_command_received: bool,
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}
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/// QSPI register access.
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct Qspi {
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config: Config,
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interrupt_status: InterruptStatus,
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#[mmio(Write)]
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interrupt_enable: InterruptControl,
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#[mmio(Write)]
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interrupt_disable: InterruptControl,
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#[mmio(PureRead)]
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interupt_mask: InterruptMask,
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spi_enable: SpiEnable,
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delay: Delay,
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/// Transmits 1-byte command and 3-byte data OR 4-byte data.
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#[mmio(Write)]
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tx_data_00: u32,
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#[mmio(PureRead)]
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rx_data: u32,
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slave_idle_count: u32,
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/// Defines the level at which the TX FIFO not full interrupt is generated.
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tx_fifo_threshold: u32,
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/// Defines the level at which the RX FIFO not empty interrupt is generated.
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rx_fifo_threshold: u32,
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gpio: Gpio,
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_reserved0: u32,
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loopback_master_clock_delay: LoopbackMasterClockDelay,
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_reserved1: [u32; 0x11],
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/// Transmits 1-byte command.
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#[mmio(Write)]
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tx_data_01: u32,
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/// Transmits 1-byte command and 1-byte data.
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#[mmio(Write)]
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tx_data_10: u32,
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/// Transmits 1-byte command and 2-byte data.
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#[mmio(Write)]
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tx_data_11: u32,
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_reserved2: [u32; 0x5],
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linear_qspi_config: LinearQspiConfig,
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linear_qspi_status: LinearQspiStatus,
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_reserved3: [u32; 0x15],
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/// Module ID value with reset value 0x1090101.
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module_id: u32,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<Qspi>(), 0x100);
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impl Qspi {
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/// Create a new QSPI MMIO instance for for QSPI controller at address [QSPI_BASE_ADDR].
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed() -> MmioQspi<'static> {
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unsafe { Self::new_mmio_at(QSPI_BASE_ADDR) }
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}
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}
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