Robin Mueller
73fc553b18
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580 lines
13 KiB
Rust
580 lines
13 KiB
Rust
use arbitrary_int::{u2, u3, u4, u5, u6, u7, u10, u11, u12};
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pub const DDRC_BASE_ADDR: usize = 0xF800_6000;
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#[bitbybit::bitenum(u2)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum DataBusWidth {
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_32Bit = 0b00,
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_16Bit = 0b01,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum SoftReset {
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Reset = 0,
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Active = 1,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DdrcControl {
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#[bit(16, rw)]
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disable_auto_refresh: bool,
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#[bit(15, rw)]
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disable_active_bypass: bool,
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#[bit(14, rw)]
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disable_read_bypass: bool,
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#[bits(7..=13, rw)]
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read_write_idle_gap: u7,
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#[bits(4..=6, rw)]
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burst8_refresh: u3,
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#[bits(2..=3, rw)]
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data_bus_width: Option<DataBusWidth>,
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#[bit(1, rw)]
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power_down_enable: bool,
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#[bit(0, rw)]
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soft_reset: SoftReset,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct TwoRankConfig {
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#[bits(14..=18, rw)]
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addrmap_cs_bit0: u5,
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/// Reserved register, but for some reason, Xilinx tooling writes a 1 here?
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#[bits(12..=13, rw)]
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ddrc_active_ranks: u2,
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/// tREFI - Average time between refreshes, in multiples of 32 clocks.
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#[bits(0..=11, rw)]
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rfc_nom_x32: u12,
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}
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/// Queue control for the low priority and high priority read queues.
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct LprHprQueueControl {
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#[bits(22..=25, rw)]
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xact_run_length: u4,
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#[bits(11..=21, rw)]
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max_starve_x32: u11,
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#[bits(0..=10, rw)]
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min_non_critical_x32: u11,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct WriteQueueControl {
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#[bits(15..=25, rw)]
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max_starve_x32: u11,
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#[bits(11..=14, rw)]
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xact_run_length: u4,
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#[bits(0..=10, rw)]
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min_non_critical_x32: u11,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramParamReg0 {
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/// Minimum time to wait after coming out of self refresh before doing anything. This must be
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/// bigger than all the constraints that exist.
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#[bits(14..=20, rw)]
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post_selfref_gap_x32: u7,
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/// tRFC(min) - Minimum time from refresh to refresh or activate in clock
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/// cycles.
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#[bits(6..=13, rw)]
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t_rfc_min: u8,
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/// tRC - Min time between activates to the same bank.
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#[bits(0..=5, rw)]
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t_rc: u6,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramParamReg1 {
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#[bits(28..=31, rw)]
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t_cke: u4,
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#[bits(22..=26, rw)]
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t_ras_min: u5,
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#[bits(16..=21, rw)]
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t_ras_max: u6,
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#[bits(10..=15, rw)]
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t_faw: u6,
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#[bits(5..=9, rw)]
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powerdown_to_x32: u5,
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#[bits(0..=4, rw)]
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wr2pre: u5,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramParamReg2 {
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#[bits(28..=31, rw)]
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t_rcd: u4,
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#[bits(23..=27, rw)]
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rd2pre: u5,
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#[bits(20..=22, rw)]
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pad_pd: u3,
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#[bits(15..=19, rw)]
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t_xp: u5,
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#[bits(10..=14, rw)]
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wr2rd: u5,
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#[bits(5..=9, rw)]
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rd2wr: u5,
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#[bits(0..=4, rw)]
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write_latency: u5,
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}
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/// Weird naming.
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#[bitbybit::bitenum(u1, exhaustive = true)]
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pub enum MobileSetting {
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Ddr2Ddr3 = 0,
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Lpddr2 = 1,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramParamReg3 {
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#[bit(30, rw)]
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disable_pad_pd_feature: bool,
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#[bits(24..=28, rw)]
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read_latency: u5,
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#[bit(23, rw)]
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enable_dfi_dram_clk_disable: bool,
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/// 0: DDR2 or DDR3. 1: LPDDR2.
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#[bit(22, rw)]
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mobile: MobileSetting,
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/// Must be set to 0.
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#[bit(21, rw)]
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sdram: bool,
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#[bits(16..=20, rw)]
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refresh_to_x32: u5,
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#[bits(12..=15, rw)]
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t_rp: u4,
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#[bits(8..=11, rw)]
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refresh_margin: u4,
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#[bits(5..=7, rw)]
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t_rrd: u3,
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#[bits(2..=4, rw)]
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t_ccd: u3,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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pub enum ModeRegisterType {
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Write = 0,
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Read = 1,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramParamReg4 {
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#[bit(27, rw)]
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mr_rdata_valid: bool,
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#[bit(26, rw)]
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mr_type: ModeRegisterType,
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#[bit(25, rw)]
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mr_wr_busy: bool,
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#[bits(9..=24, rw)]
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mr_data: u16,
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#[bits(7..=8, rw)]
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mr_addr: u2,
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#[bit(6, rw)]
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mr_wr: bool,
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#[bit(1, rw)]
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prefer_write: bool,
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#[bit(0, rw)]
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enable_2t_timing_mode: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramInitParam {
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#[bits(11..=13, rw)]
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t_mrd: u3,
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#[bits(7..=10, rw)]
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pre_ocd_x32: u4,
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#[bits(0..=6, rw)]
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final_wait_x32: u7,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramEmr {
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#[bits(16..=31, rw)]
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emr3: u16,
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#[bits(0..=15, rw)]
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emr2: u16,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramEmrMr {
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#[bits(16..=31, rw)]
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emr: u16,
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#[bits(0..=15, rw)]
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mr: u16,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramBurst8ReadWrite {
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#[bits(0..=3, rw)]
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burst_rdwr: u4,
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#[bits(4..=13, rw)]
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pre_cke_x1024: u10,
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#[bits(16..=25, rw)]
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post_cke_x1024: u10,
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#[bit(26, rw)]
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burstchop: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DisableDq {
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#[bit(1, rw)]
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dis_dq: bool,
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#[bit(0, rw)]
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force_low_pri_n: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramAddrMapBank {
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#[bits(16..=19, rw)]
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addrmap_bank_b6: u4,
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#[bits(12..=15, rw)]
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addrmap_bank_b5: u4,
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#[bits(8..=11, rw)]
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addrmap_bank_b2: u4,
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#[bits(4..=7, rw)]
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addrmap_bank_b1: u4,
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#[bits(0..=3, rw)]
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addrmap_bank_b0: u4,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramAddrMapColumn {
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#[bits(28..=31, rw)]
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addrmap_col_b11: u4,
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#[bits(24..=27, rw)]
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addrmap_col_b10: u4,
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#[bits(20..=23, rw)]
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addrmap_col_b9: u4,
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#[bits(16..=19, rw)]
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addrmap_col_b8: u4,
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#[bits(12..=15, rw)]
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addrmap_col_b7: u4,
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#[bits(8..=11, rw)]
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addrmap_col_b4: u4,
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#[bits(4..=7, rw)]
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addrmap_col_b3: u4,
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#[bits(0..=3, rw)]
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addrmap_col_b2: u4,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramAddrMapRow {
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#[bits(24..=27, rw)]
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addrmap_row_b15: u4,
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#[bits(20..=23, rw)]
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addrmap_row_b14: u4,
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#[bits(16..=19, rw)]
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addrmap_row_b13: u4,
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#[bits(12..=15, rw)]
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addrmap_row_b12: u4,
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#[bits(8..=11, rw)]
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addrmap_row_b2_11: u4,
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#[bits(4..=7, rw)]
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addrmap_row_b1: u4,
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#[bits(0..=3, rw)]
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addrmap_row_b0: u4,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DramOdt {
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#[bits(16..=17, rw)]
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phy_idle_local_odt: u2,
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#[bits(14..=15, rw)]
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phy_write_local_odt: u2,
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#[bits(12..=13, rw)]
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phy_read_local_odt: u2,
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#[bits(3..=5, rw)]
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rank0_wr_odt: u3,
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#[bits(0..=2, rw)]
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rank0_rd_odt: u3,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct PhyCmdTimeoutRdDataCpt {
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#[bits(28..=31, rw)]
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wrlvl_num_of_dq0: u4,
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#[bits(24..=27, rw)]
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gatelvl_num_of_dq0: u4,
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#[bit(19, rw)]
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clk_stall_level: bool,
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#[bit(18, rw)]
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dis_phy_ctrl_rstn: bool,
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#[bit(17, rw)]
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rdc_fifo_rst_err_cnt_clr: bool,
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#[bit(16, rw)]
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use_fixed_re: bool,
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#[bits(8..=11, rw)]
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rdc_we_to_re_delay: u4,
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#[bits(4..=7, rw)]
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wr_cmd_to_data: u4,
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#[bits(0..=3, rw)]
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rd_cmd_to_data: u4,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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pub enum DllCalibSel {
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Periodic = 0,
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Manual = 1,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct DllCalib {
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#[bit(16, rw)]
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sel: DllCalibSel,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct OdtDelayHold {
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#[bits(12..=15, rw)]
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wr_odt_hold: u4,
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#[bits(8..=11, rw)]
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rd_odt_hold: u4,
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#[bits(4..=7, rw)]
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wr_odt_delay: u4,
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#[bits(0..=3, rw)]
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rd_odt_delay: u4,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CtrlReg1 {
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#[bit(12, rw)]
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selfref_enable: bool,
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#[bit(10, rw)]
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dis_collision_page_opt: bool,
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#[bit(9, rw)]
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dis_wc: bool,
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#[bit(8, rw)]
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refresh_update_level: bool,
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#[bit(7, rw)]
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auto_pre_en: bool,
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#[bits(1..=6, rw)]
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lpr_num_entries: u6,
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#[bit(0, rw)]
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pageclose: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CtrlReg2 {
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#[bit(17, rw)]
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go_2_critcal_enable: bool,
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#[bits(5..=12, rw)]
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go_2_critical_hysteresis: u8,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CtrlReg3 {
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#[bits(16..=25, rw)]
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dfi_t_wlmrd: u10,
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#[bits(8..=15, rw)]
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rdlvl_rr: u8,
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#[bits(0..=7, rw)]
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wrlvl_ww: u8,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CtrlReg4 {
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#[bits(8..=15, rw)]
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dfi_t_ctrlupd_interval_max_x1024: u8,
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#[bits(0..=7, rw)]
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dfi_t_ctrlupd_interval_min_x1024: u8,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CtrlReg5 {
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#[bits(20..=25, rw)]
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t_ckesr: u6,
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#[bits(16..=19, rw)]
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t_cksrx: u4,
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#[bits(12..=15, rw)]
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t_ckrse: u4,
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#[bits(8..=11, rw)]
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dfi_t_dram_clk_enable: u4,
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#[bits(4..=7, rw)]
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dfi_t_dram_clk_disable: u4,
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#[bits(0..=3, rw)]
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dfi_t_ctrl_delay: u4,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CtrlReg6 {
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#[bits(16..=19, rw)]
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t_cksx: u4,
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#[bits(12..=15, rw)]
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t_ckdpdx: u4,
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#[bits(8..=11, rw)]
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t_ckdpde: u4,
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#[bits(4..=7, rw)]
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t_ckpdx: u4,
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#[bits(0..=3, rw)]
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t_ckpde: u4,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct CheTZq {
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#[bits(22..=31, rw)]
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t_zq_short_nop: u10,
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#[bits(12..=21, rw)]
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t_zq_long_nop: u10,
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#[bits(2..=11, rw)]
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t_mode: u10,
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#[bit(1, rw)]
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ddr3: bool,
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#[bit(0, rw)]
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dis_auto_zq: bool,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct DdrController {
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ddrc_ctrl: DdrcControl,
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two_rank_cfg: TwoRankConfig,
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hpr_queue_ctrl: LprHprQueueControl,
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lpr_queue_ctrl: LprHprQueueControl,
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wr_reg: WriteQueueControl,
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dram_param_reg0: DramParamReg0,
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dram_param_reg1: DramParamReg1,
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dram_param_reg2: DramParamReg2,
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dram_param_reg3: DramParamReg3,
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dram_param_reg4: DramParamReg4,
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dram_init_param: DramInitParam,
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dram_emr: DramEmr,
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dram_emr_mr: DramEmrMr,
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dram_burst8_rdwr: DramBurst8ReadWrite,
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dram_disable_dq: DisableDq,
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dram_addr_map_bank: DramAddrMapBank,
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dram_addr_map_col: DramAddrMapColumn,
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dram_addr_map_row: DramAddrMapRow,
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dram_odt_reg: DramOdt,
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#[mmio(PureRead)]
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phy_debug_reg: u32,
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phy_cmd_timeout_rddata_cpt: PhyCmdTimeoutRdDataCpt,
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#[mmio(PureRead)]
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mode_status: u32,
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dll_calib: DllCalib,
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odt_delay_hold: u32,
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ctrl_reg1: CtrlReg1,
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ctrl_reg2: CtrlReg2,
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ctrl_reg3: CtrlReg3,
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ctrl_reg4: CtrlReg4,
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_reserved0: [u32; 0x2],
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ctrl_reg5: CtrlReg5,
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ctrl_reg6: CtrlReg6,
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_reserved1: [u32; 0x8],
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che_refresh_timer_01: u32,
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che_t_zq: CheTZq,
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che_t_zq_short_interval_reg: u32,
|
|
deep_powerdown_reg: u32,
|
|
reg_2c: u32,
|
|
reg_2d: u32,
|
|
dfi_timing: u32,
|
|
_reserved2: [u32; 0x2],
|
|
che_corr_control: u32,
|
|
#[mmio(PureRead)]
|
|
che_corr_ecc_log: u32,
|
|
#[mmio(PureRead)]
|
|
che_corr_ecc_addr: u32,
|
|
#[mmio(PureRead)]
|
|
che_corr_ecc_data_31_0: u32,
|
|
#[mmio(PureRead)]
|
|
che_corr_ecc_data_63_32: u32,
|
|
#[mmio(PureRead)]
|
|
che_corr_ecc_data_71_64: u32,
|
|
/// Clear on write, but the write is performed on another register.
|
|
#[mmio(PureRead)]
|
|
che_uncorr_ecc_log: u32,
|
|
#[mmio(PureRead)]
|
|
che_uncorr_ecc_addr: u32,
|
|
#[mmio(PureRead)]
|
|
che_uncorr_ecc_data_31_0: u32,
|
|
#[mmio(PureRead)]
|
|
che_uncorr_ecc_data_63_32: u32,
|
|
#[mmio(PureRead)]
|
|
che_uncorr_ecc_data_71_64: u32,
|
|
#[mmio(PureRead)]
|
|
che_ecc_stats: u32,
|
|
ecc_scrub: u32,
|
|
che_ecc_corr_bit_mask_31_0: u32,
|
|
che_ecc_corr_bit_mask_63_32: u32,
|
|
|
|
_reserved3: [u32; 0x5],
|
|
|
|
phy_receiver_enable: u32,
|
|
phy_config: [u32; 4],
|
|
_reserved4: u32,
|
|
phy_init_ratio: [u32; 4],
|
|
_reserved5: u32,
|
|
phy_rd_dqs_cfg: [u32; 4],
|
|
_reserved6: u32,
|
|
phy_wr_dqs_cfg: [u32; 4],
|
|
_reserved7: u32,
|
|
phy_we_cfg_0: [u32; 4],
|
|
_reserved8: u32,
|
|
wr_data_slave: [u32; 4],
|
|
|
|
_reserved9: u32,
|
|
|
|
reg_64: u32,
|
|
reg_65: u32,
|
|
_reserved10: [u32; 3],
|
|
#[mmio(PureRead)]
|
|
reg69_6a0: u32,
|
|
#[mmio(PureRead)]
|
|
reg69_6a1: u32,
|
|
_reserved11: u32,
|
|
#[mmio(PureRead)]
|
|
reg69_6d2: u32,
|
|
#[mmio(PureRead)]
|
|
reg69_6d3: u32,
|
|
#[mmio(PureRead)]
|
|
reg69_710: u32,
|
|
#[mmio(PureRead)]
|
|
reg6e_711: u32,
|
|
#[mmio(PureRead)]
|
|
reg6e_712: u32,
|
|
#[mmio(PureRead)]
|
|
reg6e_713: u32,
|
|
_reserved12: u32,
|
|
#[mmio(PureRead)]
|
|
phy_dll_status: [u32; 4],
|
|
_reserved13: u32,
|
|
#[mmio(PureRead)]
|
|
dll_lock_status: u32,
|
|
#[mmio(PureRead)]
|
|
phy_control_status: u32,
|
|
#[mmio(PureRead)]
|
|
phy_control_status_2: u32,
|
|
|
|
_reserved14: [u32; 0x5],
|
|
|
|
// DDRI registers.
|
|
#[mmio(PureRead)]
|
|
axi_id: u32,
|
|
page_mask: u32,
|
|
axi_priority_wr_port: [u32; 4],
|
|
axi_priority_rd_port: [u32; 4],
|
|
|
|
_reserved15: [u32; 0x1B],
|
|
|
|
excl_access_cfg: [u32; 4],
|
|
#[mmio(PureRead)]
|
|
mode_reg_read: u32,
|
|
lpddr_ctrl_0: u32,
|
|
lpddr_ctrl_1: u32,
|
|
lpddr_ctrl_2: u32,
|
|
lpddr_ctrl_3: u32,
|
|
}
|
|
|
|
static_assertions::const_assert_eq!(core::mem::size_of::<DdrController>(), 0x2B8);
|
|
|
|
impl DdrController {
|
|
/// Create a new DDR MMIO instance for the DDR controller at address [DDRC_BASE_ADDR].
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// This API can be used to potentially create a driver to the same peripheral structure
|
|
/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
|
|
/// interfere with each other.
|
|
pub const unsafe fn new_mmio_fixed() -> MmioDdrController<'static> {
|
|
unsafe { Self::new_mmio_at(DDRC_BASE_ADDR) }
|
|
}
|
|
}
|